tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/clk_freqs.h

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #ifndef MBED_CLK_FREQS_H
  17 #define MBED_CLK_FREQS_H
  18
  19 #ifdef __cplusplus
  20 extern "C" {
  21 #endif
  22
  23 #include "PeripheralPins.h"
  24
  25 //Get the peripheral bus clock frequency
  26 static inline uint32_t bus_frequency(void) {
  27     return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
  28 }
  29
  30 #if defined(TARGET_KL43Z)
  31
  32 static inline uint32_t extosc_frequency(void) {
  33     return CPU_XTAL_CLK_HZ;
  34 }
  35
  36 static inline uint32_t fastirc_frequency(void) {
  37     return CPU_INT_FAST_CLK_HZ;
  38 }
  39
  40 static inline uint32_t mcgirc_frequency(void) {
  41     uint32_t mcgirc_clock = 0;
  42
  43     if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
  44         mcgirc_clock  = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
  45         mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
  46         mcgirc_clock /= 1u +  (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
  47     }
  48
  49     return mcgirc_clock;
  50 }
  51
  52 #else
  53
  54 //Get external oscillator (crystal) frequency
  55 static uint32_t extosc_frequency(void) {
  56     uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
  57
  58     if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2))     //MCG clock = external reference clock
  59         return MCGClock;
  60
  61     uint32_t divider, multiplier;
  62     #ifdef MCG_C5_PLLCLKEN0_MASK                            //PLL available
  63     if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) {   //PLL/FLL is selected
  64         if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
  65     #endif
  66             if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) {     //FLL uses external reference
  67                 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
  68                 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
  69                     divider <<= 5u;
  70                 /* Select correct multiplier to calculate the MCG output clock  */
  71                 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
  72                     case 0x0u:
  73                       multiplier = 640u;
  74                       break;
  75                     case 0x20u:
  76                       multiplier = 1280u;
  77                       break;
  78                     case 0x40u:
  79                       multiplier = 1920u;
  80                       break;
  81                     case 0x60u:
  82                       multiplier = 2560u;
  83                       break;
  84                     case 0x80u:
  85                       multiplier = 732u;
  86                       break;
  87                     case 0xA0u:
  88                       multiplier = 1464u;
  89                       break;
  90                     case 0xC0u:
  91                       multiplier = 2197u;
  92                       break;
  93                     case 0xE0u:
  94                     default:
  95                       multiplier = 2929u;
  96                       break;
  97                 }
  98
  99                 return MCGClock * divider / multiplier;
 100             }
 101     #ifdef MCG_C5_PLLCLKEN0_MASK
 102         } else {             //PLL is selected
 103             divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
 104             multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
 105             return MCGClock * divider / multiplier;
 106         }
 107     }
 108     #endif
 109
 110     //In all other cases either there is no crystal or we cannot determine it
 111     //For example when the FLL is running on the internal reference, and there is also an
 112     //external crystal. However these are unlikely situations
 113     return 0;
 114 }
 115
 116 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
 117 static uint32_t mcgpllfll_frequency(void) {
 118     if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0))   //PLL/FLL is not selected
 119         return 0;
 120
 121     uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
 122     #ifdef MCG_C5_PLLCLKEN0_MASK
 123     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
 124         SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;        //MCG peripheral clock is FLL output
 125     #endif
 126         return MCGClock;
 127     #ifdef MCG_C5_PLLCLKEN0_MASK
 128     } else {                                            //PLL is selected
 129         SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;         //MCG peripheral clock is PLL output
 130         return (MCGClock >> 1);
 131     }
 132     #endif
 133
 134     //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
 135     //for the peripherals, this is however an unlikely setup
 136 }
 137
 138 #endif
 139
 140 #ifdef __cplusplus
 141 }
 142 #endif
 143
 144 #endif