tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_DMAMUX_REGISTERS_H__
  78 #define __HW_DMAMUX_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 DMAMUX
  85  *
  86  * DMA channel multiplexor
  87  *
  88  * Registers defined in this header file:
  89  * - HW_DMAMUX_CHCFGn - Channel Configuration register
  90  *
  91  * - hw_dmamux_t - Struct containing all module registers.
  92  */
  93
  94 #define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
  95
  96 /*******************************************************************************
  97  * HW_DMAMUX_CHCFGn - Channel Configuration register
  98  ******************************************************************************/
  99
 100 /*!
 101  * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
 102  *
 103  * Reset value: 0x00U
 104  *
 105  * Each of the DMA channels can be independently enabled/disabled and associated
 106  * with one of the DMA slots (peripheral slots or always-on slots) in the
 107  * system. Setting multiple CHCFG registers with the same source value will result in
 108  * unpredictable behavior. Before changing the trigger or source settings, a DMA
 109  * channel must be disabled via CHCFGn[ENBL].
 110  */
 111 typedef union _hw_dmamux_chcfgn
 112 {
 113     uint8_t U;
 114     struct _hw_dmamux_chcfgn_bitfields
 115     {
 116         uint8_t SOURCE : 6;            /*!< [5:0] DMA Channel Source (Slot) */
 117         uint8_t TRIG : 1;              /*!< [6] DMA Channel Trigger Enable */
 118         uint8_t ENBL : 1;              /*!< [7] DMA Channel Enable */
 119     } B;
 120 } hw_dmamux_chcfgn_t;
 121
 122 /*!
 123  * @name Constants and macros for entire DMAMUX_CHCFGn register
 124  */
 125 /*@{*/
 126 #define HW_DMAMUX_CHCFGn_COUNT (16U)
 127
 128 #define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
 129
 130 #define HW_DMAMUX_CHCFGn(x, n)   (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
 131 #define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
 132 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
 133 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) |  (v)))
 134 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
 135 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^  (v)))
 136 /*@}*/
 137
 138 /*
 139  * Constants & macros for individual DMAMUX_CHCFGn bitfields
 140  */
 141
 142 /*!
 143  * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
 144  *
 145  * Specifies which DMA source, if any, is routed to a particular DMA channel.
 146  * See your device's chip configuration details for information about the
 147  * peripherals and their slot numbers.
 148  */
 149 /*@{*/
 150 #define BP_DMAMUX_CHCFGn_SOURCE (0U)       /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
 151 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU)    /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
 152 #define BS_DMAMUX_CHCFGn_SOURCE (6U)       /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
 153
 154 /*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
 155 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
 156
 157 /*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
 158 #define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
 159
 160 /*! @brief Set the SOURCE field to a new value. */
 161 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
 162 /*@}*/
 163
 164 /*!
 165  * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
 166  *
 167  * Enables the periodic trigger capability for the triggered DMA channel.
 168  *
 169  * Values:
 170  * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
 171  *     DMA Channel will simply route the specified source to the DMA channel.
 172  *     (Normal mode)
 173  * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
 174  *     DMAMUX is in Periodic Trigger mode.
 175  */
 176 /*@{*/
 177 #define BP_DMAMUX_CHCFGn_TRIG (6U)         /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
 178 #define BM_DMAMUX_CHCFGn_TRIG (0x40U)      /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
 179 #define BS_DMAMUX_CHCFGn_TRIG (1U)         /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
 180
 181 /*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
 182 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
 183
 184 /*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
 185 #define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
 186
 187 /*! @brief Set the TRIG field to a new value. */
 188 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
 189 /*@}*/
 190
 191 /*!
 192  * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
 193  *
 194  * Enables the DMA channel.
 195  *
 196  * Values:
 197  * - 0 - DMA channel is disabled. This mode is primarily used during
 198  *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
 199  *     should be used to disable or reconfigure a DMA channel.
 200  * - 1 - DMA channel is enabled
 201  */
 202 /*@{*/
 203 #define BP_DMAMUX_CHCFGn_ENBL (7U)         /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
 204 #define BM_DMAMUX_CHCFGn_ENBL (0x80U)      /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
 205 #define BS_DMAMUX_CHCFGn_ENBL (1U)         /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
 206
 207 /*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
 208 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
 209
 210 /*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
 211 #define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
 212
 213 /*! @brief Set the ENBL field to a new value. */
 214 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
 215 /*@}*/
 216
 217 /*******************************************************************************
 218  * hw_dmamux_t - module struct
 219  ******************************************************************************/
 220 /*!
 221  * @brief All DMAMUX module registers.
 222  */
 223 #pragma pack(1)
 224 typedef struct _hw_dmamux
 225 {
 226     __IO hw_dmamux_chcfgn_t CHCFGn[16];    /*!< [0x0] Channel Configuration register */
 227 } hw_dmamux_t;
 228 #pragma pack()
 229
 230 /*! @brief Macro to access all DMAMUX registers. */
 231 /*! @param x DMAMUX module instance base address. */
 232 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 233  *     use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
 234 #define HW_DMAMUX(x)   (*(hw_dmamux_t *)(x))
 235
 236 #endif /* __HW_DMAMUX_REGISTERS_H__ */
 237 /* EOF */