tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_EWM_REGISTERS_H__
  78 #define __HW_EWM_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 EWM
  85  *
  86  * External Watchdog Monitor
  87  *
  88  * Registers defined in this header file:
  89  * - HW_EWM_CTRL - Control Register
  90  * - HW_EWM_SERV - Service Register
  91  * - HW_EWM_CMPL - Compare Low Register
  92  * - HW_EWM_CMPH - Compare High Register
  93  * - HW_EWM_CLKPRESCALER - Clock Prescaler Register
  94  *
  95  * - hw_ewm_t - Struct containing all module registers.
  96  */
  97
  98 #define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
  99
 100 /*******************************************************************************
 101  * HW_EWM_CTRL - Control Register
 102  ******************************************************************************/
 103
 104 /*!
 105  * @brief HW_EWM_CTRL - Control Register (RW)
 106  *
 107  * Reset value: 0x00U
 108  *
 109  * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
 110  * written once after a CPU reset. Modifying these bits more than once, generates
 111  * a bus transfer error.
 112  */
 113 typedef union _hw_ewm_ctrl
 114 {
 115     uint8_t U;
 116     struct _hw_ewm_ctrl_bitfields
 117     {
 118         uint8_t EWMEN : 1;             /*!< [0] EWM enable. */
 119         uint8_t ASSIN : 1;             /*!< [1] EWM_in's Assertion State Select. */
 120         uint8_t INEN : 1;              /*!< [2] Input Enable. */
 121         uint8_t INTEN : 1;             /*!< [3] Interrupt Enable. */
 122         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
 123     } B;
 124 } hw_ewm_ctrl_t;
 125
 126 /*!
 127  * @name Constants and macros for entire EWM_CTRL register
 128  */
 129 /*@{*/
 130 #define HW_EWM_CTRL_ADDR(x)      ((x) + 0x0U)
 131
 132 #define HW_EWM_CTRL(x)           (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
 133 #define HW_EWM_CTRL_RD(x)        (HW_EWM_CTRL(x).U)
 134 #define HW_EWM_CTRL_WR(x, v)     (HW_EWM_CTRL(x).U = (v))
 135 #define HW_EWM_CTRL_SET(x, v)    (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) |  (v)))
 136 #define HW_EWM_CTRL_CLR(x, v)    (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
 137 #define HW_EWM_CTRL_TOG(x, v)    (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^  (v)))
 138 /*@}*/
 139
 140 /*
 141  * Constants & macros for individual EWM_CTRL bitfields
 142  */
 143
 144 /*!
 145  * @name Register EWM_CTRL, field EWMEN[0] (RW)
 146  *
 147  * This bit when set, enables the EWM module. This resets the EWM counter to
 148  * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
 149  * therefore it cannot be enabled until a reset occurs, due to the write-once
 150  * nature of this bit.
 151  */
 152 /*@{*/
 153 #define BP_EWM_CTRL_EWMEN    (0U)          /*!< Bit position for EWM_CTRL_EWMEN. */
 154 #define BM_EWM_CTRL_EWMEN    (0x01U)       /*!< Bit mask for EWM_CTRL_EWMEN. */
 155 #define BS_EWM_CTRL_EWMEN    (1U)          /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
 156
 157 /*! @brief Read current value of the EWM_CTRL_EWMEN field. */
 158 #define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN))
 159
 160 /*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
 161 #define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
 162
 163 /*! @brief Set the EWMEN field to a new value. */
 164 #define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v))
 165 /*@}*/
 166
 167 /*!
 168  * @name Register EWM_CTRL, field ASSIN[1] (RW)
 169  *
 170  * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
 171  * inverts the assert state to a logic one.
 172  */
 173 /*@{*/
 174 #define BP_EWM_CTRL_ASSIN    (1U)          /*!< Bit position for EWM_CTRL_ASSIN. */
 175 #define BM_EWM_CTRL_ASSIN    (0x02U)       /*!< Bit mask for EWM_CTRL_ASSIN. */
 176 #define BS_EWM_CTRL_ASSIN    (1U)          /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
 177
 178 /*! @brief Read current value of the EWM_CTRL_ASSIN field. */
 179 #define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN))
 180
 181 /*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
 182 #define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
 183
 184 /*! @brief Set the ASSIN field to a new value. */
 185 #define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v))
 186 /*@}*/
 187
 188 /*!
 189  * @name Register EWM_CTRL, field INEN[2] (RW)
 190  *
 191  * This bit when set, enables the EWM_in port.
 192  */
 193 /*@{*/
 194 #define BP_EWM_CTRL_INEN     (2U)          /*!< Bit position for EWM_CTRL_INEN. */
 195 #define BM_EWM_CTRL_INEN     (0x04U)       /*!< Bit mask for EWM_CTRL_INEN. */
 196 #define BS_EWM_CTRL_INEN     (1U)          /*!< Bit field size in bits for EWM_CTRL_INEN. */
 197
 198 /*! @brief Read current value of the EWM_CTRL_INEN field. */
 199 #define BR_EWM_CTRL_INEN(x)  (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN))
 200
 201 /*! @brief Format value for bitfield EWM_CTRL_INEN. */
 202 #define BF_EWM_CTRL_INEN(v)  ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
 203
 204 /*! @brief Set the INEN field to a new value. */
 205 #define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v))
 206 /*@}*/
 207
 208 /*!
 209  * @name Register EWM_CTRL, field INTEN[3] (RW)
 210  *
 211  * This bit when set and EWM_out is asserted, an interrupt request is generated.
 212  * To de-assert interrupt request, user should clear this bit by writing 0.
 213  */
 214 /*@{*/
 215 #define BP_EWM_CTRL_INTEN    (3U)          /*!< Bit position for EWM_CTRL_INTEN. */
 216 #define BM_EWM_CTRL_INTEN    (0x08U)       /*!< Bit mask for EWM_CTRL_INTEN. */
 217 #define BS_EWM_CTRL_INTEN    (1U)          /*!< Bit field size in bits for EWM_CTRL_INTEN. */
 218
 219 /*! @brief Read current value of the EWM_CTRL_INTEN field. */
 220 #define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN))
 221
 222 /*! @brief Format value for bitfield EWM_CTRL_INTEN. */
 223 #define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
 224
 225 /*! @brief Set the INTEN field to a new value. */
 226 #define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v))
 227 /*@}*/
 228
 229 /*******************************************************************************
 230  * HW_EWM_SERV - Service Register
 231  ******************************************************************************/
 232
 233 /*!
 234  * @brief HW_EWM_SERV - Service Register (WORZ)
 235  *
 236  * Reset value: 0x00U
 237  *
 238  * The SERV register provides the interface from the CPU to the EWM module. It
 239  * is write-only and reads of this register return zero.
 240  */
 241 typedef union _hw_ewm_serv
 242 {
 243     uint8_t U;
 244     struct _hw_ewm_serv_bitfields
 245     {
 246         uint8_t SERVICE : 8;           /*!< [7:0]  */
 247     } B;
 248 } hw_ewm_serv_t;
 249
 250 /*!
 251  * @name Constants and macros for entire EWM_SERV register
 252  */
 253 /*@{*/
 254 #define HW_EWM_SERV_ADDR(x)      ((x) + 0x1U)
 255
 256 #define HW_EWM_SERV(x)           (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
 257 #define HW_EWM_SERV_RD(x)        (HW_EWM_SERV(x).U)
 258 #define HW_EWM_SERV_WR(x, v)     (HW_EWM_SERV(x).U = (v))
 259 /*@}*/
 260
 261 /*
 262  * Constants & macros for individual EWM_SERV bitfields
 263  */
 264
 265 /*!
 266  * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
 267  *
 268  * The EWM service mechanism requires the CPU to write two values to the SERV
 269  * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
 270  * EWM service is illegal if either of the following conditions is true. The
 271  * first or second data byte is not written correctly. The second data byte is not
 272  * written within a fixed number of peripheral bus cycles of the first data byte.
 273  * This fixed number of cycles is called EWM_service_time.
 274  */
 275 /*@{*/
 276 #define BP_EWM_SERV_SERVICE  (0U)          /*!< Bit position for EWM_SERV_SERVICE. */
 277 #define BM_EWM_SERV_SERVICE  (0xFFU)       /*!< Bit mask for EWM_SERV_SERVICE. */
 278 #define BS_EWM_SERV_SERVICE  (8U)          /*!< Bit field size in bits for EWM_SERV_SERVICE. */
 279
 280 /*! @brief Format value for bitfield EWM_SERV_SERVICE. */
 281 #define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
 282
 283 /*! @brief Set the SERVICE field to a new value. */
 284 #define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
 285 /*@}*/
 286
 287 /*******************************************************************************
 288  * HW_EWM_CMPL - Compare Low Register
 289  ******************************************************************************/
 290
 291 /*!
 292  * @brief HW_EWM_CMPL - Compare Low Register (RW)
 293  *
 294  * Reset value: 0x00U
 295  *
 296  * The CMPL register is reset to zero after a CPU reset. This provides no
 297  * minimum time for the CPU to service the EWM counter. This register can be written
 298  * only once after a CPU reset. Writing this register more than once generates a
 299  * bus transfer error.
 300  */
 301 typedef union _hw_ewm_cmpl
 302 {
 303     uint8_t U;
 304     struct _hw_ewm_cmpl_bitfields
 305     {
 306         uint8_t COMPAREL : 8;          /*!< [7:0]  */
 307     } B;
 308 } hw_ewm_cmpl_t;
 309
 310 /*!
 311  * @name Constants and macros for entire EWM_CMPL register
 312  */
 313 /*@{*/
 314 #define HW_EWM_CMPL_ADDR(x)      ((x) + 0x2U)
 315
 316 #define HW_EWM_CMPL(x)           (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
 317 #define HW_EWM_CMPL_RD(x)        (HW_EWM_CMPL(x).U)
 318 #define HW_EWM_CMPL_WR(x, v)     (HW_EWM_CMPL(x).U = (v))
 319 #define HW_EWM_CMPL_SET(x, v)    (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) |  (v)))
 320 #define HW_EWM_CMPL_CLR(x, v)    (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
 321 #define HW_EWM_CMPL_TOG(x, v)    (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^  (v)))
 322 /*@}*/
 323
 324 /*
 325  * Constants & macros for individual EWM_CMPL bitfields
 326  */
 327
 328 /*!
 329  * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
 330  *
 331  * To prevent runaway code from changing this field, software should write to
 332  * this field after a CPU reset even if the (default) minimum service time is
 333  * required.
 334  */
 335 /*@{*/
 336 #define BP_EWM_CMPL_COMPAREL (0U)          /*!< Bit position for EWM_CMPL_COMPAREL. */
 337 #define BM_EWM_CMPL_COMPAREL (0xFFU)       /*!< Bit mask for EWM_CMPL_COMPAREL. */
 338 #define BS_EWM_CMPL_COMPAREL (8U)          /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
 339
 340 /*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
 341 #define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
 342
 343 /*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
 344 #define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
 345
 346 /*! @brief Set the COMPAREL field to a new value. */
 347 #define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
 348 /*@}*/
 349
 350 /*******************************************************************************
 351  * HW_EWM_CMPH - Compare High Register
 352  ******************************************************************************/
 353
 354 /*!
 355  * @brief HW_EWM_CMPH - Compare High Register (RW)
 356  *
 357  * Reset value: 0xFFU
 358  *
 359  * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
 360  * of 256 clocks time, for the CPU to service the EWM counter. This register can
 361  * be written only once after a CPU reset. Writing this register more than once
 362  * generates a bus transfer error. The valid values for CMPH are up to 0xFE
 363  * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
 364  * if EWM counter is greater than CMPH.
 365  */
 366 typedef union _hw_ewm_cmph
 367 {
 368     uint8_t U;
 369     struct _hw_ewm_cmph_bitfields
 370     {
 371         uint8_t COMPAREH : 8;          /*!< [7:0]  */
 372     } B;
 373 } hw_ewm_cmph_t;
 374
 375 /*!
 376  * @name Constants and macros for entire EWM_CMPH register
 377  */
 378 /*@{*/
 379 #define HW_EWM_CMPH_ADDR(x)      ((x) + 0x3U)
 380
 381 #define HW_EWM_CMPH(x)           (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
 382 #define HW_EWM_CMPH_RD(x)        (HW_EWM_CMPH(x).U)
 383 #define HW_EWM_CMPH_WR(x, v)     (HW_EWM_CMPH(x).U = (v))
 384 #define HW_EWM_CMPH_SET(x, v)    (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) |  (v)))
 385 #define HW_EWM_CMPH_CLR(x, v)    (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
 386 #define HW_EWM_CMPH_TOG(x, v)    (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^  (v)))
 387 /*@}*/
 388
 389 /*
 390  * Constants & macros for individual EWM_CMPH bitfields
 391  */
 392
 393 /*!
 394  * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
 395  *
 396  * To prevent runaway code from changing this field, software should write to
 397  * this field after a CPU reset even if the (default) maximum service time is
 398  * required.
 399  */
 400 /*@{*/
 401 #define BP_EWM_CMPH_COMPAREH (0U)          /*!< Bit position for EWM_CMPH_COMPAREH. */
 402 #define BM_EWM_CMPH_COMPAREH (0xFFU)       /*!< Bit mask for EWM_CMPH_COMPAREH. */
 403 #define BS_EWM_CMPH_COMPAREH (8U)          /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
 404
 405 /*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
 406 #define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
 407
 408 /*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
 409 #define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
 410
 411 /*! @brief Set the COMPAREH field to a new value. */
 412 #define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
 413 /*@}*/
 414
 415 /*******************************************************************************
 416  * HW_EWM_CLKPRESCALER - Clock Prescaler Register
 417  ******************************************************************************/
 418
 419 /*!
 420  * @brief HW_EWM_CLKPRESCALER - Clock Prescaler Register (RW)
 421  *
 422  * Reset value: 0x00U
 423  *
 424  * This CLKPRESCALER register is reset to 0x00 after a CPU reset. This register
 425  * can be written only once after a CPU reset. Writing this register more than
 426  * once generates a bus transfer error. Write the required prescaler value before
 427  * enabling the EWM. The implementation of this register is chip-specific. See the
 428  * Chip Configuration details.
 429  */
 430 typedef union _hw_ewm_clkprescaler
 431 {
 432     uint8_t U;
 433     struct _hw_ewm_clkprescaler_bitfields
 434     {
 435         uint8_t CLK_DIV : 8;           /*!< [7:0]  */
 436     } B;
 437 } hw_ewm_clkprescaler_t;
 438
 439 /*!
 440  * @name Constants and macros for entire EWM_CLKPRESCALER register
 441  */
 442 /*@{*/
 443 #define HW_EWM_CLKPRESCALER_ADDR(x) ((x) + 0x5U)
 444
 445 #define HW_EWM_CLKPRESCALER(x)   (*(__IO hw_ewm_clkprescaler_t *) HW_EWM_CLKPRESCALER_ADDR(x))
 446 #define HW_EWM_CLKPRESCALER_RD(x) (HW_EWM_CLKPRESCALER(x).U)
 447 #define HW_EWM_CLKPRESCALER_WR(x, v) (HW_EWM_CLKPRESCALER(x).U = (v))
 448 #define HW_EWM_CLKPRESCALER_SET(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) |  (v)))
 449 #define HW_EWM_CLKPRESCALER_CLR(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) & ~(v)))
 450 #define HW_EWM_CLKPRESCALER_TOG(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) ^  (v)))
 451 /*@}*/
 452
 453 /*
 454  * Constants & macros for individual EWM_CLKPRESCALER bitfields
 455  */
 456
 457 /*!
 458  * @name Register EWM_CLKPRESCALER, field CLK_DIV[7:0] (RW)
 459  *
 460  * Selected low power source for running the EWM counter can be prescaled as
 461  * below. Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK_DIV
 462  * )
 463  */
 464 /*@{*/
 465 #define BP_EWM_CLKPRESCALER_CLK_DIV (0U)   /*!< Bit position for EWM_CLKPRESCALER_CLK_DIV. */
 466 #define BM_EWM_CLKPRESCALER_CLK_DIV (0xFFU) /*!< Bit mask for EWM_CLKPRESCALER_CLK_DIV. */
 467 #define BS_EWM_CLKPRESCALER_CLK_DIV (8U)   /*!< Bit field size in bits for EWM_CLKPRESCALER_CLK_DIV. */
 468
 469 /*! @brief Read current value of the EWM_CLKPRESCALER_CLK_DIV field. */
 470 #define BR_EWM_CLKPRESCALER_CLK_DIV(x) (HW_EWM_CLKPRESCALER(x).U)
 471
 472 /*! @brief Format value for bitfield EWM_CLKPRESCALER_CLK_DIV. */
 473 #define BF_EWM_CLKPRESCALER_CLK_DIV(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CLKPRESCALER_CLK_DIV) & BM_EWM_CLKPRESCALER_CLK_DIV)
 474
 475 /*! @brief Set the CLK_DIV field to a new value. */
 476 #define BW_EWM_CLKPRESCALER_CLK_DIV(x, v) (HW_EWM_CLKPRESCALER_WR(x, v))
 477 /*@}*/
 478
 479 /*******************************************************************************
 480  * hw_ewm_t - module struct
 481  ******************************************************************************/
 482 /*!
 483  * @brief All EWM module registers.
 484  */
 485 #pragma pack(1)
 486 typedef struct _hw_ewm
 487 {
 488     __IO hw_ewm_ctrl_t CTRL;               /*!< [0x0] Control Register */
 489     __O hw_ewm_serv_t SERV;                /*!< [0x1] Service Register */
 490     __IO hw_ewm_cmpl_t CMPL;               /*!< [0x2] Compare Low Register */
 491     __IO hw_ewm_cmph_t CMPH;               /*!< [0x3] Compare High Register */
 492     uint8_t _reserved0[1];
 493     __IO hw_ewm_clkprescaler_t CLKPRESCALER; /*!< [0x5] Clock Prescaler Register */
 494 } hw_ewm_t;
 495 #pragma pack()
 496
 497 /*! @brief Macro to access all EWM registers. */
 498 /*! @param x EWM module instance base address. */
 499 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 500  *     use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
 501 #define HW_EWM(x)      (*(hw_ewm_t *)(x))
 502
 503 #endif /* __HW_EWM_REGISTERS_H__ */
 504 /* EOF */