2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_FMC_REGISTERS_H__
78 #define __HW_FMC_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Flash Memory Controller
88 * Registers defined in this header file:
89 * - HW_FMC_PFAPR - Flash Access Protection Register
90 * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
91 * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
92 * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
93 * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
94 * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
95 * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
96 * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
97 * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
98 * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
99 * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
100 * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
101 * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
102 * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
103 * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
105 * - hw_fmc_t - Struct containing all module registers.
108 #define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
110 /*******************************************************************************
111 * HW_FMC_PFAPR - Flash Access Protection Register
112 ******************************************************************************/
115 * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
117 * Reset value: 0x00F8003FU
119 typedef union _hw_fmc_pfapr
122 struct _hw_fmc_pfapr_bitfields
124 uint32_t M0AP
: 2; /*!< [1:0] Master 0 Access Protection */
125 uint32_t M1AP
: 2; /*!< [3:2] Master 1 Access Protection */
126 uint32_t M2AP
: 2; /*!< [5:4] Master 2 Access Protection */
127 uint32_t M3AP
: 2; /*!< [7:6] Master 3 Access Protection */
128 uint32_t M4AP
: 2; /*!< [9:8] Master 4 Access Protection */
129 uint32_t M5AP
: 2; /*!< [11:10] Master 5 Access Protection */
130 uint32_t M6AP
: 2; /*!< [13:12] Master 6 Access Protection */
131 uint32_t M7AP
: 2; /*!< [15:14] Master 7 Access Protection */
132 uint32_t M0PFD
: 1; /*!< [16] Master 0 Prefetch Disable */
133 uint32_t M1PFD
: 1; /*!< [17] Master 1 Prefetch Disable */
134 uint32_t M2PFD
: 1; /*!< [18] Master 2 Prefetch Disable */
135 uint32_t M3PFD
: 1; /*!< [19] Master 3 Prefetch Disable */
136 uint32_t M4PFD
: 1; /*!< [20] Master 4 Prefetch Disable */
137 uint32_t M5PFD
: 1; /*!< [21] Master 5 Prefetch Disable */
138 uint32_t M6PFD
: 1; /*!< [22] Master 6 Prefetch Disable */
139 uint32_t M7PFD
: 1; /*!< [23] Master 7 Prefetch Disable */
140 uint32_t RESERVED0
: 8; /*!< [31:24] */
145 * @name Constants and macros for entire FMC_PFAPR register
148 #define HW_FMC_PFAPR_ADDR(x) ((x) + 0x0U)
150 #define HW_FMC_PFAPR(x) (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x))
151 #define HW_FMC_PFAPR_RD(x) (HW_FMC_PFAPR(x).U)
152 #define HW_FMC_PFAPR_WR(x, v) (HW_FMC_PFAPR(x).U = (v))
153 #define HW_FMC_PFAPR_SET(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) | (v)))
154 #define HW_FMC_PFAPR_CLR(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v)))
155 #define HW_FMC_PFAPR_TOG(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^ (v)))
159 * Constants & macros for individual FMC_PFAPR bitfields
163 * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
165 * This field controls whether read and write access to the flash are allowed
166 * based on the logical master number of the requesting crossbar switch master.
169 * - 00 - No access may be performed by this master
170 * - 01 - Only read accesses may be performed by this master
171 * - 10 - Only write accesses may be performed by this master
172 * - 11 - Both read and write accesses may be performed by this master
175 #define BP_FMC_PFAPR_M0AP (0U) /*!< Bit position for FMC_PFAPR_M0AP. */
176 #define BM_FMC_PFAPR_M0AP (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */
177 #define BS_FMC_PFAPR_M0AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M0AP. */
179 /*! @brief Read current value of the FMC_PFAPR_M0AP field. */
180 #define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP)
182 /*! @brief Format value for bitfield FMC_PFAPR_M0AP. */
183 #define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP)
185 /*! @brief Set the M0AP field to a new value. */
186 #define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
190 * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
192 * This field controls whether read and write access to the flash are allowed
193 * based on the logical master number of the requesting crossbar switch master.
196 * - 00 - No access may be performed by this master
197 * - 01 - Only read accesses may be performed by this master
198 * - 10 - Only write accesses may be performed by this master
199 * - 11 - Both read and write accesses may be performed by this master
202 #define BP_FMC_PFAPR_M1AP (2U) /*!< Bit position for FMC_PFAPR_M1AP. */
203 #define BM_FMC_PFAPR_M1AP (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */
204 #define BS_FMC_PFAPR_M1AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M1AP. */
206 /*! @brief Read current value of the FMC_PFAPR_M1AP field. */
207 #define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP)
209 /*! @brief Format value for bitfield FMC_PFAPR_M1AP. */
210 #define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP)
212 /*! @brief Set the M1AP field to a new value. */
213 #define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
217 * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
219 * This field controls whether read and write access to the flash are allowed
220 * based on the logical master number of the requesting crossbar switch master.
223 * - 00 - No access may be performed by this master
224 * - 01 - Only read accesses may be performed by this master
225 * - 10 - Only write accesses may be performed by this master
226 * - 11 - Both read and write accesses may be performed by this master
229 #define BP_FMC_PFAPR_M2AP (4U) /*!< Bit position for FMC_PFAPR_M2AP. */
230 #define BM_FMC_PFAPR_M2AP (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */
231 #define BS_FMC_PFAPR_M2AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M2AP. */
233 /*! @brief Read current value of the FMC_PFAPR_M2AP field. */
234 #define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP)
236 /*! @brief Format value for bitfield FMC_PFAPR_M2AP. */
237 #define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP)
239 /*! @brief Set the M2AP field to a new value. */
240 #define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
244 * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
246 * This field controls whether read and write access to the flash are allowed
247 * based on the logical master number of the requesting crossbar switch master.
250 * - 00 - No access may be performed by this master
251 * - 01 - Only read accesses may be performed by this master
252 * - 10 - Only write accesses may be performed by this master
253 * - 11 - Both read and write accesses may be performed by this master
256 #define BP_FMC_PFAPR_M3AP (6U) /*!< Bit position for FMC_PFAPR_M3AP. */
257 #define BM_FMC_PFAPR_M3AP (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */
258 #define BS_FMC_PFAPR_M3AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M3AP. */
260 /*! @brief Read current value of the FMC_PFAPR_M3AP field. */
261 #define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP)
263 /*! @brief Format value for bitfield FMC_PFAPR_M3AP. */
264 #define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP)
266 /*! @brief Set the M3AP field to a new value. */
267 #define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
271 * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
273 * This field controls whether read and write access to the flash are allowed
274 * based on the logical master number of the requesting crossbar switch master.
277 * - 00 - No access may be performed by this master
278 * - 01 - Only read accesses may be performed by this master
279 * - 10 - Only write accesses may be performed by this master
280 * - 11 - Both read and write accesses may be performed by this master
283 #define BP_FMC_PFAPR_M4AP (8U) /*!< Bit position for FMC_PFAPR_M4AP. */
284 #define BM_FMC_PFAPR_M4AP (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */
285 #define BS_FMC_PFAPR_M4AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M4AP. */
287 /*! @brief Read current value of the FMC_PFAPR_M4AP field. */
288 #define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP)
290 /*! @brief Format value for bitfield FMC_PFAPR_M4AP. */
291 #define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP)
293 /*! @brief Set the M4AP field to a new value. */
294 #define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
298 * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
300 * This field controls whether read and write access to the flash are allowed
301 * based on the logical master number of the requesting crossbar switch master.
304 * - 00 - No access may be performed by this master
305 * - 01 - Only read accesses may be performed by this master
306 * - 10 - Only write accesses may be performed by this master
307 * - 11 - Both read and write accesses may be performed by this master
310 #define BP_FMC_PFAPR_M5AP (10U) /*!< Bit position for FMC_PFAPR_M5AP. */
311 #define BM_FMC_PFAPR_M5AP (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */
312 #define BS_FMC_PFAPR_M5AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M5AP. */
314 /*! @brief Read current value of the FMC_PFAPR_M5AP field. */
315 #define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP)
317 /*! @brief Format value for bitfield FMC_PFAPR_M5AP. */
318 #define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP)
320 /*! @brief Set the M5AP field to a new value. */
321 #define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
325 * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
327 * This field controls whether read and write access to the flash are allowed
328 * based on the logical master number of the requesting crossbar switch master.
331 * - 00 - No access may be performed by this master
332 * - 01 - Only read accesses may be performed by this master
333 * - 10 - Only write accesses may be performed by this master
334 * - 11 - Both read and write accesses may be performed by this master
337 #define BP_FMC_PFAPR_M6AP (12U) /*!< Bit position for FMC_PFAPR_M6AP. */
338 #define BM_FMC_PFAPR_M6AP (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */
339 #define BS_FMC_PFAPR_M6AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M6AP. */
341 /*! @brief Read current value of the FMC_PFAPR_M6AP field. */
342 #define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP)
344 /*! @brief Format value for bitfield FMC_PFAPR_M6AP. */
345 #define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP)
347 /*! @brief Set the M6AP field to a new value. */
348 #define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
352 * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
354 * This field controls whether read and write access to the flash are allowed
355 * based on the logical master number of the requesting crossbar switch master.
358 * - 00 - No access may be performed by this master.
359 * - 01 - Only read accesses may be performed by this master.
360 * - 10 - Only write accesses may be performed by this master.
361 * - 11 - Both read and write accesses may be performed by this master.
364 #define BP_FMC_PFAPR_M7AP (14U) /*!< Bit position for FMC_PFAPR_M7AP. */
365 #define BM_FMC_PFAPR_M7AP (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */
366 #define BS_FMC_PFAPR_M7AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M7AP. */
368 /*! @brief Read current value of the FMC_PFAPR_M7AP field. */
369 #define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP)
371 /*! @brief Format value for bitfield FMC_PFAPR_M7AP. */
372 #define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP)
374 /*! @brief Set the M7AP field to a new value. */
375 #define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
379 * @name Register FMC_PFAPR, field M0PFD[16] (RW)
381 * These bits control whether prefetching is enabled based on the logical number
382 * of the requesting crossbar switch master. This field is further qualified by
383 * the PFBnCR[BxDPE,BxIPE] bits.
386 * - 0 - Prefetching for this master is enabled.
387 * - 1 - Prefetching for this master is disabled.
390 #define BP_FMC_PFAPR_M0PFD (16U) /*!< Bit position for FMC_PFAPR_M0PFD. */
391 #define BM_FMC_PFAPR_M0PFD (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */
392 #define BS_FMC_PFAPR_M0PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */
394 /*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
395 #define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD))
397 /*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */
398 #define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD)
400 /*! @brief Set the M0PFD field to a new value. */
401 #define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v))
405 * @name Register FMC_PFAPR, field M1PFD[17] (RW)
407 * These bits control whether prefetching is enabled based on the logical number
408 * of the requesting crossbar switch master. This field is further qualified by
409 * the PFBnCR[BxDPE,BxIPE] bits.
412 * - 0 - Prefetching for this master is enabled.
413 * - 1 - Prefetching for this master is disabled.
416 #define BP_FMC_PFAPR_M1PFD (17U) /*!< Bit position for FMC_PFAPR_M1PFD. */
417 #define BM_FMC_PFAPR_M1PFD (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */
418 #define BS_FMC_PFAPR_M1PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */
420 /*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
421 #define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD))
423 /*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */
424 #define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD)
426 /*! @brief Set the M1PFD field to a new value. */
427 #define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v))
431 * @name Register FMC_PFAPR, field M2PFD[18] (RW)
433 * These bits control whether prefetching is enabled based on the logical number
434 * of the requesting crossbar switch master. This field is further qualified by
435 * the PFBnCR[BxDPE,BxIPE] bits.
438 * - 0 - Prefetching for this master is enabled.
439 * - 1 - Prefetching for this master is disabled.
442 #define BP_FMC_PFAPR_M2PFD (18U) /*!< Bit position for FMC_PFAPR_M2PFD. */
443 #define BM_FMC_PFAPR_M2PFD (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */
444 #define BS_FMC_PFAPR_M2PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */
446 /*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
447 #define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD))
449 /*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */
450 #define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD)
452 /*! @brief Set the M2PFD field to a new value. */
453 #define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v))
457 * @name Register FMC_PFAPR, field M3PFD[19] (RW)
459 * These bits control whether prefetching is enabled based on the logical number
460 * of the requesting crossbar switch master. This field is further qualified by
461 * the PFBnCR[BxDPE,BxIPE] bits.
464 * - 0 - Prefetching for this master is enabled.
465 * - 1 - Prefetching for this master is disabled.
468 #define BP_FMC_PFAPR_M3PFD (19U) /*!< Bit position for FMC_PFAPR_M3PFD. */
469 #define BM_FMC_PFAPR_M3PFD (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */
470 #define BS_FMC_PFAPR_M3PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */
472 /*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
473 #define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD))
475 /*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */
476 #define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD)
478 /*! @brief Set the M3PFD field to a new value. */
479 #define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v))
483 * @name Register FMC_PFAPR, field M4PFD[20] (RW)
485 * These bits control whether prefetching is enabled based on the logical number
486 * of the requesting crossbar switch master. This field is further qualified by
487 * the PFBnCR[BxDPE,BxIPE] bits.
490 * - 0 - Prefetching for this master is enabled.
491 * - 1 - Prefetching for this master is disabled.
494 #define BP_FMC_PFAPR_M4PFD (20U) /*!< Bit position for FMC_PFAPR_M4PFD. */
495 #define BM_FMC_PFAPR_M4PFD (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */
496 #define BS_FMC_PFAPR_M4PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */
498 /*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
499 #define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD))
501 /*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */
502 #define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD)
504 /*! @brief Set the M4PFD field to a new value. */
505 #define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v))
509 * @name Register FMC_PFAPR, field M5PFD[21] (RW)
511 * These bits control whether prefetching is enabled based on the logical number
512 * of the requesting crossbar switch master. This field is further qualified by
513 * the PFBnCR[BxDPE,BxIPE] bits.
516 * - 0 - Prefetching for this master is enabled.
517 * - 1 - Prefetching for this master is disabled.
520 #define BP_FMC_PFAPR_M5PFD (21U) /*!< Bit position for FMC_PFAPR_M5PFD. */
521 #define BM_FMC_PFAPR_M5PFD (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */
522 #define BS_FMC_PFAPR_M5PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */
524 /*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
525 #define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD))
527 /*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */
528 #define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD)
530 /*! @brief Set the M5PFD field to a new value. */
531 #define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v))
535 * @name Register FMC_PFAPR, field M6PFD[22] (RW)
537 * These bits control whether prefetching is enabled based on the logical number
538 * of the requesting crossbar switch master. This field is further qualified by
539 * the PFBnCR[BxDPE,BxIPE] bits.
542 * - 0 - Prefetching for this master is enabled.
543 * - 1 - Prefetching for this master is disabled.
546 #define BP_FMC_PFAPR_M6PFD (22U) /*!< Bit position for FMC_PFAPR_M6PFD. */
547 #define BM_FMC_PFAPR_M6PFD (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */
548 #define BS_FMC_PFAPR_M6PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */
550 /*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
551 #define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD))
553 /*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */
554 #define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD)
556 /*! @brief Set the M6PFD field to a new value. */
557 #define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v))
561 * @name Register FMC_PFAPR, field M7PFD[23] (RW)
563 * These bits control whether prefetching is enabled based on the logical number
564 * of the requesting crossbar switch master. This field is further qualified by
565 * the PFBnCR[BxDPE,BxIPE] bits.
568 * - 0 - Prefetching for this master is enabled.
569 * - 1 - Prefetching for this master is disabled.
572 #define BP_FMC_PFAPR_M7PFD (23U) /*!< Bit position for FMC_PFAPR_M7PFD. */
573 #define BM_FMC_PFAPR_M7PFD (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */
574 #define BS_FMC_PFAPR_M7PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */
576 /*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
577 #define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD))
579 /*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */
580 #define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD)
582 /*! @brief Set the M7PFD field to a new value. */
583 #define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v))
586 /*******************************************************************************
587 * HW_FMC_PFB0CR - Flash Bank 0 Control Register
588 ******************************************************************************/
591 * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
593 * Reset value: 0x3002001FU
595 typedef union _hw_fmc_pfb0cr
598 struct _hw_fmc_pfb0cr_bitfields
600 uint32_t B0SEBE
: 1; /*!< [0] Bank 0 Single Entry Buffer Enable */
601 uint32_t B0IPE
: 1; /*!< [1] Bank 0 Instruction Prefetch Enable */
602 uint32_t B0DPE
: 1; /*!< [2] Bank 0 Data Prefetch Enable */
603 uint32_t B0ICE
: 1; /*!< [3] Bank 0 Instruction Cache Enable */
604 uint32_t B0DCE
: 1; /*!< [4] Bank 0 Data Cache Enable */
605 uint32_t CRC
: 3; /*!< [7:5] Cache Replacement Control */
606 uint32_t RESERVED0
: 9; /*!< [16:8] */
607 uint32_t B0MW
: 2; /*!< [18:17] Bank 0 Memory Width */
608 uint32_t S_B_INV
: 1; /*!< [19] Invalidate Prefetch Speculation
610 uint32_t CINV_WAY
: 4; /*!< [23:20] Cache Invalidate Way x */
611 uint32_t CLCK_WAY
: 4; /*!< [27:24] Cache Lock Way x */
612 uint32_t B0RWSC
: 4; /*!< [31:28] Bank 0 Read Wait State Control */
617 * @name Constants and macros for entire FMC_PFB0CR register
620 #define HW_FMC_PFB0CR_ADDR(x) ((x) + 0x4U)
622 #define HW_FMC_PFB0CR(x) (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x))
623 #define HW_FMC_PFB0CR_RD(x) (HW_FMC_PFB0CR(x).U)
624 #define HW_FMC_PFB0CR_WR(x, v) (HW_FMC_PFB0CR(x).U = (v))
625 #define HW_FMC_PFB0CR_SET(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) | (v)))
626 #define HW_FMC_PFB0CR_CLR(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v)))
627 #define HW_FMC_PFB0CR_TOG(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^ (v)))
631 * Constants & macros for individual FMC_PFB0CR bitfields
635 * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
637 * This bit controls whether the single entry page buffer is enabled in response
638 * to flash read accesses. Its operation is independent from bank 1's cache. A
639 * high-to-low transition of this enable forces the page buffer to be invalidated.
642 * - 0 - Single entry buffer is disabled.
643 * - 1 - Single entry buffer is enabled.
646 #define BP_FMC_PFB0CR_B0SEBE (0U) /*!< Bit position for FMC_PFB0CR_B0SEBE. */
647 #define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */
648 #define BS_FMC_PFB0CR_B0SEBE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */
650 /*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
651 #define BR_FMC_PFB0CR_B0SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE))
653 /*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */
654 #define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE)
656 /*! @brief Set the B0SEBE field to a new value. */
657 #define BW_FMC_PFB0CR_B0SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE) = (v))
661 * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
663 * This bit controls whether prefetches (or speculative accesses) are initiated
664 * in response to instruction fetches.
667 * - 0 - Do not prefetch in response to instruction fetches.
668 * - 1 - Enable prefetches in response to instruction fetches.
671 #define BP_FMC_PFB0CR_B0IPE (1U) /*!< Bit position for FMC_PFB0CR_B0IPE. */
672 #define BM_FMC_PFB0CR_B0IPE (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */
673 #define BS_FMC_PFB0CR_B0IPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */
675 /*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
676 #define BR_FMC_PFB0CR_B0IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE))
678 /*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */
679 #define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE)
681 /*! @brief Set the B0IPE field to a new value. */
682 #define BW_FMC_PFB0CR_B0IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE) = (v))
686 * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
688 * This bit controls whether prefetches (or speculative accesses) are initiated
689 * in response to data references.
692 * - 0 - Do not prefetch in response to data references.
693 * - 1 - Enable prefetches in response to data references.
696 #define BP_FMC_PFB0CR_B0DPE (2U) /*!< Bit position for FMC_PFB0CR_B0DPE. */
697 #define BM_FMC_PFB0CR_B0DPE (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */
698 #define BS_FMC_PFB0CR_B0DPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */
700 /*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
701 #define BR_FMC_PFB0CR_B0DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE))
703 /*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */
704 #define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE)
706 /*! @brief Set the B0DPE field to a new value. */
707 #define BW_FMC_PFB0CR_B0DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE) = (v))
711 * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
713 * This bit controls whether instruction fetches are loaded into the cache.
716 * - 0 - Do not cache instruction fetches.
717 * - 1 - Cache instruction fetches.
720 #define BP_FMC_PFB0CR_B0ICE (3U) /*!< Bit position for FMC_PFB0CR_B0ICE. */
721 #define BM_FMC_PFB0CR_B0ICE (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */
722 #define BS_FMC_PFB0CR_B0ICE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */
724 /*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
725 #define BR_FMC_PFB0CR_B0ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE))
727 /*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */
728 #define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE)
730 /*! @brief Set the B0ICE field to a new value. */
731 #define BW_FMC_PFB0CR_B0ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE) = (v))
735 * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
737 * This bit controls whether data references are loaded into the cache.
740 * - 0 - Do not cache data references.
741 * - 1 - Cache data references.
744 #define BP_FMC_PFB0CR_B0DCE (4U) /*!< Bit position for FMC_PFB0CR_B0DCE. */
745 #define BM_FMC_PFB0CR_B0DCE (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */
746 #define BS_FMC_PFB0CR_B0DCE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */
748 /*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
749 #define BR_FMC_PFB0CR_B0DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE))
751 /*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */
752 #define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE)
754 /*! @brief Set the B0DCE field to a new value. */
755 #define BW_FMC_PFB0CR_B0DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE) = (v))
759 * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
761 * This 3-bit field defines the replacement algorithm for accesses that are
765 * - 000 - LRU replacement algorithm per set across all four ways
767 * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
768 * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
772 #define BP_FMC_PFB0CR_CRC (5U) /*!< Bit position for FMC_PFB0CR_CRC. */
773 #define BM_FMC_PFB0CR_CRC (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */
774 #define BS_FMC_PFB0CR_CRC (3U) /*!< Bit field size in bits for FMC_PFB0CR_CRC. */
776 /*! @brief Read current value of the FMC_PFB0CR_CRC field. */
777 #define BR_FMC_PFB0CR_CRC(x) (HW_FMC_PFB0CR(x).B.CRC)
779 /*! @brief Format value for bitfield FMC_PFB0CR_CRC. */
780 #define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC)
782 /*! @brief Set the CRC field to a new value. */
783 #define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
787 * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
789 * This read-only field defines the width of the bank 0 memory.
798 #define BP_FMC_PFB0CR_B0MW (17U) /*!< Bit position for FMC_PFB0CR_B0MW. */
799 #define BM_FMC_PFB0CR_B0MW (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */
800 #define BS_FMC_PFB0CR_B0MW (2U) /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */
802 /*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
803 #define BR_FMC_PFB0CR_B0MW(x) (HW_FMC_PFB0CR(x).B.B0MW)
807 * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
809 * This bit determines if the FMC's prefetch speculation buffer and the single
810 * entry page buffer are to be invalidated (cleared). When this bit is written,
811 * the speculation buffer and single entry buffer are immediately cleared. This bit
812 * always reads as zero.
815 * - 0 - Speculation buffer and single entry buffer are not affected.
816 * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
819 #define BP_FMC_PFB0CR_S_B_INV (19U) /*!< Bit position for FMC_PFB0CR_S_B_INV. */
820 #define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */
821 #define BS_FMC_PFB0CR_S_B_INV (1U) /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */
823 /*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */
824 #define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV)
826 /*! @brief Set the S_B_INV field to a new value. */
827 #define BW_FMC_PFB0CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV) = (v))
831 * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
833 * These bits determine if the given cache way is to be invalidated (cleared).
834 * When a bit within this field is written, the corresponding cache way is
835 * immediately invalidated: the way's tag, data, and valid contents are cleared. This
836 * field always reads as zero. Cache invalidation takes precedence over locking.
837 * The cache is invalidated by system reset. System software is required to
838 * maintain memory coherency when any segment of the flash memory is programmed or
839 * erased. Accordingly, cache invalidations must occur after a programming or erase
840 * event is completed and before the new memory image is accessed. The bit setting
841 * definitions are for each bit in the field.
844 * - 0 - No cache way invalidation for the corresponding cache
845 * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
846 * and vld bits of ways selected
849 #define BP_FMC_PFB0CR_CINV_WAY (20U) /*!< Bit position for FMC_PFB0CR_CINV_WAY. */
850 #define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */
851 #define BS_FMC_PFB0CR_CINV_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */
853 /*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */
854 #define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY)
856 /*! @brief Set the CINV_WAY field to a new value. */
857 #define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
861 * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
863 * These bits determine if the given cache way is locked such that its contents
864 * will not be displaced by future misses. The bit setting definitions are for
865 * each bit in the field.
868 * - 0 - Cache way is unlocked and may be displaced
869 * - 1 - Cache way is locked and its contents are not displaced
872 #define BP_FMC_PFB0CR_CLCK_WAY (24U) /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */
873 #define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */
874 #define BS_FMC_PFB0CR_CLCK_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */
876 /*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
877 #define BR_FMC_PFB0CR_CLCK_WAY(x) (HW_FMC_PFB0CR(x).B.CLCK_WAY)
879 /*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */
880 #define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY)
882 /*! @brief Set the CLCK_WAY field to a new value. */
883 #define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
887 * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
889 * This read-only field defines the number of wait states required to access the
890 * bank 0 flash memory. The relationship between the read access time of the
891 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
892 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
893 * this value based on the ratio of the system clock speed to the flash clock
894 * speed. For example, when this ratio is 4:1, the field's value is 3h.
897 #define BP_FMC_PFB0CR_B0RWSC (28U) /*!< Bit position for FMC_PFB0CR_B0RWSC. */
898 #define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */
899 #define BS_FMC_PFB0CR_B0RWSC (4U) /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */
901 /*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
902 #define BR_FMC_PFB0CR_B0RWSC(x) (HW_FMC_PFB0CR(x).B.B0RWSC)
905 /*******************************************************************************
906 * HW_FMC_PFB1CR - Flash Bank 1 Control Register
907 ******************************************************************************/
910 * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
912 * Reset value: 0x3002001FU
914 * This register has a format similar to that for PFB0CR, except it controls the
915 * operation of flash bank 1, and the "global" cache control fields are empty.
917 typedef union _hw_fmc_pfb1cr
920 struct _hw_fmc_pfb1cr_bitfields
922 uint32_t B1SEBE
: 1; /*!< [0] Bank 1 Single Entry Buffer Enable */
923 uint32_t B1IPE
: 1; /*!< [1] Bank 1 Instruction Prefetch Enable */
924 uint32_t B1DPE
: 1; /*!< [2] Bank 1 Data Prefetch Enable */
925 uint32_t B1ICE
: 1; /*!< [3] Bank 1 Instruction Cache Enable */
926 uint32_t B1DCE
: 1; /*!< [4] Bank 1 Data Cache Enable */
927 uint32_t RESERVED0
: 12; /*!< [16:5] */
928 uint32_t B1MW
: 2; /*!< [18:17] Bank 1 Memory Width */
929 uint32_t RESERVED1
: 9; /*!< [27:19] */
930 uint32_t B1RWSC
: 4; /*!< [31:28] Bank 1 Read Wait State Control */
935 * @name Constants and macros for entire FMC_PFB1CR register
938 #define HW_FMC_PFB1CR_ADDR(x) ((x) + 0x8U)
940 #define HW_FMC_PFB1CR(x) (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x))
941 #define HW_FMC_PFB1CR_RD(x) (HW_FMC_PFB1CR(x).U)
942 #define HW_FMC_PFB1CR_WR(x, v) (HW_FMC_PFB1CR(x).U = (v))
943 #define HW_FMC_PFB1CR_SET(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) | (v)))
944 #define HW_FMC_PFB1CR_CLR(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v)))
945 #define HW_FMC_PFB1CR_TOG(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^ (v)))
949 * Constants & macros for individual FMC_PFB1CR bitfields
953 * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
955 * This bit controls whether the single entry buffer is enabled in response to
956 * flash read accesses. Its operation is independent from bank 0's cache. A
957 * high-to-low transition of this enable forces the page buffer to be invalidated.
960 * - 0 - Single entry buffer is disabled.
961 * - 1 - Single entry buffer is enabled.
964 #define BP_FMC_PFB1CR_B1SEBE (0U) /*!< Bit position for FMC_PFB1CR_B1SEBE. */
965 #define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */
966 #define BS_FMC_PFB1CR_B1SEBE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */
968 /*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
969 #define BR_FMC_PFB1CR_B1SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE))
971 /*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */
972 #define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE)
974 /*! @brief Set the B1SEBE field to a new value. */
975 #define BW_FMC_PFB1CR_B1SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE) = (v))
979 * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
981 * This bit controls whether prefetches (or speculative accesses) are initiated
982 * in response to instruction fetches.
985 * - 0 - Do not prefetch in response to instruction fetches.
986 * - 1 - Enable prefetches in response to instruction fetches.
989 #define BP_FMC_PFB1CR_B1IPE (1U) /*!< Bit position for FMC_PFB1CR_B1IPE. */
990 #define BM_FMC_PFB1CR_B1IPE (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */
991 #define BS_FMC_PFB1CR_B1IPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */
993 /*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
994 #define BR_FMC_PFB1CR_B1IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE))
996 /*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */
997 #define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE)
999 /*! @brief Set the B1IPE field to a new value. */
1000 #define BW_FMC_PFB1CR_B1IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE) = (v))
1004 * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
1006 * This bit controls whether prefetches (or speculative accesses) are initiated
1007 * in response to data references.
1010 * - 0 - Do not prefetch in response to data references.
1011 * - 1 - Enable prefetches in response to data references.
1014 #define BP_FMC_PFB1CR_B1DPE (2U) /*!< Bit position for FMC_PFB1CR_B1DPE. */
1015 #define BM_FMC_PFB1CR_B1DPE (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */
1016 #define BS_FMC_PFB1CR_B1DPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */
1018 /*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
1019 #define BR_FMC_PFB1CR_B1DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE))
1021 /*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */
1022 #define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE)
1024 /*! @brief Set the B1DPE field to a new value. */
1025 #define BW_FMC_PFB1CR_B1DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE) = (v))
1029 * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
1031 * This bit controls whether instruction fetches are loaded into the cache.
1034 * - 0 - Do not cache instruction fetches.
1035 * - 1 - Cache instruction fetches.
1038 #define BP_FMC_PFB1CR_B1ICE (3U) /*!< Bit position for FMC_PFB1CR_B1ICE. */
1039 #define BM_FMC_PFB1CR_B1ICE (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */
1040 #define BS_FMC_PFB1CR_B1ICE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */
1042 /*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
1043 #define BR_FMC_PFB1CR_B1ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE))
1045 /*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */
1046 #define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE)
1048 /*! @brief Set the B1ICE field to a new value. */
1049 #define BW_FMC_PFB1CR_B1ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE) = (v))
1053 * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
1055 * This bit controls whether data references are loaded into the cache.
1058 * - 0 - Do not cache data references.
1059 * - 1 - Cache data references.
1062 #define BP_FMC_PFB1CR_B1DCE (4U) /*!< Bit position for FMC_PFB1CR_B1DCE. */
1063 #define BM_FMC_PFB1CR_B1DCE (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */
1064 #define BS_FMC_PFB1CR_B1DCE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */
1066 /*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
1067 #define BR_FMC_PFB1CR_B1DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE))
1069 /*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */
1070 #define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE)
1072 /*! @brief Set the B1DCE field to a new value. */
1073 #define BW_FMC_PFB1CR_B1DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE) = (v))
1077 * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
1079 * This read-only field defines the width of the bank 1 memory.
1088 #define BP_FMC_PFB1CR_B1MW (17U) /*!< Bit position for FMC_PFB1CR_B1MW. */
1089 #define BM_FMC_PFB1CR_B1MW (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */
1090 #define BS_FMC_PFB1CR_B1MW (2U) /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */
1092 /*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
1093 #define BR_FMC_PFB1CR_B1MW(x) (HW_FMC_PFB1CR(x).B.B1MW)
1097 * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
1099 * This read-only field defines the number of wait states required to access the
1100 * bank 1 flash memory. The relationship between the read access time of the
1101 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
1102 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
1103 * this value based on the ratio of the system clock speed to the flash clock
1104 * speed. For example, when this ratio is 4:1, the field's value is 3h.
1107 #define BP_FMC_PFB1CR_B1RWSC (28U) /*!< Bit position for FMC_PFB1CR_B1RWSC. */
1108 #define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */
1109 #define BS_FMC_PFB1CR_B1RWSC (4U) /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */
1111 /*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
1112 #define BR_FMC_PFB1CR_B1RWSC(x) (HW_FMC_PFB1CR(x).B.B1RWSC)
1115 /*******************************************************************************
1116 * HW_FMC_TAGVDW0Sn - Cache Tag Storage
1117 ******************************************************************************/
1120 * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
1122 * Reset value: 0x00000000U
1124 * The cache is a 4-way, set-associative cache with 8 sets. The ways are
1125 * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y
1126 * denotes the set. This section represents tag/vld information for all sets in the
1129 typedef union _hw_fmc_tagvdw0sn
1132 struct _hw_fmc_tagvdw0sn_bitfields
1134 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1135 uint32_t RESERVED0
: 4; /*!< [4:1] */
1136 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1137 uint32_t RESERVED1
: 13; /*!< [31:19] */
1139 } hw_fmc_tagvdw0sn_t
;
1142 * @name Constants and macros for entire FMC_TAGVDW0Sn register
1145 #define HW_FMC_TAGVDW0Sn_COUNT (8U)
1147 #define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n)))
1149 #define HW_FMC_TAGVDW0Sn(x, n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n))
1150 #define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U)
1151 #define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v))
1152 #define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) | (v)))
1153 #define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v)))
1154 #define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^ (v)))
1158 * Constants & macros for individual FMC_TAGVDW0Sn bitfields
1162 * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
1165 #define BP_FMC_TAGVDW0Sn_valid (0U) /*!< Bit position for FMC_TAGVDW0Sn_valid. */
1166 #define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */
1167 #define BS_FMC_TAGVDW0Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */
1169 /*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */
1170 #define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid))
1172 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */
1173 #define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid)
1175 /*! @brief Set the valid field to a new value. */
1176 #define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v))
1180 * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
1183 #define BP_FMC_TAGVDW0Sn_tag (5U) /*!< Bit position for FMC_TAGVDW0Sn_tag. */
1184 #define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */
1185 #define BS_FMC_TAGVDW0Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */
1187 /*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */
1188 #define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag)
1190 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */
1191 #define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag)
1193 /*! @brief Set the tag field to a new value. */
1194 #define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
1197 /*******************************************************************************
1198 * HW_FMC_TAGVDW1Sn - Cache Tag Storage
1199 ******************************************************************************/
1202 * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
1204 * Reset value: 0x00000000U
1206 * The cache is a 4-way, set-associative cache with 8 sets. The ways are
1207 * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y
1208 * denotes the set. This section represents tag/vld information for all sets in the
1211 typedef union _hw_fmc_tagvdw1sn
1214 struct _hw_fmc_tagvdw1sn_bitfields
1216 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1217 uint32_t RESERVED0
: 4; /*!< [4:1] */
1218 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1219 uint32_t RESERVED1
: 13; /*!< [31:19] */
1221 } hw_fmc_tagvdw1sn_t
;
1224 * @name Constants and macros for entire FMC_TAGVDW1Sn register
1227 #define HW_FMC_TAGVDW1Sn_COUNT (8U)
1229 #define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n)))
1231 #define HW_FMC_TAGVDW1Sn(x, n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n))
1232 #define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U)
1233 #define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v))
1234 #define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) | (v)))
1235 #define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v)))
1236 #define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^ (v)))
1240 * Constants & macros for individual FMC_TAGVDW1Sn bitfields
1244 * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
1247 #define BP_FMC_TAGVDW1Sn_valid (0U) /*!< Bit position for FMC_TAGVDW1Sn_valid. */
1248 #define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */
1249 #define BS_FMC_TAGVDW1Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */
1251 /*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */
1252 #define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid))
1254 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */
1255 #define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid)
1257 /*! @brief Set the valid field to a new value. */
1258 #define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v))
1262 * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
1265 #define BP_FMC_TAGVDW1Sn_tag (5U) /*!< Bit position for FMC_TAGVDW1Sn_tag. */
1266 #define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */
1267 #define BS_FMC_TAGVDW1Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */
1269 /*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */
1270 #define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag)
1272 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */
1273 #define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag)
1275 /*! @brief Set the tag field to a new value. */
1276 #define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
1279 /*******************************************************************************
1280 * HW_FMC_TAGVDW2Sn - Cache Tag Storage
1281 ******************************************************************************/
1284 * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
1286 * Reset value: 0x00000000U
1288 * The cache is a 4-way, set-associative cache with 8 sets. The ways are
1289 * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y
1290 * denotes the set. This section represents tag/vld information for all sets in the
1293 typedef union _hw_fmc_tagvdw2sn
1296 struct _hw_fmc_tagvdw2sn_bitfields
1298 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1299 uint32_t RESERVED0
: 4; /*!< [4:1] */
1300 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1301 uint32_t RESERVED1
: 13; /*!< [31:19] */
1303 } hw_fmc_tagvdw2sn_t
;
1306 * @name Constants and macros for entire FMC_TAGVDW2Sn register
1309 #define HW_FMC_TAGVDW2Sn_COUNT (8U)
1311 #define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x140U + (0x4U * (n)))
1313 #define HW_FMC_TAGVDW2Sn(x, n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n))
1314 #define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U)
1315 #define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v))
1316 #define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) | (v)))
1317 #define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v)))
1318 #define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^ (v)))
1322 * Constants & macros for individual FMC_TAGVDW2Sn bitfields
1326 * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
1329 #define BP_FMC_TAGVDW2Sn_valid (0U) /*!< Bit position for FMC_TAGVDW2Sn_valid. */
1330 #define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */
1331 #define BS_FMC_TAGVDW2Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */
1333 /*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */
1334 #define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid))
1336 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */
1337 #define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid)
1339 /*! @brief Set the valid field to a new value. */
1340 #define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v))
1344 * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
1347 #define BP_FMC_TAGVDW2Sn_tag (5U) /*!< Bit position for FMC_TAGVDW2Sn_tag. */
1348 #define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */
1349 #define BS_FMC_TAGVDW2Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */
1351 /*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */
1352 #define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag)
1354 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */
1355 #define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag)
1357 /*! @brief Set the tag field to a new value. */
1358 #define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
1361 /*******************************************************************************
1362 * HW_FMC_TAGVDW3Sn - Cache Tag Storage
1363 ******************************************************************************/
1366 * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
1368 * Reset value: 0x00000000U
1370 * The cache is a 4-way, set-associative cache with 8 sets. The ways are
1371 * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y
1372 * denotes the set. This section represents tag/vld information for all sets in the
1375 typedef union _hw_fmc_tagvdw3sn
1378 struct _hw_fmc_tagvdw3sn_bitfields
1380 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1381 uint32_t RESERVED0
: 4; /*!< [4:1] */
1382 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1383 uint32_t RESERVED1
: 13; /*!< [31:19] */
1385 } hw_fmc_tagvdw3sn_t
;
1388 * @name Constants and macros for entire FMC_TAGVDW3Sn register
1391 #define HW_FMC_TAGVDW3Sn_COUNT (8U)
1393 #define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x160U + (0x4U * (n)))
1395 #define HW_FMC_TAGVDW3Sn(x, n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n))
1396 #define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U)
1397 #define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v))
1398 #define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) | (v)))
1399 #define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v)))
1400 #define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^ (v)))
1404 * Constants & macros for individual FMC_TAGVDW3Sn bitfields
1408 * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
1411 #define BP_FMC_TAGVDW3Sn_valid (0U) /*!< Bit position for FMC_TAGVDW3Sn_valid. */
1412 #define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */
1413 #define BS_FMC_TAGVDW3Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */
1415 /*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */
1416 #define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid))
1418 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */
1419 #define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid)
1421 /*! @brief Set the valid field to a new value. */
1422 #define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v))
1426 * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
1429 #define BP_FMC_TAGVDW3Sn_tag (5U) /*!< Bit position for FMC_TAGVDW3Sn_tag. */
1430 #define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */
1431 #define BS_FMC_TAGVDW3Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */
1433 /*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */
1434 #define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag)
1436 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */
1437 #define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag)
1439 /*! @brief Set the tag field to a new value. */
1440 #define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
1443 /*******************************************************************************
1444 * HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
1445 ******************************************************************************/
1448 * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
1450 * Reset value: 0x00000000U
1452 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1453 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1454 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1455 * lower word, respectively. This section represents data for the upper word (bits
1456 * [63:32]) of all sets in the indicated way.
1458 typedef union _hw_fmc_dataw0snu
1461 struct _hw_fmc_dataw0snu_bitfields
1463 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1465 } hw_fmc_dataw0snu_t
;
1468 * @name Constants and macros for entire FMC_DATAW0SnU register
1471 #define HW_FMC_DATAW0SnU_COUNT (8U)
1473 #define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n)))
1475 #define HW_FMC_DATAW0SnU(x, n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n))
1476 #define HW_FMC_DATAW0SnU_RD(x, n) (HW_FMC_DATAW0SnU(x, n).U)
1477 #define HW_FMC_DATAW0SnU_WR(x, n, v) (HW_FMC_DATAW0SnU(x, n).U = (v))
1478 #define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) | (v)))
1479 #define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v)))
1480 #define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^ (v)))
1484 * Constants & macros for individual FMC_DATAW0SnU bitfields
1488 * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
1491 #define BP_FMC_DATAW0SnU_data (0U) /*!< Bit position for FMC_DATAW0SnU_data. */
1492 #define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */
1493 #define BS_FMC_DATAW0SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnU_data. */
1495 /*! @brief Read current value of the FMC_DATAW0SnU_data field. */
1496 #define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U)
1498 /*! @brief Format value for bitfield FMC_DATAW0SnU_data. */
1499 #define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data)
1501 /*! @brief Set the data field to a new value. */
1502 #define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v))
1504 /*******************************************************************************
1505 * HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
1506 ******************************************************************************/
1509 * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
1511 * Reset value: 0x00000000U
1513 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1514 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1515 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1516 * lower word, respectively. This section represents data for the lower word (bits
1517 * [31:0]) of all sets in the indicated way.
1519 typedef union _hw_fmc_dataw0snl
1522 struct _hw_fmc_dataw0snl_bitfields
1524 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1526 } hw_fmc_dataw0snl_t
;
1529 * @name Constants and macros for entire FMC_DATAW0SnL register
1532 #define HW_FMC_DATAW0SnL_COUNT (8U)
1534 #define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n)))
1536 #define HW_FMC_DATAW0SnL(x, n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n))
1537 #define HW_FMC_DATAW0SnL_RD(x, n) (HW_FMC_DATAW0SnL(x, n).U)
1538 #define HW_FMC_DATAW0SnL_WR(x, n, v) (HW_FMC_DATAW0SnL(x, n).U = (v))
1539 #define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) | (v)))
1540 #define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v)))
1541 #define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^ (v)))
1545 * Constants & macros for individual FMC_DATAW0SnL bitfields
1549 * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
1552 #define BP_FMC_DATAW0SnL_data (0U) /*!< Bit position for FMC_DATAW0SnL_data. */
1553 #define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */
1554 #define BS_FMC_DATAW0SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnL_data. */
1556 /*! @brief Read current value of the FMC_DATAW0SnL_data field. */
1557 #define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U)
1559 /*! @brief Format value for bitfield FMC_DATAW0SnL_data. */
1560 #define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data)
1562 /*! @brief Set the data field to a new value. */
1563 #define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v))
1566 /*******************************************************************************
1567 * HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
1568 ******************************************************************************/
1571 * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
1573 * Reset value: 0x00000000U
1575 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1576 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1577 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1578 * lower word, respectively. This section represents data for the upper word (bits
1579 * [63:32]) of all sets in the indicated way.
1581 typedef union _hw_fmc_dataw1snu
1584 struct _hw_fmc_dataw1snu_bitfields
1586 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1588 } hw_fmc_dataw1snu_t
;
1591 * @name Constants and macros for entire FMC_DATAW1SnU register
1594 #define HW_FMC_DATAW1SnU_COUNT (8U)
1596 #define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n)))
1598 #define HW_FMC_DATAW1SnU(x, n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n))
1599 #define HW_FMC_DATAW1SnU_RD(x, n) (HW_FMC_DATAW1SnU(x, n).U)
1600 #define HW_FMC_DATAW1SnU_WR(x, n, v) (HW_FMC_DATAW1SnU(x, n).U = (v))
1601 #define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) | (v)))
1602 #define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v)))
1603 #define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^ (v)))
1607 * Constants & macros for individual FMC_DATAW1SnU bitfields
1611 * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
1614 #define BP_FMC_DATAW1SnU_data (0U) /*!< Bit position for FMC_DATAW1SnU_data. */
1615 #define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */
1616 #define BS_FMC_DATAW1SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnU_data. */
1618 /*! @brief Read current value of the FMC_DATAW1SnU_data field. */
1619 #define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U)
1621 /*! @brief Format value for bitfield FMC_DATAW1SnU_data. */
1622 #define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data)
1624 /*! @brief Set the data field to a new value. */
1625 #define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v))
1627 /*******************************************************************************
1628 * HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
1629 ******************************************************************************/
1632 * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
1634 * Reset value: 0x00000000U
1636 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1637 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1638 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1639 * lower word, respectively. This section represents data for the lower word (bits
1640 * [31:0]) of all sets in the indicated way.
1642 typedef union _hw_fmc_dataw1snl
1645 struct _hw_fmc_dataw1snl_bitfields
1647 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1649 } hw_fmc_dataw1snl_t
;
1652 * @name Constants and macros for entire FMC_DATAW1SnL register
1655 #define HW_FMC_DATAW1SnL_COUNT (8U)
1657 #define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n)))
1659 #define HW_FMC_DATAW1SnL(x, n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n))
1660 #define HW_FMC_DATAW1SnL_RD(x, n) (HW_FMC_DATAW1SnL(x, n).U)
1661 #define HW_FMC_DATAW1SnL_WR(x, n, v) (HW_FMC_DATAW1SnL(x, n).U = (v))
1662 #define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) | (v)))
1663 #define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v)))
1664 #define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^ (v)))
1668 * Constants & macros for individual FMC_DATAW1SnL bitfields
1672 * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
1675 #define BP_FMC_DATAW1SnL_data (0U) /*!< Bit position for FMC_DATAW1SnL_data. */
1676 #define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */
1677 #define BS_FMC_DATAW1SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnL_data. */
1679 /*! @brief Read current value of the FMC_DATAW1SnL_data field. */
1680 #define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U)
1682 /*! @brief Format value for bitfield FMC_DATAW1SnL_data. */
1683 #define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data)
1685 /*! @brief Set the data field to a new value. */
1686 #define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v))
1689 /*******************************************************************************
1690 * HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
1691 ******************************************************************************/
1694 * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
1696 * Reset value: 0x00000000U
1698 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1699 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1700 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1701 * lower word, respectively. This section represents data for the upper word (bits
1702 * [63:32]) of all sets in the indicated way.
1704 typedef union _hw_fmc_dataw2snu
1707 struct _hw_fmc_dataw2snu_bitfields
1709 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1711 } hw_fmc_dataw2snu_t
;
1714 * @name Constants and macros for entire FMC_DATAW2SnU register
1717 #define HW_FMC_DATAW2SnU_COUNT (8U)
1719 #define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x280U + (0x8U * (n)))
1721 #define HW_FMC_DATAW2SnU(x, n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n))
1722 #define HW_FMC_DATAW2SnU_RD(x, n) (HW_FMC_DATAW2SnU(x, n).U)
1723 #define HW_FMC_DATAW2SnU_WR(x, n, v) (HW_FMC_DATAW2SnU(x, n).U = (v))
1724 #define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) | (v)))
1725 #define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v)))
1726 #define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^ (v)))
1730 * Constants & macros for individual FMC_DATAW2SnU bitfields
1734 * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
1737 #define BP_FMC_DATAW2SnU_data (0U) /*!< Bit position for FMC_DATAW2SnU_data. */
1738 #define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */
1739 #define BS_FMC_DATAW2SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnU_data. */
1741 /*! @brief Read current value of the FMC_DATAW2SnU_data field. */
1742 #define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U)
1744 /*! @brief Format value for bitfield FMC_DATAW2SnU_data. */
1745 #define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data)
1747 /*! @brief Set the data field to a new value. */
1748 #define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v))
1750 /*******************************************************************************
1751 * HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
1752 ******************************************************************************/
1755 * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
1757 * Reset value: 0x00000000U
1759 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1760 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1761 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1762 * lower word, respectively. This section represents data for the lower word (bits
1763 * [31:0]) of all sets in the indicated way.
1765 typedef union _hw_fmc_dataw2snl
1768 struct _hw_fmc_dataw2snl_bitfields
1770 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1772 } hw_fmc_dataw2snl_t
;
1775 * @name Constants and macros for entire FMC_DATAW2SnL register
1778 #define HW_FMC_DATAW2SnL_COUNT (8U)
1780 #define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x284U + (0x8U * (n)))
1782 #define HW_FMC_DATAW2SnL(x, n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n))
1783 #define HW_FMC_DATAW2SnL_RD(x, n) (HW_FMC_DATAW2SnL(x, n).U)
1784 #define HW_FMC_DATAW2SnL_WR(x, n, v) (HW_FMC_DATAW2SnL(x, n).U = (v))
1785 #define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) | (v)))
1786 #define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v)))
1787 #define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^ (v)))
1791 * Constants & macros for individual FMC_DATAW2SnL bitfields
1795 * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
1798 #define BP_FMC_DATAW2SnL_data (0U) /*!< Bit position for FMC_DATAW2SnL_data. */
1799 #define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */
1800 #define BS_FMC_DATAW2SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnL_data. */
1802 /*! @brief Read current value of the FMC_DATAW2SnL_data field. */
1803 #define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U)
1805 /*! @brief Format value for bitfield FMC_DATAW2SnL_data. */
1806 #define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data)
1808 /*! @brief Set the data field to a new value. */
1809 #define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v))
1812 /*******************************************************************************
1813 * HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
1814 ******************************************************************************/
1817 * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
1819 * Reset value: 0x00000000U
1821 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1822 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1823 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1824 * lower word, respectively. This section represents data for the upper word (bits
1825 * [63:32]) of all sets in the indicated way.
1827 typedef union _hw_fmc_dataw3snu
1830 struct _hw_fmc_dataw3snu_bitfields
1832 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1834 } hw_fmc_dataw3snu_t
;
1837 * @name Constants and macros for entire FMC_DATAW3SnU register
1840 #define HW_FMC_DATAW3SnU_COUNT (8U)
1842 #define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x2C0U + (0x8U * (n)))
1844 #define HW_FMC_DATAW3SnU(x, n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n))
1845 #define HW_FMC_DATAW3SnU_RD(x, n) (HW_FMC_DATAW3SnU(x, n).U)
1846 #define HW_FMC_DATAW3SnU_WR(x, n, v) (HW_FMC_DATAW3SnU(x, n).U = (v))
1847 #define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) | (v)))
1848 #define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v)))
1849 #define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^ (v)))
1853 * Constants & macros for individual FMC_DATAW3SnU bitfields
1857 * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
1860 #define BP_FMC_DATAW3SnU_data (0U) /*!< Bit position for FMC_DATAW3SnU_data. */
1861 #define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */
1862 #define BS_FMC_DATAW3SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnU_data. */
1864 /*! @brief Read current value of the FMC_DATAW3SnU_data field. */
1865 #define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U)
1867 /*! @brief Format value for bitfield FMC_DATAW3SnU_data. */
1868 #define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data)
1870 /*! @brief Set the data field to a new value. */
1871 #define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v))
1873 /*******************************************************************************
1874 * HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
1875 ******************************************************************************/
1878 * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
1880 * Reset value: 0x00000000U
1882 * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets.
1883 * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and
1884 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1885 * lower word, respectively. This section represents data for the lower word (bits
1886 * [31:0]) of all sets in the indicated way.
1888 typedef union _hw_fmc_dataw3snl
1891 struct _hw_fmc_dataw3snl_bitfields
1893 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1895 } hw_fmc_dataw3snl_t
;
1898 * @name Constants and macros for entire FMC_DATAW3SnL register
1901 #define HW_FMC_DATAW3SnL_COUNT (8U)
1903 #define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x2C4U + (0x8U * (n)))
1905 #define HW_FMC_DATAW3SnL(x, n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n))
1906 #define HW_FMC_DATAW3SnL_RD(x, n) (HW_FMC_DATAW3SnL(x, n).U)
1907 #define HW_FMC_DATAW3SnL_WR(x, n, v) (HW_FMC_DATAW3SnL(x, n).U = (v))
1908 #define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) | (v)))
1909 #define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v)))
1910 #define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^ (v)))
1914 * Constants & macros for individual FMC_DATAW3SnL bitfields
1918 * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
1921 #define BP_FMC_DATAW3SnL_data (0U) /*!< Bit position for FMC_DATAW3SnL_data. */
1922 #define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */
1923 #define BS_FMC_DATAW3SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnL_data. */
1925 /*! @brief Read current value of the FMC_DATAW3SnL_data field. */
1926 #define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U)
1928 /*! @brief Format value for bitfield FMC_DATAW3SnL_data. */
1929 #define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data)
1931 /*! @brief Set the data field to a new value. */
1932 #define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v))
1935 /*******************************************************************************
1936 * hw_fmc_t - module struct
1937 ******************************************************************************/
1939 * @brief All FMC module registers.
1942 typedef struct _hw_fmc
1944 __IO hw_fmc_pfapr_t PFAPR
; /*!< [0x0] Flash Access Protection Register */
1945 __IO hw_fmc_pfb0cr_t PFB0CR
; /*!< [0x4] Flash Bank 0 Control Register */
1946 __IO hw_fmc_pfb1cr_t PFB1CR
; /*!< [0x8] Flash Bank 1 Control Register */
1947 uint8_t _reserved0
[244];
1948 __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn
[8]; /*!< [0x100] Cache Tag Storage */
1949 __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn
[8]; /*!< [0x120] Cache Tag Storage */
1950 __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn
[8]; /*!< [0x140] Cache Tag Storage */
1951 __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn
[8]; /*!< [0x160] Cache Tag Storage */
1952 uint8_t _reserved1
[128];
1954 __IO hw_fmc_dataw0snu_t DATAW0SnU
; /*!< [0x200] Cache Data Storage (upper word) */
1955 __IO hw_fmc_dataw0snl_t DATAW0SnL
; /*!< [0x204] Cache Data Storage (lower word) */
1958 __IO hw_fmc_dataw1snu_t DATAW1SnU
; /*!< [0x240] Cache Data Storage (upper word) */
1959 __IO hw_fmc_dataw1snl_t DATAW1SnL
; /*!< [0x244] Cache Data Storage (lower word) */
1962 __IO hw_fmc_dataw2snu_t DATAW2SnU
; /*!< [0x280] Cache Data Storage (upper word) */
1963 __IO hw_fmc_dataw2snl_t DATAW2SnL
; /*!< [0x284] Cache Data Storage (lower word) */
1966 __IO hw_fmc_dataw3snu_t DATAW3SnU
; /*!< [0x2C0] Cache Data Storage (upper word) */
1967 __IO hw_fmc_dataw3snl_t DATAW3SnL
; /*!< [0x2C4] Cache Data Storage (lower word) */
1972 /*! @brief Macro to access all FMC registers. */
1973 /*! @param x FMC module instance base address. */
1974 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1975 * use the '&' operator, like <code>&HW_FMC(FMC_BASE)</code>. */
1976 #define HW_FMC(x) (*(hw_fmc_t *)(x))
1978 #endif /* __HW_FMC_REGISTERS_H__ */