tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_I2C_REGISTERS_H__
  78 #define __HW_I2C_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 I2C
  85  *
  86  * Inter-Integrated Circuit
  87  *
  88  * Registers defined in this header file:
  89  * - HW_I2C_A1 - I2C Address Register 1
  90  * - HW_I2C_F - I2C Frequency Divider register
  91  * - HW_I2C_C1 - I2C Control Register 1
  92  * - HW_I2C_S - I2C Status register
  93  * - HW_I2C_D - I2C Data I/O register
  94  * - HW_I2C_C2 - I2C Control Register 2
  95  * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
  96  * - HW_I2C_RA - I2C Range Address register
  97  * - HW_I2C_SMB - I2C SMBus Control and Status register
  98  * - HW_I2C_A2 - I2C Address Register 2
  99  * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
 100  * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
 101  *
 102  * - hw_i2c_t - Struct containing all module registers.
 103  */
 104
 105 #define HW_I2C_INSTANCE_COUNT (2U) /*!< Number of instances of the I2C module. */
 106 #define HW_I2C0 (0U) /*!< Instance number for I2C0. */
 107 #define HW_I2C1 (1U) /*!< Instance number for I2C1. */
 108
 109 /*******************************************************************************
 110  * HW_I2C_A1 - I2C Address Register 1
 111  ******************************************************************************/
 112
 113 /*!
 114  * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
 115  *
 116  * Reset value: 0x00U
 117  *
 118  * This register contains the slave address to be used by the I2C module.
 119  */
 120 typedef union _hw_i2c_a1
 121 {
 122     uint8_t U;
 123     struct _hw_i2c_a1_bitfields
 124     {
 125         uint8_t RESERVED0 : 1;         /*!< [0]  */
 126         uint8_t AD : 7;                /*!< [7:1] Address */
 127     } B;
 128 } hw_i2c_a1_t;
 129
 130 /*!
 131  * @name Constants and macros for entire I2C_A1 register
 132  */
 133 /*@{*/
 134 #define HW_I2C_A1_ADDR(x)        ((x) + 0x0U)
 135
 136 #define HW_I2C_A1(x)             (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
 137 #define HW_I2C_A1_RD(x)          (HW_I2C_A1(x).U)
 138 #define HW_I2C_A1_WR(x, v)       (HW_I2C_A1(x).U = (v))
 139 #define HW_I2C_A1_SET(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) |  (v)))
 140 #define HW_I2C_A1_CLR(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
 141 #define HW_I2C_A1_TOG(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^  (v)))
 142 /*@}*/
 143
 144 /*
 145  * Constants & macros for individual I2C_A1 bitfields
 146  */
 147
 148 /*!
 149  * @name Register I2C_A1, field AD[7:1] (RW)
 150  *
 151  * Contains the primary slave address used by the I2C module when it is
 152  * addressed as a slave. This field is used in the 7-bit address scheme and the lower
 153  * seven bits in the 10-bit address scheme.
 154  */
 155 /*@{*/
 156 #define BP_I2C_A1_AD         (1U)          /*!< Bit position for I2C_A1_AD. */
 157 #define BM_I2C_A1_AD         (0xFEU)       /*!< Bit mask for I2C_A1_AD. */
 158 #define BS_I2C_A1_AD         (7U)          /*!< Bit field size in bits for I2C_A1_AD. */
 159
 160 /*! @brief Read current value of the I2C_A1_AD field. */
 161 #define BR_I2C_A1_AD(x)      (HW_I2C_A1(x).B.AD)
 162
 163 /*! @brief Format value for bitfield I2C_A1_AD. */
 164 #define BF_I2C_A1_AD(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_A1_AD) & BM_I2C_A1_AD)
 165
 166 /*! @brief Set the AD field to a new value. */
 167 #define BW_I2C_A1_AD(x, v)   (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
 168 /*@}*/
 169
 170 /*******************************************************************************
 171  * HW_I2C_F - I2C Frequency Divider register
 172  ******************************************************************************/
 173
 174 /*!
 175  * @brief HW_I2C_F - I2C Frequency Divider register (RW)
 176  *
 177  * Reset value: 0x00U
 178  */
 179 typedef union _hw_i2c_f
 180 {
 181     uint8_t U;
 182     struct _hw_i2c_f_bitfields
 183     {
 184         uint8_t ICR : 6;               /*!< [5:0] ClockRate */
 185         uint8_t MULT : 2;              /*!< [7:6] Multiplier Factor */
 186     } B;
 187 } hw_i2c_f_t;
 188
 189 /*!
 190  * @name Constants and macros for entire I2C_F register
 191  */
 192 /*@{*/
 193 #define HW_I2C_F_ADDR(x)         ((x) + 0x1U)
 194
 195 #define HW_I2C_F(x)              (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
 196 #define HW_I2C_F_RD(x)           (HW_I2C_F(x).U)
 197 #define HW_I2C_F_WR(x, v)        (HW_I2C_F(x).U = (v))
 198 #define HW_I2C_F_SET(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) |  (v)))
 199 #define HW_I2C_F_CLR(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
 200 #define HW_I2C_F_TOG(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^  (v)))
 201 /*@}*/
 202
 203 /*
 204  * Constants & macros for individual I2C_F bitfields
 205  */
 206
 207 /*!
 208  * @name Register I2C_F, field ICR[5:0] (RW)
 209  *
 210  * Prescales the I2C module clock for bit rate selection. This field and the
 211  * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
 212  * time, and the SCL stop hold time. For a list of values corresponding to each ICR
 213  * setting, see I2C divider and hold values. The SCL divider multiplied by
 214  * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
 215  * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
 216  * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
 217  * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
 218  * the delay from the falling edge of SDA (I2C data) while SCL is high (start
 219  * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
 220  * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
 221  * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
 222  * data) while SCL is high (stop condition). SCL stop hold time = I2C module
 223  * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
 224  * speed is 8 MHz, the following table shows the possible hold time values with
 225  * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
 226  * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
 227  * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
 228  * 1.125 4.750 5.125
 229  */
 230 /*@{*/
 231 #define BP_I2C_F_ICR         (0U)          /*!< Bit position for I2C_F_ICR. */
 232 #define BM_I2C_F_ICR         (0x3FU)       /*!< Bit mask for I2C_F_ICR. */
 233 #define BS_I2C_F_ICR         (6U)          /*!< Bit field size in bits for I2C_F_ICR. */
 234
 235 /*! @brief Read current value of the I2C_F_ICR field. */
 236 #define BR_I2C_F_ICR(x)      (HW_I2C_F(x).B.ICR)
 237
 238 /*! @brief Format value for bitfield I2C_F_ICR. */
 239 #define BF_I2C_F_ICR(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_F_ICR) & BM_I2C_F_ICR)
 240
 241 /*! @brief Set the ICR field to a new value. */
 242 #define BW_I2C_F_ICR(x, v)   (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
 243 /*@}*/
 244
 245 /*!
 246  * @name Register I2C_F, field MULT[7:6] (RW)
 247  *
 248  * Defines the multiplier factor (mul). This factor is used along with the SCL
 249  * divider to generate the I2C baud rate.
 250  *
 251  * Values:
 252  * - 00 - mul = 1
 253  * - 01 - mul = 2
 254  * - 10 - mul = 4
 255  * - 11 - Reserved
 256  */
 257 /*@{*/
 258 #define BP_I2C_F_MULT        (6U)          /*!< Bit position for I2C_F_MULT. */
 259 #define BM_I2C_F_MULT        (0xC0U)       /*!< Bit mask for I2C_F_MULT. */
 260 #define BS_I2C_F_MULT        (2U)          /*!< Bit field size in bits for I2C_F_MULT. */
 261
 262 /*! @brief Read current value of the I2C_F_MULT field. */
 263 #define BR_I2C_F_MULT(x)     (HW_I2C_F(x).B.MULT)
 264
 265 /*! @brief Format value for bitfield I2C_F_MULT. */
 266 #define BF_I2C_F_MULT(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_F_MULT) & BM_I2C_F_MULT)
 267
 268 /*! @brief Set the MULT field to a new value. */
 269 #define BW_I2C_F_MULT(x, v)  (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
 270 /*@}*/
 271
 272 /*******************************************************************************
 273  * HW_I2C_C1 - I2C Control Register 1
 274  ******************************************************************************/
 275
 276 /*!
 277  * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
 278  *
 279  * Reset value: 0x00U
 280  */
 281 typedef union _hw_i2c_c1
 282 {
 283     uint8_t U;
 284     struct _hw_i2c_c1_bitfields
 285     {
 286         uint8_t DMAEN : 1;             /*!< [0] DMA Enable */
 287         uint8_t WUEN : 1;              /*!< [1] Wakeup Enable */
 288         uint8_t RSTA : 1;              /*!< [2] Repeat START */
 289         uint8_t TXAK : 1;              /*!< [3] Transmit Acknowledge Enable */
 290         uint8_t TX : 1;                /*!< [4] Transmit Mode Select */
 291         uint8_t MST : 1;               /*!< [5] Master Mode Select */
 292         uint8_t IICIE : 1;             /*!< [6] I2C Interrupt Enable */
 293         uint8_t IICEN : 1;             /*!< [7] I2C Enable */
 294     } B;
 295 } hw_i2c_c1_t;
 296
 297 /*!
 298  * @name Constants and macros for entire I2C_C1 register
 299  */
 300 /*@{*/
 301 #define HW_I2C_C1_ADDR(x)        ((x) + 0x2U)
 302
 303 #define HW_I2C_C1(x)             (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
 304 #define HW_I2C_C1_RD(x)          (HW_I2C_C1(x).U)
 305 #define HW_I2C_C1_WR(x, v)       (HW_I2C_C1(x).U = (v))
 306 #define HW_I2C_C1_SET(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) |  (v)))
 307 #define HW_I2C_C1_CLR(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
 308 #define HW_I2C_C1_TOG(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^  (v)))
 309 /*@}*/
 310
 311 /*
 312  * Constants & macros for individual I2C_C1 bitfields
 313  */
 314
 315 /*!
 316  * @name Register I2C_C1, field DMAEN[0] (RW)
 317  *
 318  * Enables or disables the DMA function.
 319  *
 320  * Values:
 321  * - 0 - All DMA signalling disabled.
 322  * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
 323  *     trigger the DMA request: a data byte is received, and either address or
 324  *     data is transmitted. (ACK/NACK is automatic) the first byte received matches
 325  *     the A1 register or is a general call address. If any address matching
 326  *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
 327  *     from master to slave, then it is not required to check S[SRW]. With this
 328  *     assumption, DMA can also be used in this case. In other cases, if the master
 329  *     reads data from the slave, then it is required to rewrite the C1 register
 330  *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
 331  *     address or a data byte is transmitted.
 332  */
 333 /*@{*/
 334 #define BP_I2C_C1_DMAEN      (0U)          /*!< Bit position for I2C_C1_DMAEN. */
 335 #define BM_I2C_C1_DMAEN      (0x01U)       /*!< Bit mask for I2C_C1_DMAEN. */
 336 #define BS_I2C_C1_DMAEN      (1U)          /*!< Bit field size in bits for I2C_C1_DMAEN. */
 337
 338 /*! @brief Read current value of the I2C_C1_DMAEN field. */
 339 #define BR_I2C_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
 340
 341 /*! @brief Format value for bitfield I2C_C1_DMAEN. */
 342 #define BF_I2C_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_DMAEN) & BM_I2C_C1_DMAEN)
 343
 344 /*! @brief Set the DMAEN field to a new value. */
 345 #define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
 346 /*@}*/
 347
 348 /*!
 349  * @name Register I2C_C1, field WUEN[1] (RW)
 350  *
 351  * The I2C module can wake the MCU from low power mode with no peripheral bus
 352  * running when slave address matching occurs.
 353  *
 354  * Values:
 355  * - 0 - Normal operation. No interrupt generated when address matching in low
 356  *     power mode.
 357  * - 1 - Enables the wakeup function in low power mode.
 358  */
 359 /*@{*/
 360 #define BP_I2C_C1_WUEN       (1U)          /*!< Bit position for I2C_C1_WUEN. */
 361 #define BM_I2C_C1_WUEN       (0x02U)       /*!< Bit mask for I2C_C1_WUEN. */
 362 #define BS_I2C_C1_WUEN       (1U)          /*!< Bit field size in bits for I2C_C1_WUEN. */
 363
 364 /*! @brief Read current value of the I2C_C1_WUEN field. */
 365 #define BR_I2C_C1_WUEN(x)    (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
 366
 367 /*! @brief Format value for bitfield I2C_C1_WUEN. */
 368 #define BF_I2C_C1_WUEN(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_WUEN) & BM_I2C_C1_WUEN)
 369
 370 /*! @brief Set the WUEN field to a new value. */
 371 #define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
 372 /*@}*/
 373
 374 /*!
 375  * @name Register I2C_C1, field RSTA[2] (WORZ)
 376  *
 377  * Writing 1 to this bit generates a repeated START condition provided it is the
 378  * current master. This bit will always be read as 0. Attempting a repeat at the
 379  * wrong time results in loss of arbitration.
 380  */
 381 /*@{*/
 382 #define BP_I2C_C1_RSTA       (2U)          /*!< Bit position for I2C_C1_RSTA. */
 383 #define BM_I2C_C1_RSTA       (0x04U)       /*!< Bit mask for I2C_C1_RSTA. */
 384 #define BS_I2C_C1_RSTA       (1U)          /*!< Bit field size in bits for I2C_C1_RSTA. */
 385
 386 /*! @brief Format value for bitfield I2C_C1_RSTA. */
 387 #define BF_I2C_C1_RSTA(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_RSTA) & BM_I2C_C1_RSTA)
 388
 389 /*! @brief Set the RSTA field to a new value. */
 390 #define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
 391 /*@}*/
 392
 393 /*!
 394  * @name Register I2C_C1, field TXAK[3] (RW)
 395  *
 396  * Specifies the value driven onto the SDA during data acknowledge cycles for
 397  * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
 398  * generation. SCL is held low until TXAK is written.
 399  *
 400  * Values:
 401  * - 0 - An acknowledge signal is sent to the bus on the following receiving
 402  *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
 403  * - 1 - No acknowledge signal is sent to the bus on the following receiving
 404  *     data byte (if FACK is cleared) or the current receiving data byte (if FACK is
 405  *     set).
 406  */
 407 /*@{*/
 408 #define BP_I2C_C1_TXAK       (3U)          /*!< Bit position for I2C_C1_TXAK. */
 409 #define BM_I2C_C1_TXAK       (0x08U)       /*!< Bit mask for I2C_C1_TXAK. */
 410 #define BS_I2C_C1_TXAK       (1U)          /*!< Bit field size in bits for I2C_C1_TXAK. */
 411
 412 /*! @brief Read current value of the I2C_C1_TXAK field. */
 413 #define BR_I2C_C1_TXAK(x)    (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
 414
 415 /*! @brief Format value for bitfield I2C_C1_TXAK. */
 416 #define BF_I2C_C1_TXAK(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TXAK) & BM_I2C_C1_TXAK)
 417
 418 /*! @brief Set the TXAK field to a new value. */
 419 #define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
 420 /*@}*/
 421
 422 /*!
 423  * @name Register I2C_C1, field TX[4] (RW)
 424  *
 425  * Selects the direction of master and slave transfers. In master mode this bit
 426  * must be set according to the type of transfer required. Therefore, for address
 427  * cycles, this bit is always set. When addressed as a slave this bit must be
 428  * set by software according to the SRW bit in the status register.
 429  *
 430  * Values:
 431  * - 0 - Receive
 432  * - 1 - Transmit
 433  */
 434 /*@{*/
 435 #define BP_I2C_C1_TX         (4U)          /*!< Bit position for I2C_C1_TX. */
 436 #define BM_I2C_C1_TX         (0x10U)       /*!< Bit mask for I2C_C1_TX. */
 437 #define BS_I2C_C1_TX         (1U)          /*!< Bit field size in bits for I2C_C1_TX. */
 438
 439 /*! @brief Read current value of the I2C_C1_TX field. */
 440 #define BR_I2C_C1_TX(x)      (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
 441
 442 /*! @brief Format value for bitfield I2C_C1_TX. */
 443 #define BF_I2C_C1_TX(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TX) & BM_I2C_C1_TX)
 444
 445 /*! @brief Set the TX field to a new value. */
 446 #define BW_I2C_C1_TX(x, v)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
 447 /*@}*/
 448
 449 /*!
 450  * @name Register I2C_C1, field MST[5] (RW)
 451  *
 452  * When MST is changed from 0 to 1, a START signal is generated on the bus and
 453  * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
 454  * generated and the mode of operation changes from master to slave.
 455  *
 456  * Values:
 457  * - 0 - Slave mode
 458  * - 1 - Master mode
 459  */
 460 /*@{*/
 461 #define BP_I2C_C1_MST        (5U)          /*!< Bit position for I2C_C1_MST. */
 462 #define BM_I2C_C1_MST        (0x20U)       /*!< Bit mask for I2C_C1_MST. */
 463 #define BS_I2C_C1_MST        (1U)          /*!< Bit field size in bits for I2C_C1_MST. */
 464
 465 /*! @brief Read current value of the I2C_C1_MST field. */
 466 #define BR_I2C_C1_MST(x)     (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
 467
 468 /*! @brief Format value for bitfield I2C_C1_MST. */
 469 #define BF_I2C_C1_MST(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_C1_MST) & BM_I2C_C1_MST)
 470
 471 /*! @brief Set the MST field to a new value. */
 472 #define BW_I2C_C1_MST(x, v)  (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
 473 /*@}*/
 474
 475 /*!
 476  * @name Register I2C_C1, field IICIE[6] (RW)
 477  *
 478  * Enables I2C interrupt requests.
 479  *
 480  * Values:
 481  * - 0 - Disabled
 482  * - 1 - Enabled
 483  */
 484 /*@{*/
 485 #define BP_I2C_C1_IICIE      (6U)          /*!< Bit position for I2C_C1_IICIE. */
 486 #define BM_I2C_C1_IICIE      (0x40U)       /*!< Bit mask for I2C_C1_IICIE. */
 487 #define BS_I2C_C1_IICIE      (1U)          /*!< Bit field size in bits for I2C_C1_IICIE. */
 488
 489 /*! @brief Read current value of the I2C_C1_IICIE field. */
 490 #define BR_I2C_C1_IICIE(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
 491
 492 /*! @brief Format value for bitfield I2C_C1_IICIE. */
 493 #define BF_I2C_C1_IICIE(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICIE) & BM_I2C_C1_IICIE)
 494
 495 /*! @brief Set the IICIE field to a new value. */
 496 #define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
 497 /*@}*/
 498
 499 /*!
 500  * @name Register I2C_C1, field IICEN[7] (RW)
 501  *
 502  * Enables I2C module operation.
 503  *
 504  * Values:
 505  * - 0 - Disabled
 506  * - 1 - Enabled
 507  */
 508 /*@{*/
 509 #define BP_I2C_C1_IICEN      (7U)          /*!< Bit position for I2C_C1_IICEN. */
 510 #define BM_I2C_C1_IICEN      (0x80U)       /*!< Bit mask for I2C_C1_IICEN. */
 511 #define BS_I2C_C1_IICEN      (1U)          /*!< Bit field size in bits for I2C_C1_IICEN. */
 512
 513 /*! @brief Read current value of the I2C_C1_IICEN field. */
 514 #define BR_I2C_C1_IICEN(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
 515
 516 /*! @brief Format value for bitfield I2C_C1_IICEN. */
 517 #define BF_I2C_C1_IICEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICEN) & BM_I2C_C1_IICEN)
 518
 519 /*! @brief Set the IICEN field to a new value. */
 520 #define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
 521 /*@}*/
 522
 523 /*******************************************************************************
 524  * HW_I2C_S - I2C Status register
 525  ******************************************************************************/
 526
 527 /*!
 528  * @brief HW_I2C_S - I2C Status register (RW)
 529  *
 530  * Reset value: 0x80U
 531  */
 532 typedef union _hw_i2c_s
 533 {
 534     uint8_t U;
 535     struct _hw_i2c_s_bitfields
 536     {
 537         uint8_t RXAK : 1;              /*!< [0] Receive Acknowledge */
 538         uint8_t IICIF : 1;             /*!< [1] Interrupt Flag */
 539         uint8_t SRW : 1;               /*!< [2] Slave Read/Write */
 540         uint8_t RAM : 1;               /*!< [3] Range Address Match */
 541         uint8_t ARBL : 1;              /*!< [4] Arbitration Lost */
 542         uint8_t BUSY : 1;              /*!< [5] Bus Busy */
 543         uint8_t IAAS : 1;              /*!< [6] Addressed As A Slave */
 544         uint8_t TCF : 1;               /*!< [7] Transfer Complete Flag */
 545     } B;
 546 } hw_i2c_s_t;
 547
 548 /*!
 549  * @name Constants and macros for entire I2C_S register
 550  */
 551 /*@{*/
 552 #define HW_I2C_S_ADDR(x)         ((x) + 0x3U)
 553
 554 #define HW_I2C_S(x)              (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
 555 #define HW_I2C_S_RD(x)           (HW_I2C_S(x).U)
 556 #define HW_I2C_S_WR(x, v)        (HW_I2C_S(x).U = (v))
 557 #define HW_I2C_S_SET(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) |  (v)))
 558 #define HW_I2C_S_CLR(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
 559 #define HW_I2C_S_TOG(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^  (v)))
 560 /*@}*/
 561
 562 /*
 563  * Constants & macros for individual I2C_S bitfields
 564  */
 565
 566 /*!
 567  * @name Register I2C_S, field RXAK[0] (RO)
 568  *
 569  * Values:
 570  * - 0 - Acknowledge signal was received after the completion of one byte of
 571  *     data transmission on the bus
 572  * - 1 - No acknowledge signal detected
 573  */
 574 /*@{*/
 575 #define BP_I2C_S_RXAK        (0U)          /*!< Bit position for I2C_S_RXAK. */
 576 #define BM_I2C_S_RXAK        (0x01U)       /*!< Bit mask for I2C_S_RXAK. */
 577 #define BS_I2C_S_RXAK        (1U)          /*!< Bit field size in bits for I2C_S_RXAK. */
 578
 579 /*! @brief Read current value of the I2C_S_RXAK field. */
 580 #define BR_I2C_S_RXAK(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
 581 /*@}*/
 582
 583 /*!
 584  * @name Register I2C_S, field IICIF[1] (W1C)
 585  *
 586  * This bit sets when an interrupt is pending. This bit must be cleared by
 587  * software by writing 1 to it, such as in the interrupt routine. One of the following
 588  * events can set this bit: One byte transfer, including ACK/NACK bit, completes
 589  * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
 590  * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
 591  * completes if FACK is 1. Match of slave address to calling address including
 592  * primary slave address, range slave address , alert response address, second
 593  * slave address, or general call address. Arbitration lost In SMBus mode, any
 594  * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
 595  * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
 596  * start detection interrupt: In the interrupt service routine, first clear the
 597  * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
 598  * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
 599  * asserted again.
 600  *
 601  * Values:
 602  * - 0 - No interrupt pending
 603  * - 1 - Interrupt pending
 604  */
 605 /*@{*/
 606 #define BP_I2C_S_IICIF       (1U)          /*!< Bit position for I2C_S_IICIF. */
 607 #define BM_I2C_S_IICIF       (0x02U)       /*!< Bit mask for I2C_S_IICIF. */
 608 #define BS_I2C_S_IICIF       (1U)          /*!< Bit field size in bits for I2C_S_IICIF. */
 609
 610 /*! @brief Read current value of the I2C_S_IICIF field. */
 611 #define BR_I2C_S_IICIF(x)    (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
 612
 613 /*! @brief Format value for bitfield I2C_S_IICIF. */
 614 #define BF_I2C_S_IICIF(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_S_IICIF) & BM_I2C_S_IICIF)
 615
 616 /*! @brief Set the IICIF field to a new value. */
 617 #define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
 618 /*@}*/
 619
 620 /*!
 621  * @name Register I2C_S, field SRW[2] (RO)
 622  *
 623  * When addressed as a slave, SRW indicates the value of the R/W command bit of
 624  * the calling address sent to the master.
 625  *
 626  * Values:
 627  * - 0 - Slave receive, master writing to slave
 628  * - 1 - Slave transmit, master reading from slave
 629  */
 630 /*@{*/
 631 #define BP_I2C_S_SRW         (2U)          /*!< Bit position for I2C_S_SRW. */
 632 #define BM_I2C_S_SRW         (0x04U)       /*!< Bit mask for I2C_S_SRW. */
 633 #define BS_I2C_S_SRW         (1U)          /*!< Bit field size in bits for I2C_S_SRW. */
 634
 635 /*! @brief Read current value of the I2C_S_SRW field. */
 636 #define BR_I2C_S_SRW(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
 637 /*@}*/
 638
 639 /*!
 640  * @name Register I2C_S, field RAM[3] (RW)
 641  *
 642  * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
 643  * Any nonzero calling address is received that matches the address in the RA
 644  * register. The calling address is within the range of values of the A1 and RA
 645  * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
 646  * Writing the C1 register with any value clears this bit to 0.
 647  *
 648  * Values:
 649  * - 0 - Not addressed
 650  * - 1 - Addressed as a slave
 651  */
 652 /*@{*/
 653 #define BP_I2C_S_RAM         (3U)          /*!< Bit position for I2C_S_RAM. */
 654 #define BM_I2C_S_RAM         (0x08U)       /*!< Bit mask for I2C_S_RAM. */
 655 #define BS_I2C_S_RAM         (1U)          /*!< Bit field size in bits for I2C_S_RAM. */
 656
 657 /*! @brief Read current value of the I2C_S_RAM field. */
 658 #define BR_I2C_S_RAM(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
 659
 660 /*! @brief Format value for bitfield I2C_S_RAM. */
 661 #define BF_I2C_S_RAM(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_S_RAM) & BM_I2C_S_RAM)
 662
 663 /*! @brief Set the RAM field to a new value. */
 664 #define BW_I2C_S_RAM(x, v)   (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
 665 /*@}*/
 666
 667 /*!
 668  * @name Register I2C_S, field ARBL[4] (W1C)
 669  *
 670  * This bit is set by hardware when the arbitration procedure is lost. The ARBL
 671  * bit must be cleared by software, by writing 1 to it.
 672  *
 673  * Values:
 674  * - 0 - Standard bus operation.
 675  * - 1 - Loss of arbitration.
 676  */
 677 /*@{*/
 678 #define BP_I2C_S_ARBL        (4U)          /*!< Bit position for I2C_S_ARBL. */
 679 #define BM_I2C_S_ARBL        (0x10U)       /*!< Bit mask for I2C_S_ARBL. */
 680 #define BS_I2C_S_ARBL        (1U)          /*!< Bit field size in bits for I2C_S_ARBL. */
 681
 682 /*! @brief Read current value of the I2C_S_ARBL field. */
 683 #define BR_I2C_S_ARBL(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
 684
 685 /*! @brief Format value for bitfield I2C_S_ARBL. */
 686 #define BF_I2C_S_ARBL(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_S_ARBL) & BM_I2C_S_ARBL)
 687
 688 /*! @brief Set the ARBL field to a new value. */
 689 #define BW_I2C_S_ARBL(x, v)  (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
 690 /*@}*/
 691
 692 /*!
 693  * @name Register I2C_S, field BUSY[5] (RO)
 694  *
 695  * Indicates the status of the bus regardless of slave or master mode. This bit
 696  * is set when a START signal is detected and cleared when a STOP signal is
 697  * detected.
 698  *
 699  * Values:
 700  * - 0 - Bus is idle
 701  * - 1 - Bus is busy
 702  */
 703 /*@{*/
 704 #define BP_I2C_S_BUSY        (5U)          /*!< Bit position for I2C_S_BUSY. */
 705 #define BM_I2C_S_BUSY        (0x20U)       /*!< Bit mask for I2C_S_BUSY. */
 706 #define BS_I2C_S_BUSY        (1U)          /*!< Bit field size in bits for I2C_S_BUSY. */
 707
 708 /*! @brief Read current value of the I2C_S_BUSY field. */
 709 #define BR_I2C_S_BUSY(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
 710 /*@}*/
 711
 712 /*!
 713  * @name Register I2C_S, field IAAS[6] (RW)
 714  *
 715  * This bit is set by one of the following conditions: The calling address
 716  * matches the programmed primary slave address in the A1 register, or matches the
 717  * range address in the RA register (which must be set to a nonzero value and under
 718  * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
 719  * received. SMB[SIICAEN] is set and the calling address matches the second programmed
 720  * slave address. ALERTEN is set and an SMBus alert response address is received
 721  * RMEN is set and an address is received that is within the range between the
 722  * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
 723  * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
 724  * value clears this bit.
 725  *
 726  * Values:
 727  * - 0 - Not addressed
 728  * - 1 - Addressed as a slave
 729  */
 730 /*@{*/
 731 #define BP_I2C_S_IAAS        (6U)          /*!< Bit position for I2C_S_IAAS. */
 732 #define BM_I2C_S_IAAS        (0x40U)       /*!< Bit mask for I2C_S_IAAS. */
 733 #define BS_I2C_S_IAAS        (1U)          /*!< Bit field size in bits for I2C_S_IAAS. */
 734
 735 /*! @brief Read current value of the I2C_S_IAAS field. */
 736 #define BR_I2C_S_IAAS(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
 737
 738 /*! @brief Format value for bitfield I2C_S_IAAS. */
 739 #define BF_I2C_S_IAAS(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_S_IAAS) & BM_I2C_S_IAAS)
 740
 741 /*! @brief Set the IAAS field to a new value. */
 742 #define BW_I2C_S_IAAS(x, v)  (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
 743 /*@}*/
 744
 745 /*!
 746  * @name Register I2C_S, field TCF[7] (RO)
 747  *
 748  * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
 749  * This bit is valid only during or immediately following a transfer to or from
 750  * the I2C module. TCF is cleared by reading the I2C data register in receive mode
 751  * or by writing to the I2C data register in transmit mode.
 752  *
 753  * Values:
 754  * - 0 - Transfer in progress
 755  * - 1 - Transfer complete
 756  */
 757 /*@{*/
 758 #define BP_I2C_S_TCF         (7U)          /*!< Bit position for I2C_S_TCF. */
 759 #define BM_I2C_S_TCF         (0x80U)       /*!< Bit mask for I2C_S_TCF. */
 760 #define BS_I2C_S_TCF         (1U)          /*!< Bit field size in bits for I2C_S_TCF. */
 761
 762 /*! @brief Read current value of the I2C_S_TCF field. */
 763 #define BR_I2C_S_TCF(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
 764 /*@}*/
 765
 766 /*******************************************************************************
 767  * HW_I2C_D - I2C Data I/O register
 768  ******************************************************************************/
 769
 770 /*!
 771  * @brief HW_I2C_D - I2C Data I/O register (RW)
 772  *
 773  * Reset value: 0x00U
 774  */
 775 typedef union _hw_i2c_d
 776 {
 777     uint8_t U;
 778     struct _hw_i2c_d_bitfields
 779     {
 780         uint8_t DATA : 8;              /*!< [7:0] Data */
 781     } B;
 782 } hw_i2c_d_t;
 783
 784 /*!
 785  * @name Constants and macros for entire I2C_D register
 786  */
 787 /*@{*/
 788 #define HW_I2C_D_ADDR(x)         ((x) + 0x4U)
 789
 790 #define HW_I2C_D(x)              (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
 791 #define HW_I2C_D_RD(x)           (HW_I2C_D(x).U)
 792 #define HW_I2C_D_WR(x, v)        (HW_I2C_D(x).U = (v))
 793 #define HW_I2C_D_SET(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) |  (v)))
 794 #define HW_I2C_D_CLR(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
 795 #define HW_I2C_D_TOG(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^  (v)))
 796 /*@}*/
 797
 798 /*
 799  * Constants & macros for individual I2C_D bitfields
 800  */
 801
 802 /*!
 803  * @name Register I2C_D, field DATA[7:0] (RW)
 804  *
 805  * In master transmit mode, when data is written to this register, a data
 806  * transfer is initiated. The most significant bit is sent first. In master receive
 807  * mode, reading this register initiates receiving of the next byte of data. When
 808  * making the transition out of master receive mode, switch the I2C mode before
 809  * reading the Data register to prevent an inadvertent initiation of a master
 810  * receive data transfer. In slave mode, the same functions are available after an
 811  * address match occurs. The C1[TX] bit must correctly reflect the desired direction
 812  * of transfer in master and slave modes for the transmission to begin. For
 813  * example, if the I2C module is configured for master transmit but a master receive
 814  * is desired, reading the Data register does not initiate the receive. Reading
 815  * the Data register returns the last byte received while the I2C module is
 816  * configured in master receive or slave receive mode. The Data register does not
 817  * reflect every byte that is transmitted on the I2C bus, and neither can software
 818  * verify that a byte has been written to the Data register correctly by reading it
 819  * back. In master transmit mode, the first byte of data written to the Data
 820  * register following assertion of MST (start bit) or assertion of RSTA (repeated
 821  * start bit) is used for the address transfer and must consist of the calling
 822  * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
 823  */
 824 /*@{*/
 825 #define BP_I2C_D_DATA        (0U)          /*!< Bit position for I2C_D_DATA. */
 826 #define BM_I2C_D_DATA        (0xFFU)       /*!< Bit mask for I2C_D_DATA. */
 827 #define BS_I2C_D_DATA        (8U)          /*!< Bit field size in bits for I2C_D_DATA. */
 828
 829 /*! @brief Read current value of the I2C_D_DATA field. */
 830 #define BR_I2C_D_DATA(x)     (HW_I2C_D(x).U)
 831
 832 /*! @brief Format value for bitfield I2C_D_DATA. */
 833 #define BF_I2C_D_DATA(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_D_DATA) & BM_I2C_D_DATA)
 834
 835 /*! @brief Set the DATA field to a new value. */
 836 #define BW_I2C_D_DATA(x, v)  (HW_I2C_D_WR(x, v))
 837 /*@}*/
 838
 839 /*******************************************************************************
 840  * HW_I2C_C2 - I2C Control Register 2
 841  ******************************************************************************/
 842
 843 /*!
 844  * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
 845  *
 846  * Reset value: 0x00U
 847  */
 848 typedef union _hw_i2c_c2
 849 {
 850     uint8_t U;
 851     struct _hw_i2c_c2_bitfields
 852     {
 853         uint8_t AD : 3;                /*!< [2:0] Slave Address */
 854         uint8_t RMEN : 1;              /*!< [3] Range Address Matching Enable */
 855         uint8_t SBRC : 1;              /*!< [4] Slave Baud Rate Control */
 856         uint8_t HDRS : 1;              /*!< [5] High Drive Select */
 857         uint8_t ADEXT : 1;             /*!< [6] Address Extension */
 858         uint8_t GCAEN : 1;             /*!< [7] General Call Address Enable */
 859     } B;
 860 } hw_i2c_c2_t;
 861
 862 /*!
 863  * @name Constants and macros for entire I2C_C2 register
 864  */
 865 /*@{*/
 866 #define HW_I2C_C2_ADDR(x)        ((x) + 0x5U)
 867
 868 #define HW_I2C_C2(x)             (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
 869 #define HW_I2C_C2_RD(x)          (HW_I2C_C2(x).U)
 870 #define HW_I2C_C2_WR(x, v)       (HW_I2C_C2(x).U = (v))
 871 #define HW_I2C_C2_SET(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) |  (v)))
 872 #define HW_I2C_C2_CLR(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
 873 #define HW_I2C_C2_TOG(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^  (v)))
 874 /*@}*/
 875
 876 /*
 877  * Constants & macros for individual I2C_C2 bitfields
 878  */
 879
 880 /*!
 881  * @name Register I2C_C2, field AD[2:0] (RW)
 882  *
 883  * Contains the upper three bits of the slave address in the 10-bit address
 884  * scheme. This field is valid only while the ADEXT bit is set.
 885  */
 886 /*@{*/
 887 #define BP_I2C_C2_AD         (0U)          /*!< Bit position for I2C_C2_AD. */
 888 #define BM_I2C_C2_AD         (0x07U)       /*!< Bit mask for I2C_C2_AD. */
 889 #define BS_I2C_C2_AD         (3U)          /*!< Bit field size in bits for I2C_C2_AD. */
 890
 891 /*! @brief Read current value of the I2C_C2_AD field. */
 892 #define BR_I2C_C2_AD(x)      (HW_I2C_C2(x).B.AD)
 893
 894 /*! @brief Format value for bitfield I2C_C2_AD. */
 895 #define BF_I2C_C2_AD(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_C2_AD) & BM_I2C_C2_AD)
 896
 897 /*! @brief Set the AD field to a new value. */
 898 #define BW_I2C_C2_AD(x, v)   (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
 899 /*@}*/
 900
 901 /*!
 902  * @name Register I2C_C2, field RMEN[3] (RW)
 903  *
 904  * This bit controls the slave address matching for addresses between the values
 905  * of the A1 and RA registers. When this bit is set, a slave address matching
 906  * occurs for any address greater than the value of the A1 register and less than
 907  * or equal to the value of the RA register.
 908  *
 909  * Values:
 910  * - 0 - Range mode disabled. No address matching occurs for an address within
 911  *     the range of values of the A1 and RA registers.
 912  * - 1 - Range mode enabled. Address matching occurs when a slave receives an
 913  *     address within the range of values of the A1 and RA registers.
 914  */
 915 /*@{*/
 916 #define BP_I2C_C2_RMEN       (3U)          /*!< Bit position for I2C_C2_RMEN. */
 917 #define BM_I2C_C2_RMEN       (0x08U)       /*!< Bit mask for I2C_C2_RMEN. */
 918 #define BS_I2C_C2_RMEN       (1U)          /*!< Bit field size in bits for I2C_C2_RMEN. */
 919
 920 /*! @brief Read current value of the I2C_C2_RMEN field. */
 921 #define BR_I2C_C2_RMEN(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
 922
 923 /*! @brief Format value for bitfield I2C_C2_RMEN. */
 924 #define BF_I2C_C2_RMEN(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_RMEN) & BM_I2C_C2_RMEN)
 925
 926 /*! @brief Set the RMEN field to a new value. */
 927 #define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
 928 /*@}*/
 929
 930 /*!
 931  * @name Register I2C_C2, field SBRC[4] (RW)
 932  *
 933  * Enables independent slave mode baud rate at maximum frequency, which forces
 934  * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
 935  * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
 936  * capture the master's data at only 10 kbit/s.
 937  *
 938  * Values:
 939  * - 0 - The slave baud rate follows the master baud rate and clock stretching
 940  *     may occur
 941  * - 1 - Slave baud rate is independent of the master baud rate
 942  */
 943 /*@{*/
 944 #define BP_I2C_C2_SBRC       (4U)          /*!< Bit position for I2C_C2_SBRC. */
 945 #define BM_I2C_C2_SBRC       (0x10U)       /*!< Bit mask for I2C_C2_SBRC. */
 946 #define BS_I2C_C2_SBRC       (1U)          /*!< Bit field size in bits for I2C_C2_SBRC. */
 947
 948 /*! @brief Read current value of the I2C_C2_SBRC field. */
 949 #define BR_I2C_C2_SBRC(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
 950
 951 /*! @brief Format value for bitfield I2C_C2_SBRC. */
 952 #define BF_I2C_C2_SBRC(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_SBRC) & BM_I2C_C2_SBRC)
 953
 954 /*! @brief Set the SBRC field to a new value. */
 955 #define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
 956 /*@}*/
 957
 958 /*!
 959  * @name Register I2C_C2, field HDRS[5] (RW)
 960  *
 961  * Controls the drive capability of the I2C pads.
 962  *
 963  * Values:
 964  * - 0 - Normal drive mode
 965  * - 1 - High drive mode
 966  */
 967 /*@{*/
 968 #define BP_I2C_C2_HDRS       (5U)          /*!< Bit position for I2C_C2_HDRS. */
 969 #define BM_I2C_C2_HDRS       (0x20U)       /*!< Bit mask for I2C_C2_HDRS. */
 970 #define BS_I2C_C2_HDRS       (1U)          /*!< Bit field size in bits for I2C_C2_HDRS. */
 971
 972 /*! @brief Read current value of the I2C_C2_HDRS field. */
 973 #define BR_I2C_C2_HDRS(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
 974
 975 /*! @brief Format value for bitfield I2C_C2_HDRS. */
 976 #define BF_I2C_C2_HDRS(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_HDRS) & BM_I2C_C2_HDRS)
 977
 978 /*! @brief Set the HDRS field to a new value. */
 979 #define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
 980 /*@}*/
 981
 982 /*!
 983  * @name Register I2C_C2, field ADEXT[6] (RW)
 984  *
 985  * Controls the number of bits used for the slave address.
 986  *
 987  * Values:
 988  * - 0 - 7-bit address scheme
 989  * - 1 - 10-bit address scheme
 990  */
 991 /*@{*/
 992 #define BP_I2C_C2_ADEXT      (6U)          /*!< Bit position for I2C_C2_ADEXT. */
 993 #define BM_I2C_C2_ADEXT      (0x40U)       /*!< Bit mask for I2C_C2_ADEXT. */
 994 #define BS_I2C_C2_ADEXT      (1U)          /*!< Bit field size in bits for I2C_C2_ADEXT. */
 995
 996 /*! @brief Read current value of the I2C_C2_ADEXT field. */
 997 #define BR_I2C_C2_ADEXT(x)   (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
 998
 999 /*! @brief Format value for bitfield I2C_C2_ADEXT. */
1000 #define BF_I2C_C2_ADEXT(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C2_ADEXT) & BM_I2C_C2_ADEXT)
1001
1002 /*! @brief Set the ADEXT field to a new value. */
1003 #define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
1004 /*@}*/
1005
1006 /*!
1007  * @name Register I2C_C2, field GCAEN[7] (RW)
1008  *
1009  * Enables general call address.
1010  *
1011  * Values:
1012  * - 0 - Disabled
1013  * - 1 - Enabled
1014  */
1015 /*@{*/
1016 #define BP_I2C_C2_GCAEN      (7U)          /*!< Bit position for I2C_C2_GCAEN. */
1017 #define BM_I2C_C2_GCAEN      (0x80U)       /*!< Bit mask for I2C_C2_GCAEN. */
1018 #define BS_I2C_C2_GCAEN      (1U)          /*!< Bit field size in bits for I2C_C2_GCAEN. */
1019
1020 /*! @brief Read current value of the I2C_C2_GCAEN field. */
1021 #define BR_I2C_C2_GCAEN(x)   (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
1022
1023 /*! @brief Format value for bitfield I2C_C2_GCAEN. */
1024 #define BF_I2C_C2_GCAEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C2_GCAEN) & BM_I2C_C2_GCAEN)
1025
1026 /*! @brief Set the GCAEN field to a new value. */
1027 #define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
1028 /*@}*/
1029
1030 /*******************************************************************************
1031  * HW_I2C_FLT - I2C Programmable Input Glitch Filter register
1032  ******************************************************************************/
1033
1034 /*!
1035  * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
1036  *
1037  * Reset value: 0x00U
1038  */
1039 typedef union _hw_i2c_flt
1040 {
1041     uint8_t U;
1042     struct _hw_i2c_flt_bitfields
1043     {
1044         uint8_t FLT : 4;               /*!< [3:0] I2C Programmable Filter Factor */
1045         uint8_t STARTF : 1;            /*!< [4] I2C Bus Start Detect Flag */
1046         uint8_t SSIE : 1;              /*!< [5] I2C Bus Stop or Start Interrupt Enable */
1047         uint8_t STOPF : 1;             /*!< [6] I2C Bus Stop Detect Flag */
1048         uint8_t SHEN : 1;              /*!< [7] Stop Hold Enable */
1049     } B;
1050 } hw_i2c_flt_t;
1051
1052 /*!
1053  * @name Constants and macros for entire I2C_FLT register
1054  */
1055 /*@{*/
1056 #define HW_I2C_FLT_ADDR(x)       ((x) + 0x6U)
1057
1058 #define HW_I2C_FLT(x)            (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
1059 #define HW_I2C_FLT_RD(x)         (HW_I2C_FLT(x).U)
1060 #define HW_I2C_FLT_WR(x, v)      (HW_I2C_FLT(x).U = (v))
1061 #define HW_I2C_FLT_SET(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) |  (v)))
1062 #define HW_I2C_FLT_CLR(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
1063 #define HW_I2C_FLT_TOG(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^  (v)))
1064 /*@}*/
1065
1066 /*
1067  * Constants & macros for individual I2C_FLT bitfields
1068  */
1069
1070 /*!
1071  * @name Register I2C_FLT, field FLT[3:0] (RW)
1072  *
1073  * Controls the width of the glitch, in terms of I2C module clock cycles, that
1074  * the filter must absorb. For any glitch whose size is less than or equal to this
1075  * width setting, the filter does not allow the glitch to pass.
1076  *
1077  * Values:
1078  * - 0 - No filter/bypass
1079  */
1080 /*@{*/
1081 #define BP_I2C_FLT_FLT       (0U)          /*!< Bit position for I2C_FLT_FLT. */
1082 #define BM_I2C_FLT_FLT       (0x0FU)       /*!< Bit mask for I2C_FLT_FLT. */
1083 #define BS_I2C_FLT_FLT       (4U)          /*!< Bit field size in bits for I2C_FLT_FLT. */
1084
1085 /*! @brief Read current value of the I2C_FLT_FLT field. */
1086 #define BR_I2C_FLT_FLT(x)    (HW_I2C_FLT(x).B.FLT)
1087
1088 /*! @brief Format value for bitfield I2C_FLT_FLT. */
1089 #define BF_I2C_FLT_FLT(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_FLT) & BM_I2C_FLT_FLT)
1090
1091 /*! @brief Set the FLT field to a new value. */
1092 #define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
1093 /*@}*/
1094
1095 /*!
1096  * @name Register I2C_FLT, field STARTF[4] (W1C)
1097  *
1098  * Hardware sets this bit when the I2C bus's start status is detected. The
1099  * STARTF bit must be cleared by writing 1 to it.
1100  *
1101  * Values:
1102  * - 0 - No start happens on I2C bus
1103  * - 1 - Start detected on I2C bus
1104  */
1105 /*@{*/
1106 #define BP_I2C_FLT_STARTF    (4U)          /*!< Bit position for I2C_FLT_STARTF. */
1107 #define BM_I2C_FLT_STARTF    (0x10U)       /*!< Bit mask for I2C_FLT_STARTF. */
1108 #define BS_I2C_FLT_STARTF    (1U)          /*!< Bit field size in bits for I2C_FLT_STARTF. */
1109
1110 /*! @brief Read current value of the I2C_FLT_STARTF field. */
1111 #define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
1112
1113 /*! @brief Format value for bitfield I2C_FLT_STARTF. */
1114 #define BF_I2C_FLT_STARTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STARTF) & BM_I2C_FLT_STARTF)
1115
1116 /*! @brief Set the STARTF field to a new value. */
1117 #define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
1118 /*@}*/
1119
1120 /*!
1121  * @name Register I2C_FLT, field SSIE[5] (RW)
1122  *
1123  * This bit enables the interrupt for I2C bus stop or start detection. To clear
1124  * the I2C bus stop or start detection interrupt: In the interrupt service
1125  * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
1126  * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
1127  * is asserted again.
1128  *
1129  * Values:
1130  * - 0 - Stop or start detection interrupt is disabled
1131  * - 1 - Stop or start detection interrupt is enabled
1132  */
1133 /*@{*/
1134 #define BP_I2C_FLT_SSIE      (5U)          /*!< Bit position for I2C_FLT_SSIE. */
1135 #define BM_I2C_FLT_SSIE      (0x20U)       /*!< Bit mask for I2C_FLT_SSIE. */
1136 #define BS_I2C_FLT_SSIE      (1U)          /*!< Bit field size in bits for I2C_FLT_SSIE. */
1137
1138 /*! @brief Read current value of the I2C_FLT_SSIE field. */
1139 #define BR_I2C_FLT_SSIE(x)   (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
1140
1141 /*! @brief Format value for bitfield I2C_FLT_SSIE. */
1142 #define BF_I2C_FLT_SSIE(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SSIE) & BM_I2C_FLT_SSIE)
1143
1144 /*! @brief Set the SSIE field to a new value. */
1145 #define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
1146 /*@}*/
1147
1148 /*!
1149  * @name Register I2C_FLT, field STOPF[6] (W1C)
1150  *
1151  * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
1152  * bit must be cleared by writing 1 to it.
1153  *
1154  * Values:
1155  * - 0 - No stop happens on I2C bus
1156  * - 1 - Stop detected on I2C bus
1157  */
1158 /*@{*/
1159 #define BP_I2C_FLT_STOPF     (6U)          /*!< Bit position for I2C_FLT_STOPF. */
1160 #define BM_I2C_FLT_STOPF     (0x40U)       /*!< Bit mask for I2C_FLT_STOPF. */
1161 #define BS_I2C_FLT_STOPF     (1U)          /*!< Bit field size in bits for I2C_FLT_STOPF. */
1162
1163 /*! @brief Read current value of the I2C_FLT_STOPF field. */
1164 #define BR_I2C_FLT_STOPF(x)  (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
1165
1166 /*! @brief Format value for bitfield I2C_FLT_STOPF. */
1167 #define BF_I2C_FLT_STOPF(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STOPF) & BM_I2C_FLT_STOPF)
1168
1169 /*! @brief Set the STOPF field to a new value. */
1170 #define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
1171 /*@}*/
1172
1173 /*!
1174  * @name Register I2C_FLT, field SHEN[7] (RW)
1175  *
1176  * Set this bit to hold off entry to stop mode when any data transmission or
1177  * reception is occurring. The following scenario explains the holdoff
1178  * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
1179  * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
1180  * byte currently being transferred, including both address and data, completes
1181  * its transfer. The I2C slave or master acknowledges that the in-transfer byte
1182  * completed its transfer and acknowledges the request to enter stop mode. After
1183  * receiving the I2C module's acknowledgment of the request to enter stop mode,
1184  * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
1185  * is set to 1 and the I2C module is in an idle or disabled state when the MCU
1186  * signals to enter stop mode, the module immediately acknowledges the request to
1187  * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
1188  * reception that was suspended by stop mode entry was incomplete: To resume the
1189  * overall transmission or reception after the MCU exits stop mode, software must
1190  * reinitialize the transfer by resending the address of the slave. If the I2C
1191  * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
1192  * system software will receive the interrupt triggered by the I2C Status Register's
1193  * TCF bit after the MCU wakes from the stop mode.
1194  *
1195  * Values:
1196  * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1197  * - 1 - Stop holdoff is enabled.
1198  */
1199 /*@{*/
1200 #define BP_I2C_FLT_SHEN      (7U)          /*!< Bit position for I2C_FLT_SHEN. */
1201 #define BM_I2C_FLT_SHEN      (0x80U)       /*!< Bit mask for I2C_FLT_SHEN. */
1202 #define BS_I2C_FLT_SHEN      (1U)          /*!< Bit field size in bits for I2C_FLT_SHEN. */
1203
1204 /*! @brief Read current value of the I2C_FLT_SHEN field. */
1205 #define BR_I2C_FLT_SHEN(x)   (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
1206
1207 /*! @brief Format value for bitfield I2C_FLT_SHEN. */
1208 #define BF_I2C_FLT_SHEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SHEN) & BM_I2C_FLT_SHEN)
1209
1210 /*! @brief Set the SHEN field to a new value. */
1211 #define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
1212 /*@}*/
1213
1214 /*******************************************************************************
1215  * HW_I2C_RA - I2C Range Address register
1216  ******************************************************************************/
1217
1218 /*!
1219  * @brief HW_I2C_RA - I2C Range Address register (RW)
1220  *
1221  * Reset value: 0x00U
1222  */
1223 typedef union _hw_i2c_ra
1224 {
1225     uint8_t U;
1226     struct _hw_i2c_ra_bitfields
1227     {
1228         uint8_t RESERVED0 : 1;         /*!< [0]  */
1229         uint8_t RAD : 7;               /*!< [7:1] Range Slave Address */
1230     } B;
1231 } hw_i2c_ra_t;
1232
1233 /*!
1234  * @name Constants and macros for entire I2C_RA register
1235  */
1236 /*@{*/
1237 #define HW_I2C_RA_ADDR(x)        ((x) + 0x7U)
1238
1239 #define HW_I2C_RA(x)             (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
1240 #define HW_I2C_RA_RD(x)          (HW_I2C_RA(x).U)
1241 #define HW_I2C_RA_WR(x, v)       (HW_I2C_RA(x).U = (v))
1242 #define HW_I2C_RA_SET(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) |  (v)))
1243 #define HW_I2C_RA_CLR(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
1244 #define HW_I2C_RA_TOG(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^  (v)))
1245 /*@}*/
1246
1247 /*
1248  * Constants & macros for individual I2C_RA bitfields
1249  */
1250
1251 /*!
1252  * @name Register I2C_RA, field RAD[7:1] (RW)
1253  *
1254  * This field contains the slave address to be used by the I2C module. The field
1255  * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
1256  * value write enables this register. This register value can be considered as a
1257  * maximum boundary in the range matching mode.
1258  */
1259 /*@{*/
1260 #define BP_I2C_RA_RAD        (1U)          /*!< Bit position for I2C_RA_RAD. */
1261 #define BM_I2C_RA_RAD        (0xFEU)       /*!< Bit mask for I2C_RA_RAD. */
1262 #define BS_I2C_RA_RAD        (7U)          /*!< Bit field size in bits for I2C_RA_RAD. */
1263
1264 /*! @brief Read current value of the I2C_RA_RAD field. */
1265 #define BR_I2C_RA_RAD(x)     (HW_I2C_RA(x).B.RAD)
1266
1267 /*! @brief Format value for bitfield I2C_RA_RAD. */
1268 #define BF_I2C_RA_RAD(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_RA_RAD) & BM_I2C_RA_RAD)
1269
1270 /*! @brief Set the RAD field to a new value. */
1271 #define BW_I2C_RA_RAD(x, v)  (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
1272 /*@}*/
1273
1274 /*******************************************************************************
1275  * HW_I2C_SMB - I2C SMBus Control and Status register
1276  ******************************************************************************/
1277
1278 /*!
1279  * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
1280  *
1281  * Reset value: 0x00U
1282  *
1283  * When the SCL and SDA signals are held high for a length of time greater than
1284  * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
1285  * while the system is detecting how long these signals are being held high, a
1286  * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
1287  * bus transmission process with the idle bus state. When the TCKSEL bit is set,
1288  * there is no need to monitor the SHTF1 bit because the bus speed is too high to
1289  * match the protocol of SMBus.
1290  */
1291 typedef union _hw_i2c_smb
1292 {
1293     uint8_t U;
1294     struct _hw_i2c_smb_bitfields
1295     {
1296         uint8_t SHTF2IE : 1;           /*!< [0] SHTF2 Interrupt Enable */
1297         uint8_t SHTF2 : 1;             /*!< [1] SCL High Timeout Flag 2 */
1298         uint8_t SHTF1 : 1;             /*!< [2] SCL High Timeout Flag 1 */
1299         uint8_t SLTF : 1;              /*!< [3] SCL Low Timeout Flag */
1300         uint8_t TCKSEL : 1;            /*!< [4] Timeout Counter Clock Select */
1301         uint8_t SIICAEN : 1;           /*!< [5] Second I2C Address Enable */
1302         uint8_t ALERTEN : 1;           /*!< [6] SMBus Alert Response Address Enable */
1303         uint8_t FACK : 1;              /*!< [7] Fast NACK/ACK Enable */
1304     } B;
1305 } hw_i2c_smb_t;
1306
1307 /*!
1308  * @name Constants and macros for entire I2C_SMB register
1309  */
1310 /*@{*/
1311 #define HW_I2C_SMB_ADDR(x)       ((x) + 0x8U)
1312
1313 #define HW_I2C_SMB(x)            (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
1314 #define HW_I2C_SMB_RD(x)         (HW_I2C_SMB(x).U)
1315 #define HW_I2C_SMB_WR(x, v)      (HW_I2C_SMB(x).U = (v))
1316 #define HW_I2C_SMB_SET(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) |  (v)))
1317 #define HW_I2C_SMB_CLR(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
1318 #define HW_I2C_SMB_TOG(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^  (v)))
1319 /*@}*/
1320
1321 /*
1322  * Constants & macros for individual I2C_SMB bitfields
1323  */
1324
1325 /*!
1326  * @name Register I2C_SMB, field SHTF2IE[0] (RW)
1327  *
1328  * Enables SCL high and SDA low timeout interrupt.
1329  *
1330  * Values:
1331  * - 0 - SHTF2 interrupt is disabled
1332  * - 1 - SHTF2 interrupt is enabled
1333  */
1334 /*@{*/
1335 #define BP_I2C_SMB_SHTF2IE   (0U)          /*!< Bit position for I2C_SMB_SHTF2IE. */
1336 #define BM_I2C_SMB_SHTF2IE   (0x01U)       /*!< Bit mask for I2C_SMB_SHTF2IE. */
1337 #define BS_I2C_SMB_SHTF2IE   (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF2IE. */
1338
1339 /*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
1340 #define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
1341
1342 /*! @brief Format value for bitfield I2C_SMB_SHTF2IE. */
1343 #define BF_I2C_SMB_SHTF2IE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2IE) & BM_I2C_SMB_SHTF2IE)
1344
1345 /*! @brief Set the SHTF2IE field to a new value. */
1346 #define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
1347 /*@}*/
1348
1349 /*!
1350  * @name Register I2C_SMB, field SHTF2[1] (W1C)
1351  *
1352  * This bit sets when SCL is held high and SDA is held low more than clock *
1353  * LoValue / 512. Software clears this bit by writing 1 to it.
1354  *
1355  * Values:
1356  * - 0 - No SCL high and SDA low timeout occurs
1357  * - 1 - SCL high and SDA low timeout occurs
1358  */
1359 /*@{*/
1360 #define BP_I2C_SMB_SHTF2     (1U)          /*!< Bit position for I2C_SMB_SHTF2. */
1361 #define BM_I2C_SMB_SHTF2     (0x02U)       /*!< Bit mask for I2C_SMB_SHTF2. */
1362 #define BS_I2C_SMB_SHTF2     (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF2. */
1363
1364 /*! @brief Read current value of the I2C_SMB_SHTF2 field. */
1365 #define BR_I2C_SMB_SHTF2(x)  (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
1366
1367 /*! @brief Format value for bitfield I2C_SMB_SHTF2. */
1368 #define BF_I2C_SMB_SHTF2(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2) & BM_I2C_SMB_SHTF2)
1369
1370 /*! @brief Set the SHTF2 field to a new value. */
1371 #define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
1372 /*@}*/
1373
1374 /*!
1375  * @name Register I2C_SMB, field SHTF1[2] (RO)
1376  *
1377  * This read-only bit sets when SCL and SDA are held high more than clock *
1378  * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
1379  *
1380  * Values:
1381  * - 0 - No SCL high and SDA high timeout occurs
1382  * - 1 - SCL high and SDA high timeout occurs
1383  */
1384 /*@{*/
1385 #define BP_I2C_SMB_SHTF1     (2U)          /*!< Bit position for I2C_SMB_SHTF1. */
1386 #define BM_I2C_SMB_SHTF1     (0x04U)       /*!< Bit mask for I2C_SMB_SHTF1. */
1387 #define BS_I2C_SMB_SHTF1     (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF1. */
1388
1389 /*! @brief Read current value of the I2C_SMB_SHTF1 field. */
1390 #define BR_I2C_SMB_SHTF1(x)  (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
1391 /*@}*/
1392
1393 /*!
1394  * @name Register I2C_SMB, field SLTF[3] (W1C)
1395  *
1396  * This bit is set when the SLT register (consisting of the SLTH and SLTL
1397  * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
1398  * Software clears this bit by writing a logic 1 to it. The low timeout function
1399  * is disabled when the SLT register's value is 0.
1400  *
1401  * Values:
1402  * - 0 - No low timeout occurs
1403  * - 1 - Low timeout occurs
1404  */
1405 /*@{*/
1406 #define BP_I2C_SMB_SLTF      (3U)          /*!< Bit position for I2C_SMB_SLTF. */
1407 #define BM_I2C_SMB_SLTF      (0x08U)       /*!< Bit mask for I2C_SMB_SLTF. */
1408 #define BS_I2C_SMB_SLTF      (1U)          /*!< Bit field size in bits for I2C_SMB_SLTF. */
1409
1410 /*! @brief Read current value of the I2C_SMB_SLTF field. */
1411 #define BR_I2C_SMB_SLTF(x)   (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
1412
1413 /*! @brief Format value for bitfield I2C_SMB_SLTF. */
1414 #define BF_I2C_SMB_SLTF(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SLTF) & BM_I2C_SMB_SLTF)
1415
1416 /*! @brief Set the SLTF field to a new value. */
1417 #define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
1418 /*@}*/
1419
1420 /*!
1421  * @name Register I2C_SMB, field TCKSEL[4] (RW)
1422  *
1423  * Selects the clock source of the timeout counter.
1424  *
1425  * Values:
1426  * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
1427  * - 1 - Timeout counter counts at the frequency of the I2C module clock
1428  */
1429 /*@{*/
1430 #define BP_I2C_SMB_TCKSEL    (4U)          /*!< Bit position for I2C_SMB_TCKSEL. */
1431 #define BM_I2C_SMB_TCKSEL    (0x10U)       /*!< Bit mask for I2C_SMB_TCKSEL. */
1432 #define BS_I2C_SMB_TCKSEL    (1U)          /*!< Bit field size in bits for I2C_SMB_TCKSEL. */
1433
1434 /*! @brief Read current value of the I2C_SMB_TCKSEL field. */
1435 #define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
1436
1437 /*! @brief Format value for bitfield I2C_SMB_TCKSEL. */
1438 #define BF_I2C_SMB_TCKSEL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_TCKSEL) & BM_I2C_SMB_TCKSEL)
1439
1440 /*! @brief Set the TCKSEL field to a new value. */
1441 #define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
1442 /*@}*/
1443
1444 /*!
1445  * @name Register I2C_SMB, field SIICAEN[5] (RW)
1446  *
1447  * Enables or disables SMBus device default address.
1448  *
1449  * Values:
1450  * - 0 - I2C address register 2 matching is disabled
1451  * - 1 - I2C address register 2 matching is enabled
1452  */
1453 /*@{*/
1454 #define BP_I2C_SMB_SIICAEN   (5U)          /*!< Bit position for I2C_SMB_SIICAEN. */
1455 #define BM_I2C_SMB_SIICAEN   (0x20U)       /*!< Bit mask for I2C_SMB_SIICAEN. */
1456 #define BS_I2C_SMB_SIICAEN   (1U)          /*!< Bit field size in bits for I2C_SMB_SIICAEN. */
1457
1458 /*! @brief Read current value of the I2C_SMB_SIICAEN field. */
1459 #define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
1460
1461 /*! @brief Format value for bitfield I2C_SMB_SIICAEN. */
1462 #define BF_I2C_SMB_SIICAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SIICAEN) & BM_I2C_SMB_SIICAEN)
1463
1464 /*! @brief Set the SIICAEN field to a new value. */
1465 #define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
1466 /*@}*/
1467
1468 /*!
1469  * @name Register I2C_SMB, field ALERTEN[6] (RW)
1470  *
1471  * Enables or disables SMBus alert response address matching. After the host
1472  * responds to a device that used the alert response address, you must use software
1473  * to put the device's address on the bus. The alert protocol is described in the
1474  * SMBus specification.
1475  *
1476  * Values:
1477  * - 0 - SMBus alert response address matching is disabled
1478  * - 1 - SMBus alert response address matching is enabled
1479  */
1480 /*@{*/
1481 #define BP_I2C_SMB_ALERTEN   (6U)          /*!< Bit position for I2C_SMB_ALERTEN. */
1482 #define BM_I2C_SMB_ALERTEN   (0x40U)       /*!< Bit mask for I2C_SMB_ALERTEN. */
1483 #define BS_I2C_SMB_ALERTEN   (1U)          /*!< Bit field size in bits for I2C_SMB_ALERTEN. */
1484
1485 /*! @brief Read current value of the I2C_SMB_ALERTEN field. */
1486 #define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
1487
1488 /*! @brief Format value for bitfield I2C_SMB_ALERTEN. */
1489 #define BF_I2C_SMB_ALERTEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_ALERTEN) & BM_I2C_SMB_ALERTEN)
1490
1491 /*! @brief Set the ALERTEN field to a new value. */
1492 #define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
1493 /*@}*/
1494
1495 /*!
1496  * @name Register I2C_SMB, field FACK[7] (RW)
1497  *
1498  * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
1499  * according to the result of receiving data byte.
1500  *
1501  * Values:
1502  * - 0 - An ACK or NACK is sent on the following receiving data byte
1503  * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
1504  *     1 to TXAK after receiving a data byte generates a NACK.
1505  */
1506 /*@{*/
1507 #define BP_I2C_SMB_FACK      (7U)          /*!< Bit position for I2C_SMB_FACK. */
1508 #define BM_I2C_SMB_FACK      (0x80U)       /*!< Bit mask for I2C_SMB_FACK. */
1509 #define BS_I2C_SMB_FACK      (1U)          /*!< Bit field size in bits for I2C_SMB_FACK. */
1510
1511 /*! @brief Read current value of the I2C_SMB_FACK field. */
1512 #define BR_I2C_SMB_FACK(x)   (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
1513
1514 /*! @brief Format value for bitfield I2C_SMB_FACK. */
1515 #define BF_I2C_SMB_FACK(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_FACK) & BM_I2C_SMB_FACK)
1516
1517 /*! @brief Set the FACK field to a new value. */
1518 #define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
1519 /*@}*/
1520
1521 /*******************************************************************************
1522  * HW_I2C_A2 - I2C Address Register 2
1523  ******************************************************************************/
1524
1525 /*!
1526  * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
1527  *
1528  * Reset value: 0xC2U
1529  */
1530 typedef union _hw_i2c_a2
1531 {
1532     uint8_t U;
1533     struct _hw_i2c_a2_bitfields
1534     {
1535         uint8_t RESERVED0 : 1;         /*!< [0]  */
1536         uint8_t SAD : 7;               /*!< [7:1] SMBus Address */
1537     } B;
1538 } hw_i2c_a2_t;
1539
1540 /*!
1541  * @name Constants and macros for entire I2C_A2 register
1542  */
1543 /*@{*/
1544 #define HW_I2C_A2_ADDR(x)        ((x) + 0x9U)
1545
1546 #define HW_I2C_A2(x)             (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
1547 #define HW_I2C_A2_RD(x)          (HW_I2C_A2(x).U)
1548 #define HW_I2C_A2_WR(x, v)       (HW_I2C_A2(x).U = (v))
1549 #define HW_I2C_A2_SET(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) |  (v)))
1550 #define HW_I2C_A2_CLR(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
1551 #define HW_I2C_A2_TOG(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^  (v)))
1552 /*@}*/
1553
1554 /*
1555  * Constants & macros for individual I2C_A2 bitfields
1556  */
1557
1558 /*!
1559  * @name Register I2C_A2, field SAD[7:1] (RW)
1560  *
1561  * Contains the slave address used by the SMBus. This field is used on the
1562  * device default address or other related addresses.
1563  */
1564 /*@{*/
1565 #define BP_I2C_A2_SAD        (1U)          /*!< Bit position for I2C_A2_SAD. */
1566 #define BM_I2C_A2_SAD        (0xFEU)       /*!< Bit mask for I2C_A2_SAD. */
1567 #define BS_I2C_A2_SAD        (7U)          /*!< Bit field size in bits for I2C_A2_SAD. */
1568
1569 /*! @brief Read current value of the I2C_A2_SAD field. */
1570 #define BR_I2C_A2_SAD(x)     (HW_I2C_A2(x).B.SAD)
1571
1572 /*! @brief Format value for bitfield I2C_A2_SAD. */
1573 #define BF_I2C_A2_SAD(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_A2_SAD) & BM_I2C_A2_SAD)
1574
1575 /*! @brief Set the SAD field to a new value. */
1576 #define BW_I2C_A2_SAD(x, v)  (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
1577 /*@}*/
1578
1579 /*******************************************************************************
1580  * HW_I2C_SLTH - I2C SCL Low Timeout Register High
1581  ******************************************************************************/
1582
1583 /*!
1584  * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
1585  *
1586  * Reset value: 0x00U
1587  */
1588 typedef union _hw_i2c_slth
1589 {
1590     uint8_t U;
1591     struct _hw_i2c_slth_bitfields
1592     {
1593         uint8_t SSLT : 8;              /*!< [7:0]  */
1594     } B;
1595 } hw_i2c_slth_t;
1596
1597 /*!
1598  * @name Constants and macros for entire I2C_SLTH register
1599  */
1600 /*@{*/
1601 #define HW_I2C_SLTH_ADDR(x)      ((x) + 0xAU)
1602
1603 #define HW_I2C_SLTH(x)           (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
1604 #define HW_I2C_SLTH_RD(x)        (HW_I2C_SLTH(x).U)
1605 #define HW_I2C_SLTH_WR(x, v)     (HW_I2C_SLTH(x).U = (v))
1606 #define HW_I2C_SLTH_SET(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) |  (v)))
1607 #define HW_I2C_SLTH_CLR(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
1608 #define HW_I2C_SLTH_TOG(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^  (v)))
1609 /*@}*/
1610
1611 /*
1612  * Constants & macros for individual I2C_SLTH bitfields
1613  */
1614
1615 /*!
1616  * @name Register I2C_SLTH, field SSLT[7:0] (RW)
1617  *
1618  * Most significant byte of SCL low timeout value that determines the timeout
1619  * period of SCL low.
1620  */
1621 /*@{*/
1622 #define BP_I2C_SLTH_SSLT     (0U)          /*!< Bit position for I2C_SLTH_SSLT. */
1623 #define BM_I2C_SLTH_SSLT     (0xFFU)       /*!< Bit mask for I2C_SLTH_SSLT. */
1624 #define BS_I2C_SLTH_SSLT     (8U)          /*!< Bit field size in bits for I2C_SLTH_SSLT. */
1625
1626 /*! @brief Read current value of the I2C_SLTH_SSLT field. */
1627 #define BR_I2C_SLTH_SSLT(x)  (HW_I2C_SLTH(x).U)
1628
1629 /*! @brief Format value for bitfield I2C_SLTH_SSLT. */
1630 #define BF_I2C_SLTH_SSLT(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SLTH_SSLT) & BM_I2C_SLTH_SSLT)
1631
1632 /*! @brief Set the SSLT field to a new value. */
1633 #define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
1634 /*@}*/
1635
1636 /*******************************************************************************
1637  * HW_I2C_SLTL - I2C SCL Low Timeout Register Low
1638  ******************************************************************************/
1639
1640 /*!
1641  * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
1642  *
1643  * Reset value: 0x00U
1644  */
1645 typedef union _hw_i2c_sltl
1646 {
1647     uint8_t U;
1648     struct _hw_i2c_sltl_bitfields
1649     {
1650         uint8_t SSLT : 8;              /*!< [7:0]  */
1651     } B;
1652 } hw_i2c_sltl_t;
1653
1654 /*!
1655  * @name Constants and macros for entire I2C_SLTL register
1656  */
1657 /*@{*/
1658 #define HW_I2C_SLTL_ADDR(x)      ((x) + 0xBU)
1659
1660 #define HW_I2C_SLTL(x)           (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
1661 #define HW_I2C_SLTL_RD(x)        (HW_I2C_SLTL(x).U)
1662 #define HW_I2C_SLTL_WR(x, v)     (HW_I2C_SLTL(x).U = (v))
1663 #define HW_I2C_SLTL_SET(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) |  (v)))
1664 #define HW_I2C_SLTL_CLR(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
1665 #define HW_I2C_SLTL_TOG(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^  (v)))
1666 /*@}*/
1667
1668 /*
1669  * Constants & macros for individual I2C_SLTL bitfields
1670  */
1671
1672 /*!
1673  * @name Register I2C_SLTL, field SSLT[7:0] (RW)
1674  *
1675  * Least significant byte of SCL low timeout value that determines the timeout
1676  * period of SCL low.
1677  */
1678 /*@{*/
1679 #define BP_I2C_SLTL_SSLT     (0U)          /*!< Bit position for I2C_SLTL_SSLT. */
1680 #define BM_I2C_SLTL_SSLT     (0xFFU)       /*!< Bit mask for I2C_SLTL_SSLT. */
1681 #define BS_I2C_SLTL_SSLT     (8U)          /*!< Bit field size in bits for I2C_SLTL_SSLT. */
1682
1683 /*! @brief Read current value of the I2C_SLTL_SSLT field. */
1684 #define BR_I2C_SLTL_SSLT(x)  (HW_I2C_SLTL(x).U)
1685
1686 /*! @brief Format value for bitfield I2C_SLTL_SSLT. */
1687 #define BF_I2C_SLTL_SSLT(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SLTL_SSLT) & BM_I2C_SLTL_SSLT)
1688
1689 /*! @brief Set the SSLT field to a new value. */
1690 #define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
1691 /*@}*/
1692
1693 /*******************************************************************************
1694  * hw_i2c_t - module struct
1695  ******************************************************************************/
1696 /*!
1697  * @brief All I2C module registers.
1698  */
1699 #pragma pack(1)
1700 typedef struct _hw_i2c
1701 {
1702     __IO hw_i2c_a1_t A1;                   /*!< [0x0] I2C Address Register 1 */
1703     __IO hw_i2c_f_t F;                     /*!< [0x1] I2C Frequency Divider register */
1704     __IO hw_i2c_c1_t C1;                   /*!< [0x2] I2C Control Register 1 */
1705     __IO hw_i2c_s_t S;                     /*!< [0x3] I2C Status register */
1706     __IO hw_i2c_d_t D;                     /*!< [0x4] I2C Data I/O register */
1707     __IO hw_i2c_c2_t C2;                   /*!< [0x5] I2C Control Register 2 */
1708     __IO hw_i2c_flt_t FLT;                 /*!< [0x6] I2C Programmable Input Glitch Filter register */
1709     __IO hw_i2c_ra_t RA;                   /*!< [0x7] I2C Range Address register */
1710     __IO hw_i2c_smb_t SMB;                 /*!< [0x8] I2C SMBus Control and Status register */
1711     __IO hw_i2c_a2_t A2;                   /*!< [0x9] I2C Address Register 2 */
1712     __IO hw_i2c_slth_t SLTH;               /*!< [0xA] I2C SCL Low Timeout Register High */
1713     __IO hw_i2c_sltl_t SLTL;               /*!< [0xB] I2C SCL Low Timeout Register Low */
1714 } hw_i2c_t;
1715 #pragma pack()
1716
1717 /*! @brief Macro to access all I2C registers. */
1718 /*! @param x I2C module instance base address. */
1719 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1720  *     use the '&' operator, like <code>&HW_I2C(I2C0_BASE)</code>. */
1721 #define HW_I2C(x)      (*(hw_i2c_t *)(x))
1722
1723 #endif /* __HW_I2C_REGISTERS_H__ */
1724 /* EOF */