tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_RCM_REGISTERS_H__
  78 #define __HW_RCM_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 RCM
  85  *
  86  * Reset Control Module
  87  *
  88  * Registers defined in this header file:
  89  * - HW_RCM_SRS0 - System Reset Status Register 0
  90  * - HW_RCM_SRS1 - System Reset Status Register 1
  91  * - HW_RCM_RPFC - Reset Pin Filter Control register
  92  * - HW_RCM_RPFW - Reset Pin Filter Width register
  93  * - HW_RCM_MR - Mode Register
  94  * - HW_RCM_SSRS0 - Sticky System Reset Status Register 0
  95  * - HW_RCM_SSRS1 - Sticky System Reset Status Register 1
  96  *
  97  * - hw_rcm_t - Struct containing all module registers.
  98  */
  99
 100 #define HW_RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
 101
 102 /*******************************************************************************
 103  * HW_RCM_SRS0 - System Reset Status Register 0
 104  ******************************************************************************/
 105
 106 /*!
 107  * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
 108  *
 109  * Reset value: 0x82U
 110  *
 111  * This register includes read-only status flags to indicate the source of the
 112  * most recent reset. The reset state of these bits depends on what caused the MCU
 113  * to reset. The reset value of this register depends on the reset source: POR
 114  * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
 115  * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
 116  * reset - a bit is set if its corresponding reset source caused the reset
 117  */
 118 typedef union _hw_rcm_srs0
 119 {
 120     uint8_t U;
 121     struct _hw_rcm_srs0_bitfields
 122     {
 123         uint8_t WAKEUP : 1;            /*!< [0] Low Leakage Wakeup Reset */
 124         uint8_t LVD : 1;               /*!< [1] Low-Voltage Detect Reset */
 125         uint8_t LOC : 1;               /*!< [2] Loss-of-Clock Reset */
 126         uint8_t LOL : 1;               /*!< [3] Loss-of-Lock Reset */
 127         uint8_t RESERVED0 : 1;         /*!< [4]  */
 128         uint8_t WDOGb : 1;             /*!< [5] Watchdog */
 129         uint8_t PIN : 1;               /*!< [6] External Reset Pin */
 130         uint8_t POR : 1;               /*!< [7] Power-On Reset */
 131     } B;
 132 } hw_rcm_srs0_t;
 133
 134 /*!
 135  * @name Constants and macros for entire RCM_SRS0 register
 136  */
 137 /*@{*/
 138 #define HW_RCM_SRS0_ADDR(x)      ((x) + 0x0U)
 139
 140 #define HW_RCM_SRS0(x)           (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR(x))
 141 #define HW_RCM_SRS0_RD(x)        (HW_RCM_SRS0(x).U)
 142 /*@}*/
 143
 144 /*
 145  * Constants & macros for individual RCM_SRS0 bitfields
 146  */
 147
 148 /*!
 149  * @name Register RCM_SRS0, field WAKEUP[0] (RO)
 150  *
 151  * Indicates a reset has been caused by an enabled LLWU module wakeup source
 152  * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
 153  * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
 154  * mode causes a reset. This bit is cleared by any reset except WAKEUP.
 155  *
 156  * Values:
 157  * - 0 - Reset not caused by LLWU module wakeup source
 158  * - 1 - Reset caused by LLWU module wakeup source
 159  */
 160 /*@{*/
 161 #define BP_RCM_SRS0_WAKEUP   (0U)          /*!< Bit position for RCM_SRS0_WAKEUP. */
 162 #define BM_RCM_SRS0_WAKEUP   (0x01U)       /*!< Bit mask for RCM_SRS0_WAKEUP. */
 163 #define BS_RCM_SRS0_WAKEUP   (1U)          /*!< Bit field size in bits for RCM_SRS0_WAKEUP. */
 164
 165 /*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
 166 #define BR_RCM_SRS0_WAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WAKEUP))
 167 /*@}*/
 168
 169 /*!
 170  * @name Register RCM_SRS0, field LVD[1] (RO)
 171  *
 172  * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
 173  * an LVD reset occurs. This field is also set by POR.
 174  *
 175  * Values:
 176  * - 0 - Reset not caused by LVD trip or POR
 177  * - 1 - Reset caused by LVD trip or POR
 178  */
 179 /*@{*/
 180 #define BP_RCM_SRS0_LVD      (1U)          /*!< Bit position for RCM_SRS0_LVD. */
 181 #define BM_RCM_SRS0_LVD      (0x02U)       /*!< Bit mask for RCM_SRS0_LVD. */
 182 #define BS_RCM_SRS0_LVD      (1U)          /*!< Bit field size in bits for RCM_SRS0_LVD. */
 183
 184 /*! @brief Read current value of the RCM_SRS0_LVD field. */
 185 #define BR_RCM_SRS0_LVD(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LVD))
 186 /*@}*/
 187
 188 /*!
 189  * @name Register RCM_SRS0, field LOC[2] (RO)
 190  *
 191  * Indicates a reset has been caused by a loss of external clock. The MCG clock
 192  * monitor must be enabled for a loss of clock to be detected. Refer to the
 193  * detailed MCG description for information on enabling the clock monitor.
 194  *
 195  * Values:
 196  * - 0 - Reset not caused by a loss of external clock.
 197  * - 1 - Reset caused by a loss of external clock.
 198  */
 199 /*@{*/
 200 #define BP_RCM_SRS0_LOC      (2U)          /*!< Bit position for RCM_SRS0_LOC. */
 201 #define BM_RCM_SRS0_LOC      (0x04U)       /*!< Bit mask for RCM_SRS0_LOC. */
 202 #define BS_RCM_SRS0_LOC      (1U)          /*!< Bit field size in bits for RCM_SRS0_LOC. */
 203
 204 /*! @brief Read current value of the RCM_SRS0_LOC field. */
 205 #define BR_RCM_SRS0_LOC(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC))
 206 /*@}*/
 207
 208 /*!
 209  * @name Register RCM_SRS0, field LOL[3] (RO)
 210  *
 211  * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
 212  * MCG description for information on the loss-of-clock event.
 213  *
 214  * Values:
 215  * - 0 - Reset not caused by a loss of lock in the PLL
 216  * - 1 - Reset caused by a loss of lock in the PLL
 217  */
 218 /*@{*/
 219 #define BP_RCM_SRS0_LOL      (3U)          /*!< Bit position for RCM_SRS0_LOL. */
 220 #define BM_RCM_SRS0_LOL      (0x08U)       /*!< Bit mask for RCM_SRS0_LOL. */
 221 #define BS_RCM_SRS0_LOL      (1U)          /*!< Bit field size in bits for RCM_SRS0_LOL. */
 222
 223 /*! @brief Read current value of the RCM_SRS0_LOL field. */
 224 #define BR_RCM_SRS0_LOL(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL))
 225 /*@}*/
 226
 227 /*!
 228  * @name Register RCM_SRS0, field WDOG[5] (RO)
 229  *
 230  * Indicates a reset has been caused by the watchdog timer timing out. This
 231  * reset source can be blocked by disabling the watchdog.
 232  *
 233  * Values:
 234  * - 0 - Reset not caused by watchdog timeout
 235  * - 1 - Reset caused by watchdog timeout
 236  */
 237 /*@{*/
 238 #define BP_RCM_SRS0_WDOG     (5U)          /*!< Bit position for RCM_SRS0_WDOG. */
 239 #define BM_RCM_SRS0_WDOG     (0x20U)       /*!< Bit mask for RCM_SRS0_WDOG. */
 240 #define BS_RCM_SRS0_WDOG     (1U)          /*!< Bit field size in bits for RCM_SRS0_WDOG. */
 241
 242 /*! @brief Read current value of the RCM_SRS0_WDOG field. */
 243 #define BR_RCM_SRS0_WDOG(x)  (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WDOG))
 244 /*@}*/
 245
 246 /*!
 247  * @name Register RCM_SRS0, field PIN[6] (RO)
 248  *
 249  * Indicates a reset has been caused by an active-low level on the external
 250  * RESET pin.
 251  *
 252  * Values:
 253  * - 0 - Reset not caused by external reset pin
 254  * - 1 - Reset caused by external reset pin
 255  */
 256 /*@{*/
 257 #define BP_RCM_SRS0_PIN      (6U)          /*!< Bit position for RCM_SRS0_PIN. */
 258 #define BM_RCM_SRS0_PIN      (0x40U)       /*!< Bit mask for RCM_SRS0_PIN. */
 259 #define BS_RCM_SRS0_PIN      (1U)          /*!< Bit field size in bits for RCM_SRS0_PIN. */
 260
 261 /*! @brief Read current value of the RCM_SRS0_PIN field. */
 262 #define BR_RCM_SRS0_PIN(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_PIN))
 263 /*@}*/
 264
 265 /*!
 266  * @name Register RCM_SRS0, field POR[7] (RO)
 267  *
 268  * Indicates a reset has been caused by the power-on detection logic. Because
 269  * the internal supply voltage was ramping up at the time, the low-voltage reset
 270  * (LVD) status bit is also set to indicate that the reset occurred while the
 271  * internal supply was below the LVD threshold.
 272  *
 273  * Values:
 274  * - 0 - Reset not caused by POR
 275  * - 1 - Reset caused by POR
 276  */
 277 /*@{*/
 278 #define BP_RCM_SRS0_POR      (7U)          /*!< Bit position for RCM_SRS0_POR. */
 279 #define BM_RCM_SRS0_POR      (0x80U)       /*!< Bit mask for RCM_SRS0_POR. */
 280 #define BS_RCM_SRS0_POR      (1U)          /*!< Bit field size in bits for RCM_SRS0_POR. */
 281
 282 /*! @brief Read current value of the RCM_SRS0_POR field. */
 283 #define BR_RCM_SRS0_POR(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_POR))
 284 /*@}*/
 285
 286 /*******************************************************************************
 287  * HW_RCM_SRS1 - System Reset Status Register 1
 288  ******************************************************************************/
 289
 290 /*!
 291  * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
 292  *
 293  * Reset value: 0x00U
 294  *
 295  * This register includes read-only status flags to indicate the source of the
 296  * most recent reset. The reset state of these bits depends on what caused the MCU
 297  * to reset. The reset value of this register depends on the reset source: POR
 298  * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
 299  * reset - a bit is set if its corresponding reset source caused the reset
 300  */
 301 typedef union _hw_rcm_srs1
 302 {
 303     uint8_t U;
 304     struct _hw_rcm_srs1_bitfields
 305     {
 306         uint8_t JTAG : 1;              /*!< [0] JTAG Generated Reset */
 307         uint8_t LOCKUP : 1;            /*!< [1] Core Lockup */
 308         uint8_t SW : 1;                /*!< [2] Software */
 309         uint8_t MDM_AP : 1;            /*!< [3] MDM-AP System Reset Request */
 310         uint8_t EZPT : 1;              /*!< [4] EzPort Reset */
 311         uint8_t SACKERR : 1;           /*!< [5] Stop Mode Acknowledge Error Reset */
 312         uint8_t RESERVED0 : 2;         /*!< [7:6]  */
 313     } B;
 314 } hw_rcm_srs1_t;
 315
 316 /*!
 317  * @name Constants and macros for entire RCM_SRS1 register
 318  */
 319 /*@{*/
 320 #define HW_RCM_SRS1_ADDR(x)      ((x) + 0x1U)
 321
 322 #define HW_RCM_SRS1(x)           (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR(x))
 323 #define HW_RCM_SRS1_RD(x)        (HW_RCM_SRS1(x).U)
 324 /*@}*/
 325
 326 /*
 327  * Constants & macros for individual RCM_SRS1 bitfields
 328  */
 329
 330 /*!
 331  * @name Register RCM_SRS1, field JTAG[0] (RO)
 332  *
 333  * Indicates a reset has been caused by JTAG selection of certain IR codes:
 334  * EZPORT, EXTEST, HIGHZ, and CLAMP.
 335  *
 336  * Values:
 337  * - 0 - Reset not caused by JTAG
 338  * - 1 - Reset caused by JTAG
 339  */
 340 /*@{*/
 341 #define BP_RCM_SRS1_JTAG     (0U)          /*!< Bit position for RCM_SRS1_JTAG. */
 342 #define BM_RCM_SRS1_JTAG     (0x01U)       /*!< Bit mask for RCM_SRS1_JTAG. */
 343 #define BS_RCM_SRS1_JTAG     (1U)          /*!< Bit field size in bits for RCM_SRS1_JTAG. */
 344
 345 /*! @brief Read current value of the RCM_SRS1_JTAG field. */
 346 #define BR_RCM_SRS1_JTAG(x)  (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_JTAG))
 347 /*@}*/
 348
 349 /*!
 350  * @name Register RCM_SRS1, field LOCKUP[1] (RO)
 351  *
 352  * Indicates a reset has been caused by the ARM core indication of a LOCKUP
 353  * event.
 354  *
 355  * Values:
 356  * - 0 - Reset not caused by core LOCKUP event
 357  * - 1 - Reset caused by core LOCKUP event
 358  */
 359 /*@{*/
 360 #define BP_RCM_SRS1_LOCKUP   (1U)          /*!< Bit position for RCM_SRS1_LOCKUP. */
 361 #define BM_RCM_SRS1_LOCKUP   (0x02U)       /*!< Bit mask for RCM_SRS1_LOCKUP. */
 362 #define BS_RCM_SRS1_LOCKUP   (1U)          /*!< Bit field size in bits for RCM_SRS1_LOCKUP. */
 363
 364 /*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
 365 #define BR_RCM_SRS1_LOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_LOCKUP))
 366 /*@}*/
 367
 368 /*!
 369  * @name Register RCM_SRS1, field SW[2] (RO)
 370  *
 371  * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
 372  * Application Interrupt and Reset Control Register in the ARM core.
 373  *
 374  * Values:
 375  * - 0 - Reset not caused by software setting of SYSRESETREQ bit
 376  * - 1 - Reset caused by software setting of SYSRESETREQ bit
 377  */
 378 /*@{*/
 379 #define BP_RCM_SRS1_SW       (2U)          /*!< Bit position for RCM_SRS1_SW. */
 380 #define BM_RCM_SRS1_SW       (0x04U)       /*!< Bit mask for RCM_SRS1_SW. */
 381 #define BS_RCM_SRS1_SW       (1U)          /*!< Bit field size in bits for RCM_SRS1_SW. */
 382
 383 /*! @brief Read current value of the RCM_SRS1_SW field. */
 384 #define BR_RCM_SRS1_SW(x)    (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SW))
 385 /*@}*/
 386
 387 /*!
 388  * @name Register RCM_SRS1, field MDM_AP[3] (RO)
 389  *
 390  * Indicates a reset has been caused by the host debugger system setting of the
 391  * System Reset Request bit in the MDM-AP Control Register.
 392  *
 393  * Values:
 394  * - 0 - Reset not caused by host debugger system setting of the System Reset
 395  *     Request bit
 396  * - 1 - Reset caused by host debugger system setting of the System Reset
 397  *     Request bit
 398  */
 399 /*@{*/
 400 #define BP_RCM_SRS1_MDM_AP   (3U)          /*!< Bit position for RCM_SRS1_MDM_AP. */
 401 #define BM_RCM_SRS1_MDM_AP   (0x08U)       /*!< Bit mask for RCM_SRS1_MDM_AP. */
 402 #define BS_RCM_SRS1_MDM_AP   (1U)          /*!< Bit field size in bits for RCM_SRS1_MDM_AP. */
 403
 404 /*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
 405 #define BR_RCM_SRS1_MDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_MDM_AP))
 406 /*@}*/
 407
 408 /*!
 409  * @name Register RCM_SRS1, field EZPT[4] (RO)
 410  *
 411  * Indicates a reset has been caused by EzPort receiving the RESET command while
 412  * the device is in EzPort mode.
 413  *
 414  * Values:
 415  * - 0 - Reset not caused by EzPort receiving the RESET command while the device
 416  *     is in EzPort mode
 417  * - 1 - Reset caused by EzPort receiving the RESET command while the device is
 418  *     in EzPort mode
 419  */
 420 /*@{*/
 421 #define BP_RCM_SRS1_EZPT     (4U)          /*!< Bit position for RCM_SRS1_EZPT. */
 422 #define BM_RCM_SRS1_EZPT     (0x10U)       /*!< Bit mask for RCM_SRS1_EZPT. */
 423 #define BS_RCM_SRS1_EZPT     (1U)          /*!< Bit field size in bits for RCM_SRS1_EZPT. */
 424
 425 /*! @brief Read current value of the RCM_SRS1_EZPT field. */
 426 #define BR_RCM_SRS1_EZPT(x)  (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_EZPT))
 427 /*@}*/
 428
 429 /*!
 430  * @name Register RCM_SRS1, field SACKERR[5] (RO)
 431  *
 432  * Indicates that after an attempt to enter Stop mode, a reset has been caused
 433  * by a failure of one or more peripherals to acknowledge within approximately one
 434  * second to enter stop mode.
 435  *
 436  * Values:
 437  * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
 438  *     stop mode
 439  * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
 440  *     mode
 441  */
 442 /*@{*/
 443 #define BP_RCM_SRS1_SACKERR  (5U)          /*!< Bit position for RCM_SRS1_SACKERR. */
 444 #define BM_RCM_SRS1_SACKERR  (0x20U)       /*!< Bit mask for RCM_SRS1_SACKERR. */
 445 #define BS_RCM_SRS1_SACKERR  (1U)          /*!< Bit field size in bits for RCM_SRS1_SACKERR. */
 446
 447 /*! @brief Read current value of the RCM_SRS1_SACKERR field. */
 448 #define BR_RCM_SRS1_SACKERR(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SACKERR))
 449 /*@}*/
 450
 451 /*******************************************************************************
 452  * HW_RCM_RPFC - Reset Pin Filter Control register
 453  ******************************************************************************/
 454
 455 /*!
 456  * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
 457  *
 458  * Reset value: 0x00U
 459  *
 460  * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
 461  * other reset types. The bus clock filter is reset when disabled or when entering
 462  * stop mode. The LPO filter is reset when disabled .
 463  */
 464 typedef union _hw_rcm_rpfc
 465 {
 466     uint8_t U;
 467     struct _hw_rcm_rpfc_bitfields
 468     {
 469         uint8_t RSTFLTSRW : 2;         /*!< [1:0] Reset Pin Filter Select in Run and
 470                                         * Wait Modes */
 471         uint8_t RSTFLTSS : 1;          /*!< [2] Reset Pin Filter Select in Stop Mode */
 472         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
 473     } B;
 474 } hw_rcm_rpfc_t;
 475
 476 /*!
 477  * @name Constants and macros for entire RCM_RPFC register
 478  */
 479 /*@{*/
 480 #define HW_RCM_RPFC_ADDR(x)      ((x) + 0x4U)
 481
 482 #define HW_RCM_RPFC(x)           (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR(x))
 483 #define HW_RCM_RPFC_RD(x)        (HW_RCM_RPFC(x).U)
 484 #define HW_RCM_RPFC_WR(x, v)     (HW_RCM_RPFC(x).U = (v))
 485 #define HW_RCM_RPFC_SET(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) |  (v)))
 486 #define HW_RCM_RPFC_CLR(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) & ~(v)))
 487 #define HW_RCM_RPFC_TOG(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) ^  (v)))
 488 /*@}*/
 489
 490 /*
 491  * Constants & macros for individual RCM_RPFC bitfields
 492  */
 493
 494 /*!
 495  * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
 496  *
 497  * Selects how the reset pin filter is enabled in run and wait modes.
 498  *
 499  * Values:
 500  * - 00 - All filtering disabled
 501  * - 01 - Bus clock filter enabled for normal operation
 502  * - 10 - LPO clock filter enabled for normal operation
 503  * - 11 - Reserved
 504  */
 505 /*@{*/
 506 #define BP_RCM_RPFC_RSTFLTSRW (0U)         /*!< Bit position for RCM_RPFC_RSTFLTSRW. */
 507 #define BM_RCM_RPFC_RSTFLTSRW (0x03U)      /*!< Bit mask for RCM_RPFC_RSTFLTSRW. */
 508 #define BS_RCM_RPFC_RSTFLTSRW (2U)         /*!< Bit field size in bits for RCM_RPFC_RSTFLTSRW. */
 509
 510 /*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
 511 #define BR_RCM_RPFC_RSTFLTSRW(x) (HW_RCM_RPFC(x).B.RSTFLTSRW)
 512
 513 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW. */
 514 #define BF_RCM_RPFC_RSTFLTSRW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSRW) & BM_RCM_RPFC_RSTFLTSRW)
 515
 516 /*! @brief Set the RSTFLTSRW field to a new value. */
 517 #define BW_RCM_RPFC_RSTFLTSRW(x, v) (HW_RCM_RPFC_WR(x, (HW_RCM_RPFC_RD(x) & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
 518 /*@}*/
 519
 520 /*!
 521  * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
 522  *
 523  * Selects how the reset pin filter is enabled in Stop and VLPS modes , and also
 524  * during LLS and VLLS modes. On exit from VLLS mode, this bit should be
 525  * reconfigured before clearing PMC_REGSC[ACKISO].
 526  *
 527  * Values:
 528  * - 0 - All filtering disabled
 529  * - 1 - LPO clock filter enabled
 530  */
 531 /*@{*/
 532 #define BP_RCM_RPFC_RSTFLTSS (2U)          /*!< Bit position for RCM_RPFC_RSTFLTSS. */
 533 #define BM_RCM_RPFC_RSTFLTSS (0x04U)       /*!< Bit mask for RCM_RPFC_RSTFLTSS. */
 534 #define BS_RCM_RPFC_RSTFLTSS (1U)          /*!< Bit field size in bits for RCM_RPFC_RSTFLTSS. */
 535
 536 /*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
 537 #define BR_RCM_RPFC_RSTFLTSS(x) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS))
 538
 539 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSS. */
 540 #define BF_RCM_RPFC_RSTFLTSS(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSS) & BM_RCM_RPFC_RSTFLTSS)
 541
 542 /*! @brief Set the RSTFLTSS field to a new value. */
 543 #define BW_RCM_RPFC_RSTFLTSS(x, v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS) = (v))
 544 /*@}*/
 545
 546 /*******************************************************************************
 547  * HW_RCM_RPFW - Reset Pin Filter Width register
 548  ******************************************************************************/
 549
 550 /*!
 551  * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
 552  *
 553  * Reset value: 0x00U
 554  *
 555  * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
 556  * They are unaffected by other reset types.
 557  */
 558 typedef union _hw_rcm_rpfw
 559 {
 560     uint8_t U;
 561     struct _hw_rcm_rpfw_bitfields
 562     {
 563         uint8_t RSTFLTSEL : 5;         /*!< [4:0] Reset Pin Filter Bus Clock Select */
 564         uint8_t RESERVED0 : 3;         /*!< [7:5]  */
 565     } B;
 566 } hw_rcm_rpfw_t;
 567
 568 /*!
 569  * @name Constants and macros for entire RCM_RPFW register
 570  */
 571 /*@{*/
 572 #define HW_RCM_RPFW_ADDR(x)      ((x) + 0x5U)
 573
 574 #define HW_RCM_RPFW(x)           (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR(x))
 575 #define HW_RCM_RPFW_RD(x)        (HW_RCM_RPFW(x).U)
 576 #define HW_RCM_RPFW_WR(x, v)     (HW_RCM_RPFW(x).U = (v))
 577 #define HW_RCM_RPFW_SET(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) |  (v)))
 578 #define HW_RCM_RPFW_CLR(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) & ~(v)))
 579 #define HW_RCM_RPFW_TOG(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) ^  (v)))
 580 /*@}*/
 581
 582 /*
 583  * Constants & macros for individual RCM_RPFW bitfields
 584  */
 585
 586 /*!
 587  * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
 588  *
 589  * Selects the reset pin bus clock filter width.
 590  *
 591  * Values:
 592  * - 00000 - Bus clock filter count is 1
 593  * - 00001 - Bus clock filter count is 2
 594  * - 00010 - Bus clock filter count is 3
 595  * - 00011 - Bus clock filter count is 4
 596  * - 00100 - Bus clock filter count is 5
 597  * - 00101 - Bus clock filter count is 6
 598  * - 00110 - Bus clock filter count is 7
 599  * - 00111 - Bus clock filter count is 8
 600  * - 01000 - Bus clock filter count is 9
 601  * - 01001 - Bus clock filter count is 10
 602  * - 01010 - Bus clock filter count is 11
 603  * - 01011 - Bus clock filter count is 12
 604  * - 01100 - Bus clock filter count is 13
 605  * - 01101 - Bus clock filter count is 14
 606  * - 01110 - Bus clock filter count is 15
 607  * - 01111 - Bus clock filter count is 16
 608  * - 10000 - Bus clock filter count is 17
 609  * - 10001 - Bus clock filter count is 18
 610  * - 10010 - Bus clock filter count is 19
 611  * - 10011 - Bus clock filter count is 20
 612  * - 10100 - Bus clock filter count is 21
 613  * - 10101 - Bus clock filter count is 22
 614  * - 10110 - Bus clock filter count is 23
 615  * - 10111 - Bus clock filter count is 24
 616  * - 11000 - Bus clock filter count is 25
 617  * - 11001 - Bus clock filter count is 26
 618  * - 11010 - Bus clock filter count is 27
 619  * - 11011 - Bus clock filter count is 28
 620  * - 11100 - Bus clock filter count is 29
 621  * - 11101 - Bus clock filter count is 30
 622  * - 11110 - Bus clock filter count is 31
 623  * - 11111 - Bus clock filter count is 32
 624  */
 625 /*@{*/
 626 #define BP_RCM_RPFW_RSTFLTSEL (0U)         /*!< Bit position for RCM_RPFW_RSTFLTSEL. */
 627 #define BM_RCM_RPFW_RSTFLTSEL (0x1FU)      /*!< Bit mask for RCM_RPFW_RSTFLTSEL. */
 628 #define BS_RCM_RPFW_RSTFLTSEL (5U)         /*!< Bit field size in bits for RCM_RPFW_RSTFLTSEL. */
 629
 630 /*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
 631 #define BR_RCM_RPFW_RSTFLTSEL(x) (HW_RCM_RPFW(x).B.RSTFLTSEL)
 632
 633 /*! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL. */
 634 #define BF_RCM_RPFW_RSTFLTSEL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFW_RSTFLTSEL) & BM_RCM_RPFW_RSTFLTSEL)
 635
 636 /*! @brief Set the RSTFLTSEL field to a new value. */
 637 #define BW_RCM_RPFW_RSTFLTSEL(x, v) (HW_RCM_RPFW_WR(x, (HW_RCM_RPFW_RD(x) & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
 638 /*@}*/
 639
 640 /*******************************************************************************
 641  * HW_RCM_MR - Mode Register
 642  ******************************************************************************/
 643
 644 /*!
 645  * @brief HW_RCM_MR - Mode Register (RO)
 646  *
 647  * Reset value: 0x00U
 648  *
 649  * This register includes read-only status flags to indicate the state of the
 650  * mode pins during the last Chip Reset.
 651  */
 652 typedef union _hw_rcm_mr
 653 {
 654     uint8_t U;
 655     struct _hw_rcm_mr_bitfields
 656     {
 657         uint8_t RESERVED0 : 1;         /*!< [0]  */
 658         uint8_t EZP_MS : 1;            /*!< [1] EZP_MS_B pin state */
 659         uint8_t RESERVED1 : 6;         /*!< [7:2]  */
 660     } B;
 661 } hw_rcm_mr_t;
 662
 663 /*!
 664  * @name Constants and macros for entire RCM_MR register
 665  */
 666 /*@{*/
 667 #define HW_RCM_MR_ADDR(x)        ((x) + 0x7U)
 668
 669 #define HW_RCM_MR(x)             (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR(x))
 670 #define HW_RCM_MR_RD(x)          (HW_RCM_MR(x).U)
 671 /*@}*/
 672
 673 /*
 674  * Constants & macros for individual RCM_MR bitfields
 675  */
 676
 677 /*!
 678  * @name Register RCM_MR, field EZP_MS[1] (RO)
 679  *
 680  * Reflects the state of the EZP_MS pin during the last Chip Reset
 681  *
 682  * Values:
 683  * - 0 - Pin deasserted (logic 1)
 684  * - 1 - Pin asserted (logic 0)
 685  */
 686 /*@{*/
 687 #define BP_RCM_MR_EZP_MS     (1U)          /*!< Bit position for RCM_MR_EZP_MS. */
 688 #define BM_RCM_MR_EZP_MS     (0x02U)       /*!< Bit mask for RCM_MR_EZP_MS. */
 689 #define BS_RCM_MR_EZP_MS     (1U)          /*!< Bit field size in bits for RCM_MR_EZP_MS. */
 690
 691 /*! @brief Read current value of the RCM_MR_EZP_MS field. */
 692 #define BR_RCM_MR_EZP_MS(x)  (BITBAND_ACCESS8(HW_RCM_MR_ADDR(x), BP_RCM_MR_EZP_MS))
 693 /*@}*/
 694
 695 /*******************************************************************************
 696  * HW_RCM_SSRS0 - Sticky System Reset Status Register 0
 697  ******************************************************************************/
 698
 699 /*!
 700  * @brief HW_RCM_SSRS0 - Sticky System Reset Status Register 0 (RW)
 701  *
 702  * Reset value: 0x82U
 703  *
 704  * This register includes status flags to indicate all reset sources since the
 705  * last POR, LVD or VLLS Wakeup that have not been cleared by software. Software
 706  * can clear the status flags by writing a logic one to a flag.
 707  */
 708 typedef union _hw_rcm_ssrs0
 709 {
 710     uint8_t U;
 711     struct _hw_rcm_ssrs0_bitfields
 712     {
 713         uint8_t SWAKEUP : 1;           /*!< [0] Sticky Low Leakage Wakeup Reset */
 714         uint8_t SLVD : 1;              /*!< [1] Sticky Low-Voltage Detect Reset */
 715         uint8_t SLOC : 1;              /*!< [2] Sticky Loss-of-Clock Reset */
 716         uint8_t SLOL : 1;              /*!< [3] Sticky Loss-of-Lock Reset */
 717         uint8_t RESERVED0 : 1;         /*!< [4]  */
 718         uint8_t SWDOG : 1;             /*!< [5] Sticky Watchdog */
 719         uint8_t SPIN : 1;              /*!< [6] Sticky External Reset Pin */
 720         uint8_t SPOR : 1;              /*!< [7] Sticky Power-On Reset */
 721     } B;
 722 } hw_rcm_ssrs0_t;
 723
 724 /*!
 725  * @name Constants and macros for entire RCM_SSRS0 register
 726  */
 727 /*@{*/
 728 #define HW_RCM_SSRS0_ADDR(x)     ((x) + 0x8U)
 729
 730 #define HW_RCM_SSRS0(x)          (*(__IO hw_rcm_ssrs0_t *) HW_RCM_SSRS0_ADDR(x))
 731 #define HW_RCM_SSRS0_RD(x)       (HW_RCM_SSRS0(x).U)
 732 #define HW_RCM_SSRS0_WR(x, v)    (HW_RCM_SSRS0(x).U = (v))
 733 #define HW_RCM_SSRS0_SET(x, v)   (HW_RCM_SSRS0_WR(x, HW_RCM_SSRS0_RD(x) |  (v)))
 734 #define HW_RCM_SSRS0_CLR(x, v)   (HW_RCM_SSRS0_WR(x, HW_RCM_SSRS0_RD(x) & ~(v)))
 735 #define HW_RCM_SSRS0_TOG(x, v)   (HW_RCM_SSRS0_WR(x, HW_RCM_SSRS0_RD(x) ^  (v)))
 736 /*@}*/
 737
 738 /*
 739  * Constants & macros for individual RCM_SSRS0 bitfields
 740  */
 741
 742 /*!
 743  * @name Register RCM_SSRS0, field SWAKEUP[0] (W1C)
 744  *
 745  * Indicates a reset has been caused by an enabled LLWU modulewakeup source
 746  * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
 747  * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
 748  * mode causes a reset.
 749  *
 750  * Values:
 751  * - 0 - Reset not caused by LLWU module wakeup source
 752  * - 1 - Reset caused by LLWU module wakeup source
 753  */
 754 /*@{*/
 755 #define BP_RCM_SSRS0_SWAKEUP (0U)          /*!< Bit position for RCM_SSRS0_SWAKEUP. */
 756 #define BM_RCM_SSRS0_SWAKEUP (0x01U)       /*!< Bit mask for RCM_SSRS0_SWAKEUP. */
 757 #define BS_RCM_SSRS0_SWAKEUP (1U)          /*!< Bit field size in bits for RCM_SSRS0_SWAKEUP. */
 758
 759 /*! @brief Read current value of the RCM_SSRS0_SWAKEUP field. */
 760 #define BR_RCM_SSRS0_SWAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWAKEUP))
 761
 762 /*! @brief Format value for bitfield RCM_SSRS0_SWAKEUP. */
 763 #define BF_RCM_SSRS0_SWAKEUP(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SWAKEUP) & BM_RCM_SSRS0_SWAKEUP)
 764
 765 /*! @brief Set the SWAKEUP field to a new value. */
 766 #define BW_RCM_SSRS0_SWAKEUP(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWAKEUP) = (v))
 767 /*@}*/
 768
 769 /*!
 770  * @name Register RCM_SSRS0, field SLVD[1] (W1C)
 771  *
 772  * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
 773  * an LVD reset occurs. This field is also set by POR.
 774  *
 775  * Values:
 776  * - 0 - Reset not caused by LVD trip or POR
 777  * - 1 - Reset caused by LVD trip or POR
 778  */
 779 /*@{*/
 780 #define BP_RCM_SSRS0_SLVD    (1U)          /*!< Bit position for RCM_SSRS0_SLVD. */
 781 #define BM_RCM_SSRS0_SLVD    (0x02U)       /*!< Bit mask for RCM_SSRS0_SLVD. */
 782 #define BS_RCM_SSRS0_SLVD    (1U)          /*!< Bit field size in bits for RCM_SSRS0_SLVD. */
 783
 784 /*! @brief Read current value of the RCM_SSRS0_SLVD field. */
 785 #define BR_RCM_SSRS0_SLVD(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLVD))
 786
 787 /*! @brief Format value for bitfield RCM_SSRS0_SLVD. */
 788 #define BF_RCM_SSRS0_SLVD(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLVD) & BM_RCM_SSRS0_SLVD)
 789
 790 /*! @brief Set the SLVD field to a new value. */
 791 #define BW_RCM_SSRS0_SLVD(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLVD) = (v))
 792 /*@}*/
 793
 794 /*!
 795  * @name Register RCM_SSRS0, field SLOC[2] (W1C)
 796  *
 797  * Indicates a reset has been caused by a loss of external clock. The MCG clock
 798  * monitor must be enabled for a loss of clock to be detected. Refer to the
 799  * detailed MCG description for information on enabling the clock monitor.
 800  *
 801  * Values:
 802  * - 0 - Reset not caused by a loss of external clock.
 803  * - 1 - Reset caused by a loss of external clock.
 804  */
 805 /*@{*/
 806 #define BP_RCM_SSRS0_SLOC    (2U)          /*!< Bit position for RCM_SSRS0_SLOC. */
 807 #define BM_RCM_SSRS0_SLOC    (0x04U)       /*!< Bit mask for RCM_SSRS0_SLOC. */
 808 #define BS_RCM_SSRS0_SLOC    (1U)          /*!< Bit field size in bits for RCM_SSRS0_SLOC. */
 809
 810 /*! @brief Read current value of the RCM_SSRS0_SLOC field. */
 811 #define BR_RCM_SSRS0_SLOC(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC))
 812
 813 /*! @brief Format value for bitfield RCM_SSRS0_SLOC. */
 814 #define BF_RCM_SSRS0_SLOC(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLOC) & BM_RCM_SSRS0_SLOC)
 815
 816 /*! @brief Set the SLOC field to a new value. */
 817 #define BW_RCM_SSRS0_SLOC(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC) = (v))
 818 /*@}*/
 819
 820 /*!
 821  * @name Register RCM_SSRS0, field SLOL[3] (W1C)
 822  *
 823  * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
 824  * MCG description for information on the loss-of-clock event.
 825  *
 826  * Values:
 827  * - 0 - Reset not caused by a loss of lock in the PLL
 828  * - 1 - Reset caused by a loss of lock in the PLL
 829  */
 830 /*@{*/
 831 #define BP_RCM_SSRS0_SLOL    (3U)          /*!< Bit position for RCM_SSRS0_SLOL. */
 832 #define BM_RCM_SSRS0_SLOL    (0x08U)       /*!< Bit mask for RCM_SSRS0_SLOL. */
 833 #define BS_RCM_SSRS0_SLOL    (1U)          /*!< Bit field size in bits for RCM_SSRS0_SLOL. */
 834
 835 /*! @brief Read current value of the RCM_SSRS0_SLOL field. */
 836 #define BR_RCM_SSRS0_SLOL(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL))
 837
 838 /*! @brief Format value for bitfield RCM_SSRS0_SLOL. */
 839 #define BF_RCM_SSRS0_SLOL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLOL) & BM_RCM_SSRS0_SLOL)
 840
 841 /*! @brief Set the SLOL field to a new value. */
 842 #define BW_RCM_SSRS0_SLOL(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL) = (v))
 843 /*@}*/
 844
 845 /*!
 846  * @name Register RCM_SSRS0, field SWDOG[5] (W1C)
 847  *
 848  * Indicates a reset has been caused by the watchdog timer timing out. This
 849  * reset source can be blocked by disabling the watchdog.
 850  *
 851  * Values:
 852  * - 0 - Reset not caused by watchdog timeout
 853  * - 1 - Reset caused by watchdog timeout
 854  */
 855 /*@{*/
 856 #define BP_RCM_SSRS0_SWDOG   (5U)          /*!< Bit position for RCM_SSRS0_SWDOG. */
 857 #define BM_RCM_SSRS0_SWDOG   (0x20U)       /*!< Bit mask for RCM_SSRS0_SWDOG. */
 858 #define BS_RCM_SSRS0_SWDOG   (1U)          /*!< Bit field size in bits for RCM_SSRS0_SWDOG. */
 859
 860 /*! @brief Read current value of the RCM_SSRS0_SWDOG field. */
 861 #define BR_RCM_SSRS0_SWDOG(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWDOG))
 862
 863 /*! @brief Format value for bitfield RCM_SSRS0_SWDOG. */
 864 #define BF_RCM_SSRS0_SWDOG(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SWDOG) & BM_RCM_SSRS0_SWDOG)
 865
 866 /*! @brief Set the SWDOG field to a new value. */
 867 #define BW_RCM_SSRS0_SWDOG(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWDOG) = (v))
 868 /*@}*/
 869
 870 /*!
 871  * @name Register RCM_SSRS0, field SPIN[6] (W1C)
 872  *
 873  * Indicates a reset has been caused by an active-low level on the external
 874  * RESET pin.
 875  *
 876  * Values:
 877  * - 0 - Reset not caused by external reset pin
 878  * - 1 - Reset caused by external reset pin
 879  */
 880 /*@{*/
 881 #define BP_RCM_SSRS0_SPIN    (6U)          /*!< Bit position for RCM_SSRS0_SPIN. */
 882 #define BM_RCM_SSRS0_SPIN    (0x40U)       /*!< Bit mask for RCM_SSRS0_SPIN. */
 883 #define BS_RCM_SSRS0_SPIN    (1U)          /*!< Bit field size in bits for RCM_SSRS0_SPIN. */
 884
 885 /*! @brief Read current value of the RCM_SSRS0_SPIN field. */
 886 #define BR_RCM_SSRS0_SPIN(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPIN))
 887
 888 /*! @brief Format value for bitfield RCM_SSRS0_SPIN. */
 889 #define BF_RCM_SSRS0_SPIN(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SPIN) & BM_RCM_SSRS0_SPIN)
 890
 891 /*! @brief Set the SPIN field to a new value. */
 892 #define BW_RCM_SSRS0_SPIN(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPIN) = (v))
 893 /*@}*/
 894
 895 /*!
 896  * @name Register RCM_SSRS0, field SPOR[7] (W1C)
 897  *
 898  * Indicates a reset has been caused by the power-on detection logic. Because
 899  * the internal supply voltage was ramping up at the time, the low-voltage reset
 900  * (LVD) status bit is also set to indicate that the reset occurred while the
 901  * internal supply was below the LVD threshold.
 902  *
 903  * Values:
 904  * - 0 - Reset not caused by POR
 905  * - 1 - Reset caused by POR
 906  */
 907 /*@{*/
 908 #define BP_RCM_SSRS0_SPOR    (7U)          /*!< Bit position for RCM_SSRS0_SPOR. */
 909 #define BM_RCM_SSRS0_SPOR    (0x80U)       /*!< Bit mask for RCM_SSRS0_SPOR. */
 910 #define BS_RCM_SSRS0_SPOR    (1U)          /*!< Bit field size in bits for RCM_SSRS0_SPOR. */
 911
 912 /*! @brief Read current value of the RCM_SSRS0_SPOR field. */
 913 #define BR_RCM_SSRS0_SPOR(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPOR))
 914
 915 /*! @brief Format value for bitfield RCM_SSRS0_SPOR. */
 916 #define BF_RCM_SSRS0_SPOR(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SPOR) & BM_RCM_SSRS0_SPOR)
 917
 918 /*! @brief Set the SPOR field to a new value. */
 919 #define BW_RCM_SSRS0_SPOR(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPOR) = (v))
 920 /*@}*/
 921
 922 /*******************************************************************************
 923  * HW_RCM_SSRS1 - Sticky System Reset Status Register 1
 924  ******************************************************************************/
 925
 926 /*!
 927  * @brief HW_RCM_SSRS1 - Sticky System Reset Status Register 1 (RW)
 928  *
 929  * Reset value: 0x00U
 930  *
 931  * This register includes status flags to indicate all reset sources since the
 932  * last POR, LVD or VLLS Wakeup that have not been cleared by software. Software
 933  * can clear the status flags by writing a logic one to a flag.
 934  */
 935 typedef union _hw_rcm_ssrs1
 936 {
 937     uint8_t U;
 938     struct _hw_rcm_ssrs1_bitfields
 939     {
 940         uint8_t SJTAG : 1;             /*!< [0] Sticky JTAG Generated Reset */
 941         uint8_t SLOCKUP : 1;           /*!< [1] Sticky Core Lockup */
 942         uint8_t SSW : 1;               /*!< [2] Sticky Software */
 943         uint8_t SMDM_AP : 1;           /*!< [3] Sticky MDM-AP System Reset Request */
 944         uint8_t SEZPT : 1;             /*!< [4] Sticky EzPort Reset */
 945         uint8_t SSACKERR : 1;          /*!< [5] Sticky Stop Mode Acknowledge Error
 946                                         * Reset */
 947         uint8_t RESERVED0 : 2;         /*!< [7:6]  */
 948     } B;
 949 } hw_rcm_ssrs1_t;
 950
 951 /*!
 952  * @name Constants and macros for entire RCM_SSRS1 register
 953  */
 954 /*@{*/
 955 #define HW_RCM_SSRS1_ADDR(x)     ((x) + 0x9U)
 956
 957 #define HW_RCM_SSRS1(x)          (*(__IO hw_rcm_ssrs1_t *) HW_RCM_SSRS1_ADDR(x))
 958 #define HW_RCM_SSRS1_RD(x)       (HW_RCM_SSRS1(x).U)
 959 #define HW_RCM_SSRS1_WR(x, v)    (HW_RCM_SSRS1(x).U = (v))
 960 #define HW_RCM_SSRS1_SET(x, v)   (HW_RCM_SSRS1_WR(x, HW_RCM_SSRS1_RD(x) |  (v)))
 961 #define HW_RCM_SSRS1_CLR(x, v)   (HW_RCM_SSRS1_WR(x, HW_RCM_SSRS1_RD(x) & ~(v)))
 962 #define HW_RCM_SSRS1_TOG(x, v)   (HW_RCM_SSRS1_WR(x, HW_RCM_SSRS1_RD(x) ^  (v)))
 963 /*@}*/
 964
 965 /*
 966  * Constants & macros for individual RCM_SSRS1 bitfields
 967  */
 968
 969 /*!
 970  * @name Register RCM_SSRS1, field SJTAG[0] (W1C)
 971  *
 972  * Indicates a reset has been caused by JTAG selection of certain IR codes:
 973  * EZPORT, EXTEST, HIGHZ, and CLAMP.
 974  *
 975  * Values:
 976  * - 0 - Reset not caused by JTAG
 977  * - 1 - Reset caused by JTAG
 978  */
 979 /*@{*/
 980 #define BP_RCM_SSRS1_SJTAG   (0U)          /*!< Bit position for RCM_SSRS1_SJTAG. */
 981 #define BM_RCM_SSRS1_SJTAG   (0x01U)       /*!< Bit mask for RCM_SSRS1_SJTAG. */
 982 #define BS_RCM_SSRS1_SJTAG   (1U)          /*!< Bit field size in bits for RCM_SSRS1_SJTAG. */
 983
 984 /*! @brief Read current value of the RCM_SSRS1_SJTAG field. */
 985 #define BR_RCM_SSRS1_SJTAG(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SJTAG))
 986
 987 /*! @brief Format value for bitfield RCM_SSRS1_SJTAG. */
 988 #define BF_RCM_SSRS1_SJTAG(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SJTAG) & BM_RCM_SSRS1_SJTAG)
 989
 990 /*! @brief Set the SJTAG field to a new value. */
 991 #define BW_RCM_SSRS1_SJTAG(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SJTAG) = (v))
 992 /*@}*/
 993
 994 /*!
 995  * @name Register RCM_SSRS1, field SLOCKUP[1] (W1C)
 996  *
 997  * Indicates a reset has been caused by the ARM core indication of a LOCKUP
 998  * event.
 999  *
1000  * Values:
1001  * - 0 - Reset not caused by core LOCKUP event
1002  * - 1 - Reset caused by core LOCKUP event
1003  */
1004 /*@{*/
1005 #define BP_RCM_SSRS1_SLOCKUP (1U)          /*!< Bit position for RCM_SSRS1_SLOCKUP. */
1006 #define BM_RCM_SSRS1_SLOCKUP (0x02U)       /*!< Bit mask for RCM_SSRS1_SLOCKUP. */
1007 #define BS_RCM_SSRS1_SLOCKUP (1U)          /*!< Bit field size in bits for RCM_SSRS1_SLOCKUP. */
1008
1009 /*! @brief Read current value of the RCM_SSRS1_SLOCKUP field. */
1010 #define BR_RCM_SSRS1_SLOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SLOCKUP))
1011
1012 /*! @brief Format value for bitfield RCM_SSRS1_SLOCKUP. */
1013 #define BF_RCM_SSRS1_SLOCKUP(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SLOCKUP) & BM_RCM_SSRS1_SLOCKUP)
1014
1015 /*! @brief Set the SLOCKUP field to a new value. */
1016 #define BW_RCM_SSRS1_SLOCKUP(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SLOCKUP) = (v))
1017 /*@}*/
1018
1019 /*!
1020  * @name Register RCM_SSRS1, field SSW[2] (W1C)
1021  *
1022  * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
1023  * Application Interrupt and Reset Control Register in the ARM core.
1024  *
1025  * Values:
1026  * - 0 - Reset not caused by software setting of SYSRESETREQ bit
1027  * - 1 - Reset caused by software setting of SYSRESETREQ bit
1028  */
1029 /*@{*/
1030 #define BP_RCM_SSRS1_SSW     (2U)          /*!< Bit position for RCM_SSRS1_SSW. */
1031 #define BM_RCM_SSRS1_SSW     (0x04U)       /*!< Bit mask for RCM_SSRS1_SSW. */
1032 #define BS_RCM_SSRS1_SSW     (1U)          /*!< Bit field size in bits for RCM_SSRS1_SSW. */
1033
1034 /*! @brief Read current value of the RCM_SSRS1_SSW field. */
1035 #define BR_RCM_SSRS1_SSW(x)  (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSW))
1036
1037 /*! @brief Format value for bitfield RCM_SSRS1_SSW. */
1038 #define BF_RCM_SSRS1_SSW(v)  ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SSW) & BM_RCM_SSRS1_SSW)
1039
1040 /*! @brief Set the SSW field to a new value. */
1041 #define BW_RCM_SSRS1_SSW(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSW) = (v))
1042 /*@}*/
1043
1044 /*!
1045  * @name Register RCM_SSRS1, field SMDM_AP[3] (W1C)
1046  *
1047  * Indicates a reset has been caused by the host debugger system setting of the
1048  * System Reset Request bit in the MDM-AP Control Register.
1049  *
1050  * Values:
1051  * - 0 - Reset not caused by host debugger system setting of the System Reset
1052  *     Request bit
1053  * - 1 - Reset caused by host debugger system setting of the System Reset
1054  *     Request bit
1055  */
1056 /*@{*/
1057 #define BP_RCM_SSRS1_SMDM_AP (3U)          /*!< Bit position for RCM_SSRS1_SMDM_AP. */
1058 #define BM_RCM_SSRS1_SMDM_AP (0x08U)       /*!< Bit mask for RCM_SSRS1_SMDM_AP. */
1059 #define BS_RCM_SSRS1_SMDM_AP (1U)          /*!< Bit field size in bits for RCM_SSRS1_SMDM_AP. */
1060
1061 /*! @brief Read current value of the RCM_SSRS1_SMDM_AP field. */
1062 #define BR_RCM_SSRS1_SMDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SMDM_AP))
1063
1064 /*! @brief Format value for bitfield RCM_SSRS1_SMDM_AP. */
1065 #define BF_RCM_SSRS1_SMDM_AP(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SMDM_AP) & BM_RCM_SSRS1_SMDM_AP)
1066
1067 /*! @brief Set the SMDM_AP field to a new value. */
1068 #define BW_RCM_SSRS1_SMDM_AP(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SMDM_AP) = (v))
1069 /*@}*/
1070
1071 /*!
1072  * @name Register RCM_SSRS1, field SEZPT[4] (W1C)
1073  *
1074  * Indicates a reset has been caused by EzPort receiving the RESET command while
1075  * the device is in EzPort mode.
1076  *
1077  * Values:
1078  * - 0 - Reset not caused by EzPort receiving the RESET command while the device
1079  *     is in EzPort mode
1080  * - 1 - Reset caused by EzPort receiving the RESET command while the device is
1081  *     in EzPort mode
1082  */
1083 /*@{*/
1084 #define BP_RCM_SSRS1_SEZPT   (4U)          /*!< Bit position for RCM_SSRS1_SEZPT. */
1085 #define BM_RCM_SSRS1_SEZPT   (0x10U)       /*!< Bit mask for RCM_SSRS1_SEZPT. */
1086 #define BS_RCM_SSRS1_SEZPT   (1U)          /*!< Bit field size in bits for RCM_SSRS1_SEZPT. */
1087
1088 /*! @brief Read current value of the RCM_SSRS1_SEZPT field. */
1089 #define BR_RCM_SSRS1_SEZPT(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SEZPT))
1090
1091 /*! @brief Format value for bitfield RCM_SSRS1_SEZPT. */
1092 #define BF_RCM_SSRS1_SEZPT(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SEZPT) & BM_RCM_SSRS1_SEZPT)
1093
1094 /*! @brief Set the SEZPT field to a new value. */
1095 #define BW_RCM_SSRS1_SEZPT(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SEZPT) = (v))
1096 /*@}*/
1097
1098 /*!
1099  * @name Register RCM_SSRS1, field SSACKERR[5] (W1C)
1100  *
1101  * Indicates that after an attempt to enter Stop mode, a reset has been caused
1102  * by a failure of one or more peripherals to acknowledge within approximately one
1103  * second to enter stop mode.
1104  *
1105  * Values:
1106  * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
1107  *     stop mode
1108  * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
1109  *     mode
1110  */
1111 /*@{*/
1112 #define BP_RCM_SSRS1_SSACKERR (5U)         /*!< Bit position for RCM_SSRS1_SSACKERR. */
1113 #define BM_RCM_SSRS1_SSACKERR (0x20U)      /*!< Bit mask for RCM_SSRS1_SSACKERR. */
1114 #define BS_RCM_SSRS1_SSACKERR (1U)         /*!< Bit field size in bits for RCM_SSRS1_SSACKERR. */
1115
1116 /*! @brief Read current value of the RCM_SSRS1_SSACKERR field. */
1117 #define BR_RCM_SSRS1_SSACKERR(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSACKERR))
1118
1119 /*! @brief Format value for bitfield RCM_SSRS1_SSACKERR. */
1120 #define BF_RCM_SSRS1_SSACKERR(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SSACKERR) & BM_RCM_SSRS1_SSACKERR)
1121
1122 /*! @brief Set the SSACKERR field to a new value. */
1123 #define BW_RCM_SSRS1_SSACKERR(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSACKERR) = (v))
1124 /*@}*/
1125
1126 /*******************************************************************************
1127  * hw_rcm_t - module struct
1128  ******************************************************************************/
1129 /*!
1130  * @brief All RCM module registers.
1131  */
1132 #pragma pack(1)
1133 typedef struct _hw_rcm
1134 {
1135     __I hw_rcm_srs0_t SRS0;                /*!< [0x0] System Reset Status Register 0 */
1136     __I hw_rcm_srs1_t SRS1;                /*!< [0x1] System Reset Status Register 1 */
1137     uint8_t _reserved0[2];
1138     __IO hw_rcm_rpfc_t RPFC;               /*!< [0x4] Reset Pin Filter Control register */
1139     __IO hw_rcm_rpfw_t RPFW;               /*!< [0x5] Reset Pin Filter Width register */
1140     uint8_t _reserved1[1];
1141     __I hw_rcm_mr_t MR;                    /*!< [0x7] Mode Register */
1142     __IO hw_rcm_ssrs0_t SSRS0;             /*!< [0x8] Sticky System Reset Status Register 0 */
1143     __IO hw_rcm_ssrs1_t SSRS1;             /*!< [0x9] Sticky System Reset Status Register 1 */
1144 } hw_rcm_t;
1145 #pragma pack()
1146
1147 /*! @brief Macro to access all RCM registers. */
1148 /*! @param x RCM module instance base address. */
1149 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1150  *     use the '&' operator, like <code>&HW_RCM(RCM_BASE)</code>. */
1151 #define HW_RCM(x)      (*(hw_rcm_t *)(x))
1152
1153 #endif /* __HW_RCM_REGISTERS_H__ */
1154 /* EOF */