2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_UART_REGISTERS_H__
78 #define __HW_UART_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Serial Communication Interface
88 * Registers defined in this header file:
89 * - HW_UART_BDH - UART Baud Rate Registers: High
90 * - HW_UART_BDL - UART Baud Rate Registers: Low
91 * - HW_UART_C1 - UART Control Register 1
92 * - HW_UART_C2 - UART Control Register 2
93 * - HW_UART_S1 - UART Status Register 1
94 * - HW_UART_S2 - UART Status Register 2
95 * - HW_UART_C3 - UART Control Register 3
96 * - HW_UART_D - UART Data Register
97 * - HW_UART_MA1 - UART Match Address Registers 1
98 * - HW_UART_MA2 - UART Match Address Registers 2
99 * - HW_UART_C4 - UART Control Register 4
100 * - HW_UART_C5 - UART Control Register 5
101 * - HW_UART_ED - UART Extended Data Register
102 * - HW_UART_MODEM - UART Modem Register
103 * - HW_UART_IR - UART Infrared Register
104 * - HW_UART_PFIFO - UART FIFO Parameters
105 * - HW_UART_CFIFO - UART FIFO Control Register
106 * - HW_UART_SFIFO - UART FIFO Status Register
107 * - HW_UART_TWFIFO - UART FIFO Transmit Watermark
108 * - HW_UART_TCFIFO - UART FIFO Transmit Count
109 * - HW_UART_RWFIFO - UART FIFO Receive Watermark
110 * - HW_UART_RCFIFO - UART FIFO Receive Count
111 * - HW_UART_C7816 - UART 7816 Control Register
112 * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
113 * - HW_UART_IS7816 - UART 7816 Interrupt Status Register
114 * - HW_UART_WP7816 - UART 7816 Wait Parameter Register
115 * - HW_UART_WN7816 - UART 7816 Wait N Register
116 * - HW_UART_WF7816 - UART 7816 Wait FD Register
117 * - HW_UART_ET7816 - UART 7816 Error Threshold Register
118 * - HW_UART_TL7816 - UART 7816 Transmit Length Register
119 * - HW_UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A
120 * - HW_UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B
121 * - HW_UART_WP7816A_T0 - UART 7816 Wait Parameter Register A
122 * - HW_UART_WP7816B_T0 - UART 7816 Wait Parameter Register B
123 * - HW_UART_WP7816A_T1 - UART 7816 Wait Parameter Register A
124 * - HW_UART_WP7816B_T1 - UART 7816 Wait Parameter Register B
125 * - HW_UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register
126 * - HW_UART_WP7816C_T1 - UART 7816 Wait Parameter Register C
128 * - hw_uart_t - Struct containing all module registers.
131 #define HW_UART_INSTANCE_COUNT (3U) /*!< Number of instances of the UART module. */
132 #define HW_UART0 (0U) /*!< Instance number for UART0. */
133 #define HW_UART1 (1U) /*!< Instance number for UART1. */
134 #define HW_UART2 (2U) /*!< Instance number for UART2. */
136 /*******************************************************************************
137 * HW_UART_BDH - UART Baud Rate Registers: High
138 ******************************************************************************/
141 * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
145 * This register, along with the BDL register, controls the prescale divisor for
146 * UART baud rate generation. To update the 13-bit baud rate setting
147 * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
148 * to BDL. The working value in BDH does not change until BDL is written. BDL is
149 * reset to a nonzero value, but after reset, the baud rate generator remains
150 * disabled until the first time the receiver or transmitter is enabled, that is,
151 * when C2[RE] or C2[TE] is set.
153 typedef union _hw_uart_bdh
156 struct _hw_uart_bdh_bitfields
158 uint8_t SBR
: 5; /*!< [4:0] UART Baud Rate Bits */
159 uint8_t RESERVED0
: 1; /*!< [5] */
160 uint8_t RXEDGIE
: 1; /*!< [6] RxD Input Active Edge Interrupt Enable
162 uint8_t LBKDIE
: 1; /*!< [7] LIN Break Detect Interrupt Enable */
167 * @name Constants and macros for entire UART_BDH register
170 #define HW_UART_BDH_ADDR(x) ((x) + 0x0U)
172 #define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x))
173 #define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U)
174 #define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v))
175 #define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v)))
176 #define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
177 #define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v)))
181 * Constants & macros for individual UART_BDH bitfields
185 * @name Register UART_BDH, field SBR[4:0] (RW)
187 * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
188 * generation for details. The baud rate generator is disabled until C2[TE] or
189 * C2[RE] is set for the first time after reset.The baud rate generator is disabled
190 * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
191 * writing to BDH puts the data in a temporary location until BDL is written.
194 #define BP_UART_BDH_SBR (0U) /*!< Bit position for UART_BDH_SBR. */
195 #define BM_UART_BDH_SBR (0x1FU) /*!< Bit mask for UART_BDH_SBR. */
196 #define BS_UART_BDH_SBR (5U) /*!< Bit field size in bits for UART_BDH_SBR. */
198 /*! @brief Read current value of the UART_BDH_SBR field. */
199 #define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR)
201 /*! @brief Format value for bitfield UART_BDH_SBR. */
202 #define BF_UART_BDH_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR)
204 /*! @brief Set the SBR field to a new value. */
205 #define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v)))
209 * @name Register UART_BDH, field RXEDGIE[6] (RW)
211 * Enables the receive input active edge, RXEDGIF, to generate interrupt
215 * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
216 * - 1 - RXEDGIF interrupt request enabled.
219 #define BP_UART_BDH_RXEDGIE (6U) /*!< Bit position for UART_BDH_RXEDGIE. */
220 #define BM_UART_BDH_RXEDGIE (0x40U) /*!< Bit mask for UART_BDH_RXEDGIE. */
221 #define BS_UART_BDH_RXEDGIE (1U) /*!< Bit field size in bits for UART_BDH_RXEDGIE. */
223 /*! @brief Read current value of the UART_BDH_RXEDGIE field. */
224 #define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
226 /*! @brief Format value for bitfield UART_BDH_RXEDGIE. */
227 #define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE)
229 /*! @brief Set the RXEDGIE field to a new value. */
230 #define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
234 * @name Register UART_BDH, field LBKDIE[7] (RW)
236 * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
237 * based on the state of LBKDDMAS.
240 * - 0 - LBKDIF interrupt requests disabled.
241 * - 1 - LBKDIF interrupt requests enabled.
244 #define BP_UART_BDH_LBKDIE (7U) /*!< Bit position for UART_BDH_LBKDIE. */
245 #define BM_UART_BDH_LBKDIE (0x80U) /*!< Bit mask for UART_BDH_LBKDIE. */
246 #define BS_UART_BDH_LBKDIE (1U) /*!< Bit field size in bits for UART_BDH_LBKDIE. */
248 /*! @brief Read current value of the UART_BDH_LBKDIE field. */
249 #define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
251 /*! @brief Format value for bitfield UART_BDH_LBKDIE. */
252 #define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE)
254 /*! @brief Set the LBKDIE field to a new value. */
255 #define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
258 /*******************************************************************************
259 * HW_UART_BDL - UART Baud Rate Registers: Low
260 ******************************************************************************/
263 * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
267 * This register, along with the BDH register, controls the prescale divisor for
268 * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
269 * first write to BDH to buffer the high half of the new value and then write to
270 * BDL. The working value in BDH does not change until BDL is written. BDL is
271 * reset to a nonzero value, but after reset, the baud rate generator remains
272 * disabled until the first time the receiver or transmitter is enabled, that is, when
273 * C2[RE] or C2[TE] is set.
275 typedef union _hw_uart_bdl
278 struct _hw_uart_bdl_bitfields
280 uint8_t SBR
: 8; /*!< [7:0] UART Baud Rate Bits */
285 * @name Constants and macros for entire UART_BDL register
288 #define HW_UART_BDL_ADDR(x) ((x) + 0x1U)
290 #define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x))
291 #define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U)
292 #define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v))
293 #define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v)))
294 #define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
295 #define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v)))
299 * Constants & macros for individual UART_BDL bitfields
303 * @name Register UART_BDL, field SBR[7:0] (RW)
305 * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
306 * generation for details. The baud rate generator is disabled until C2[TE] or
307 * C2[RE] is set for the first time after reset.The baud rate generator is disabled
308 * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
309 * writing to BDH puts the data in a temporary location until BDL is written. When
310 * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
311 * fields must be even, the least significant bit is 0. See MODEM register for more
315 #define BP_UART_BDL_SBR (0U) /*!< Bit position for UART_BDL_SBR. */
316 #define BM_UART_BDL_SBR (0xFFU) /*!< Bit mask for UART_BDL_SBR. */
317 #define BS_UART_BDL_SBR (8U) /*!< Bit field size in bits for UART_BDL_SBR. */
319 /*! @brief Read current value of the UART_BDL_SBR field. */
320 #define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U)
322 /*! @brief Format value for bitfield UART_BDL_SBR. */
323 #define BF_UART_BDL_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR)
325 /*! @brief Set the SBR field to a new value. */
326 #define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
329 /*******************************************************************************
330 * HW_UART_C1 - UART Control Register 1
331 ******************************************************************************/
334 * @brief HW_UART_C1 - UART Control Register 1 (RW)
338 * This read/write register controls various optional features of the UART
341 typedef union _hw_uart_c1
344 struct _hw_uart_c1_bitfields
346 uint8_t PT
: 1; /*!< [0] Parity Type */
347 uint8_t PE
: 1; /*!< [1] Parity Enable */
348 uint8_t ILT
: 1; /*!< [2] Idle Line Type Select */
349 uint8_t WAKE
: 1; /*!< [3] Receiver Wakeup Method Select */
350 uint8_t M
: 1; /*!< [4] 9-bit or 8-bit Mode Select */
351 uint8_t RSRC
: 1; /*!< [5] Receiver Source Select */
352 uint8_t UARTSWAI
: 1; /*!< [6] UART Stops in Wait Mode */
353 uint8_t LOOPS
: 1; /*!< [7] Loop Mode Select */
358 * @name Constants and macros for entire UART_C1 register
361 #define HW_UART_C1_ADDR(x) ((x) + 0x2U)
363 #define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x))
364 #define HW_UART_C1_RD(x) (HW_UART_C1(x).U)
365 #define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v))
366 #define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v)))
367 #define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
368 #define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v)))
372 * Constants & macros for individual UART_C1 bitfields
376 * @name Register UART_C1, field PT[0] (RW)
378 * Determines whether the UART generates and checks for even parity or odd
379 * parity. With even parity, an even number of 1s clears the parity bit and an odd
380 * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
381 * parity bit and an even number of 1s sets the parity bit. This field must be
382 * cleared when C7816[ISO_7816E] is set/enabled.
389 #define BP_UART_C1_PT (0U) /*!< Bit position for UART_C1_PT. */
390 #define BM_UART_C1_PT (0x01U) /*!< Bit mask for UART_C1_PT. */
391 #define BS_UART_C1_PT (1U) /*!< Bit field size in bits for UART_C1_PT. */
393 /*! @brief Read current value of the UART_C1_PT field. */
394 #define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
396 /*! @brief Format value for bitfield UART_C1_PT. */
397 #define BF_UART_C1_PT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT)
399 /*! @brief Set the PT field to a new value. */
400 #define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
404 * @name Register UART_C1, field PE[1] (RW)
406 * Enables the parity function. When parity is enabled, parity function inserts
407 * a parity bit in the bit position immediately preceding the stop bit. This
408 * field must be set when C7816[ISO_7816E] is set/enabled.
411 * - 0 - Parity function disabled.
412 * - 1 - Parity function enabled.
415 #define BP_UART_C1_PE (1U) /*!< Bit position for UART_C1_PE. */
416 #define BM_UART_C1_PE (0x02U) /*!< Bit mask for UART_C1_PE. */
417 #define BS_UART_C1_PE (1U) /*!< Bit field size in bits for UART_C1_PE. */
419 /*! @brief Read current value of the UART_C1_PE field. */
420 #define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
422 /*! @brief Format value for bitfield UART_C1_PE. */
423 #define BF_UART_C1_PE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE)
425 /*! @brief Set the PE field to a new value. */
426 #define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
430 * @name Register UART_C1, field ILT[2] (RW)
432 * Determines when the receiver starts counting logic 1s as idle character bits.
433 * The count begins either after a valid start bit or after the stop bit. If the
434 * count begins after the start bit, then a string of logic 1s preceding the
435 * stop bit can cause false recognition of an idle character. Beginning the count
436 * after the stop bit avoids false idle character recognition, but requires
437 * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
438 * logic of 1'b0 is automatically shifted after a received stop bit, therefore
439 * resetting the idle count. In case the UART is programmed for IDLE line wakeup
440 * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
441 * logic 1s as idle character bits. In idle line wakeup, an idle character is
442 * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
443 * and C4[M10] fields.
446 * - 0 - Idle character bit count starts after start bit.
447 * - 1 - Idle character bit count starts after stop bit.
450 #define BP_UART_C1_ILT (2U) /*!< Bit position for UART_C1_ILT. */
451 #define BM_UART_C1_ILT (0x04U) /*!< Bit mask for UART_C1_ILT. */
452 #define BS_UART_C1_ILT (1U) /*!< Bit field size in bits for UART_C1_ILT. */
454 /*! @brief Read current value of the UART_C1_ILT field. */
455 #define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
457 /*! @brief Format value for bitfield UART_C1_ILT. */
458 #define BF_UART_C1_ILT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT)
460 /*! @brief Set the ILT field to a new value. */
461 #define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
465 * @name Register UART_C1, field WAKE[3] (RW)
467 * Determines which condition wakes the UART: Address mark in the most
468 * significant bit position of a received data character, or An idle condition on the
469 * receive pin input signal.
472 * - 0 - Idle line wakeup.
473 * - 1 - Address mark wakeup.
476 #define BP_UART_C1_WAKE (3U) /*!< Bit position for UART_C1_WAKE. */
477 #define BM_UART_C1_WAKE (0x08U) /*!< Bit mask for UART_C1_WAKE. */
478 #define BS_UART_C1_WAKE (1U) /*!< Bit field size in bits for UART_C1_WAKE. */
480 /*! @brief Read current value of the UART_C1_WAKE field. */
481 #define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
483 /*! @brief Format value for bitfield UART_C1_WAKE. */
484 #define BF_UART_C1_WAKE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE)
486 /*! @brief Set the WAKE field to a new value. */
487 #define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
491 * @name Register UART_C1, field M[4] (RW)
493 * This field must be set when C7816[ISO_7816E] is set/enabled.
496 * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
497 * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
500 #define BP_UART_C1_M (4U) /*!< Bit position for UART_C1_M. */
501 #define BM_UART_C1_M (0x10U) /*!< Bit mask for UART_C1_M. */
502 #define BS_UART_C1_M (1U) /*!< Bit field size in bits for UART_C1_M. */
504 /*! @brief Read current value of the UART_C1_M field. */
505 #define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
507 /*! @brief Format value for bitfield UART_C1_M. */
508 #define BF_UART_C1_M(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M)
510 /*! @brief Set the M field to a new value. */
511 #define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
515 * @name Register UART_C1, field RSRC[5] (RW)
517 * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
518 * is set, the RSRC field determines the source for the receiver shift register
522 * - 0 - Selects internal loop back mode. The receiver input is internally
523 * connected to transmitter output.
524 * - 1 - Single wire UART mode where the receiver input is connected to the
525 * transmit pin input signal.
528 #define BP_UART_C1_RSRC (5U) /*!< Bit position for UART_C1_RSRC. */
529 #define BM_UART_C1_RSRC (0x20U) /*!< Bit mask for UART_C1_RSRC. */
530 #define BS_UART_C1_RSRC (1U) /*!< Bit field size in bits for UART_C1_RSRC. */
532 /*! @brief Read current value of the UART_C1_RSRC field. */
533 #define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
535 /*! @brief Format value for bitfield UART_C1_RSRC. */
536 #define BF_UART_C1_RSRC(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC)
538 /*! @brief Set the RSRC field to a new value. */
539 #define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
543 * @name Register UART_C1, field UARTSWAI[6] (RW)
546 * - 0 - UART clock continues to run in Wait mode.
547 * - 1 - UART clock freezes while CPU is in Wait mode.
550 #define BP_UART_C1_UARTSWAI (6U) /*!< Bit position for UART_C1_UARTSWAI. */
551 #define BM_UART_C1_UARTSWAI (0x40U) /*!< Bit mask for UART_C1_UARTSWAI. */
552 #define BS_UART_C1_UARTSWAI (1U) /*!< Bit field size in bits for UART_C1_UARTSWAI. */
554 /*! @brief Read current value of the UART_C1_UARTSWAI field. */
555 #define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
557 /*! @brief Format value for bitfield UART_C1_UARTSWAI. */
558 #define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI)
560 /*! @brief Set the UARTSWAI field to a new value. */
561 #define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
565 * @name Register UART_C1, field LOOPS[7] (RW)
567 * When LOOPS is set, the RxD pin is disconnected from the UART and the
568 * transmitter output is internally connected to the receiver input. The transmitter and
569 * the receiver must be enabled to use the loop function.
572 * - 0 - Normal operation.
573 * - 1 - Loop mode where transmitter output is internally connected to receiver
574 * input. The receiver input is determined by RSRC.
577 #define BP_UART_C1_LOOPS (7U) /*!< Bit position for UART_C1_LOOPS. */
578 #define BM_UART_C1_LOOPS (0x80U) /*!< Bit mask for UART_C1_LOOPS. */
579 #define BS_UART_C1_LOOPS (1U) /*!< Bit field size in bits for UART_C1_LOOPS. */
581 /*! @brief Read current value of the UART_C1_LOOPS field. */
582 #define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
584 /*! @brief Format value for bitfield UART_C1_LOOPS. */
585 #define BF_UART_C1_LOOPS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS)
587 /*! @brief Set the LOOPS field to a new value. */
588 #define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
591 /*******************************************************************************
592 * HW_UART_C2 - UART Control Register 2
593 ******************************************************************************/
596 * @brief HW_UART_C2 - UART Control Register 2 (RW)
600 * This register can be read or written at any time.
602 typedef union _hw_uart_c2
605 struct _hw_uart_c2_bitfields
607 uint8_t SBK
: 1; /*!< [0] Send Break */
608 uint8_t RWU
: 1; /*!< [1] Receiver Wakeup Control */
609 uint8_t RE
: 1; /*!< [2] Receiver Enable */
610 uint8_t TE
: 1; /*!< [3] Transmitter Enable */
611 uint8_t ILIE
: 1; /*!< [4] Idle Line Interrupt Enable */
612 uint8_t RIE
: 1; /*!< [5] Receiver Full Interrupt or DMA Transfer
614 uint8_t TCIE
: 1; /*!< [6] Transmission Complete Interrupt Enable */
615 uint8_t TIE
: 1; /*!< [7] Transmitter Interrupt or DMA Transfer
621 * @name Constants and macros for entire UART_C2 register
624 #define HW_UART_C2_ADDR(x) ((x) + 0x3U)
626 #define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x))
627 #define HW_UART_C2_RD(x) (HW_UART_C2(x).U)
628 #define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v))
629 #define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v)))
630 #define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
631 #define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v)))
635 * Constants & macros for individual UART_C2 bitfields
639 * @name Register UART_C2, field SBK[0] (RW)
641 * Toggling SBK sends one break character from the following: See Transmitting
642 * break characters for the number of logic 0s for the different configurations.
643 * Toggling implies clearing the SBK field before the break character has finished
644 * transmitting. As long as SBK is set, the transmitter continues to send
645 * complete break characters (10, 11, or 12 bits, or 13 or 14 bits). Ensure that C2[TE]
646 * is asserted atleast 1 clock before assertion of this bit. 10, 11, or 12 logic
647 * 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13] is set. This field
648 * must be cleared when C7816[ISO_7816E] is set.
651 * - 0 - Normal transmitter operation.
652 * - 1 - Queue break characters to be sent.
655 #define BP_UART_C2_SBK (0U) /*!< Bit position for UART_C2_SBK. */
656 #define BM_UART_C2_SBK (0x01U) /*!< Bit mask for UART_C2_SBK. */
657 #define BS_UART_C2_SBK (1U) /*!< Bit field size in bits for UART_C2_SBK. */
659 /*! @brief Read current value of the UART_C2_SBK field. */
660 #define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
662 /*! @brief Format value for bitfield UART_C2_SBK. */
663 #define BF_UART_C2_SBK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK)
665 /*! @brief Set the SBK field to a new value. */
666 #define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
670 * @name Register UART_C2, field RWU[1] (RW)
672 * This field can be set to place the UART receiver in a standby state. RWU
673 * automatically clears when an RWU event occurs, that is, an IDLE event when
674 * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
675 * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
676 * on idle) if the channel is currently not idle. This can be determined by
677 * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
678 * idle, it is possible that the UART will discard data. This is because the data
679 * must be received or a LIN break detected after an IDLE is detected before IDLE
680 * is allowed to reasserted.
683 * - 0 - Normal operation.
684 * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
685 * requests. Normally, hardware wakes the receiver by automatically clearing
689 #define BP_UART_C2_RWU (1U) /*!< Bit position for UART_C2_RWU. */
690 #define BM_UART_C2_RWU (0x02U) /*!< Bit mask for UART_C2_RWU. */
691 #define BS_UART_C2_RWU (1U) /*!< Bit field size in bits for UART_C2_RWU. */
693 /*! @brief Read current value of the UART_C2_RWU field. */
694 #define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
696 /*! @brief Format value for bitfield UART_C2_RWU. */
697 #define BF_UART_C2_RWU(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU)
699 /*! @brief Set the RWU field to a new value. */
700 #define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
704 * @name Register UART_C2, field RE[2] (RW)
706 * Enables the UART receiver.
709 * - 0 - Receiver off.
713 #define BP_UART_C2_RE (2U) /*!< Bit position for UART_C2_RE. */
714 #define BM_UART_C2_RE (0x04U) /*!< Bit mask for UART_C2_RE. */
715 #define BS_UART_C2_RE (1U) /*!< Bit field size in bits for UART_C2_RE. */
717 /*! @brief Read current value of the UART_C2_RE field. */
718 #define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
720 /*! @brief Format value for bitfield UART_C2_RE. */
721 #define BF_UART_C2_RE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE)
723 /*! @brief Set the RE field to a new value. */
724 #define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
728 * @name Register UART_C2, field TE[3] (RW)
730 * Enables the UART transmitter. TE can be used to queue an idle preamble by
731 * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
732 * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
733 * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
734 * additional characters are transmitted.
737 * - 0 - Transmitter off.
738 * - 1 - Transmitter on.
741 #define BP_UART_C2_TE (3U) /*!< Bit position for UART_C2_TE. */
742 #define BM_UART_C2_TE (0x08U) /*!< Bit mask for UART_C2_TE. */
743 #define BS_UART_C2_TE (1U) /*!< Bit field size in bits for UART_C2_TE. */
745 /*! @brief Read current value of the UART_C2_TE field. */
746 #define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
748 /*! @brief Format value for bitfield UART_C2_TE. */
749 #define BF_UART_C2_TE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE)
751 /*! @brief Set the TE field to a new value. */
752 #define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
756 * @name Register UART_C2, field ILIE[4] (RW)
758 * Enables the idle line flag, S1[IDLE], to generate interrupt requests
761 * - 0 - IDLE interrupt requests disabled.
762 * - 1 - IDLE interrupt requests enabled.
765 #define BP_UART_C2_ILIE (4U) /*!< Bit position for UART_C2_ILIE. */
766 #define BM_UART_C2_ILIE (0x10U) /*!< Bit mask for UART_C2_ILIE. */
767 #define BS_UART_C2_ILIE (1U) /*!< Bit field size in bits for UART_C2_ILIE. */
769 /*! @brief Read current value of the UART_C2_ILIE field. */
770 #define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
772 /*! @brief Format value for bitfield UART_C2_ILIE. */
773 #define BF_UART_C2_ILIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE)
775 /*! @brief Set the ILIE field to a new value. */
776 #define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
780 * @name Register UART_C2, field RIE[5] (RW)
782 * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
783 * based on the state of C5[RDMAS].
786 * - 0 - RDRF interrupt and DMA transfer requests disabled.
787 * - 1 - RDRF interrupt or DMA transfer requests enabled.
790 #define BP_UART_C2_RIE (5U) /*!< Bit position for UART_C2_RIE. */
791 #define BM_UART_C2_RIE (0x20U) /*!< Bit mask for UART_C2_RIE. */
792 #define BS_UART_C2_RIE (1U) /*!< Bit field size in bits for UART_C2_RIE. */
794 /*! @brief Read current value of the UART_C2_RIE field. */
795 #define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
797 /*! @brief Format value for bitfield UART_C2_RIE. */
798 #define BF_UART_C2_RIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE)
800 /*! @brief Set the RIE field to a new value. */
801 #define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
805 * @name Register UART_C2, field TCIE[6] (RW)
807 * Enables the transmission complete flag, S1[TC], to generate interrupt
811 * - 0 - TC interrupt requests disabled.
812 * - 1 - TC interrupt requests enabled.
815 #define BP_UART_C2_TCIE (6U) /*!< Bit position for UART_C2_TCIE. */
816 #define BM_UART_C2_TCIE (0x40U) /*!< Bit mask for UART_C2_TCIE. */
817 #define BS_UART_C2_TCIE (1U) /*!< Bit field size in bits for UART_C2_TCIE. */
819 /*! @brief Read current value of the UART_C2_TCIE field. */
820 #define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
822 /*! @brief Format value for bitfield UART_C2_TCIE. */
823 #define BF_UART_C2_TCIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE)
825 /*! @brief Set the TCIE field to a new value. */
826 #define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
830 * @name Register UART_C2, field TIE[7] (RW)
832 * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
833 * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
834 * must be cleared, and D[D] must not be written unless servicing a DMA request.
837 * - 0 - TDRE interrupt and DMA transfer requests disabled.
838 * - 1 - TDRE interrupt or DMA transfer requests enabled.
841 #define BP_UART_C2_TIE (7U) /*!< Bit position for UART_C2_TIE. */
842 #define BM_UART_C2_TIE (0x80U) /*!< Bit mask for UART_C2_TIE. */
843 #define BS_UART_C2_TIE (1U) /*!< Bit field size in bits for UART_C2_TIE. */
845 /*! @brief Read current value of the UART_C2_TIE field. */
846 #define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
848 /*! @brief Format value for bitfield UART_C2_TIE. */
849 #define BF_UART_C2_TIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE)
851 /*! @brief Set the TIE field to a new value. */
852 #define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
855 /*******************************************************************************
856 * HW_UART_S1 - UART Status Register 1
857 ******************************************************************************/
860 * @brief HW_UART_S1 - UART Status Register 1 (RO)
864 * The S1 register provides inputs to the MCU for generation of UART interrupts
865 * or DMA requests. This register can also be polled by the MCU to check the
866 * status of its fields. To clear a flag, the status register should be read followed
867 * by a read or write to D register, depending on the interrupt flag type. Other
868 * instructions can be executed between the two steps as long the handling of
869 * I/O is not compromised, but the order of operations is important for flag
870 * clearing. When a flag is configured to trigger a DMA request, assertion of the
871 * associated DMA done signal from the DMA controller clears the flag. If the
872 * condition that results in the assertion of the flag, interrupt, or DMA request is not
873 * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
874 * reasserts. For example, if the DMA or interrupt service routine fails to write
875 * sufficient data to the transmit buffer to raise it above the watermark level, the
876 * flag reasserts and generates another interrupt or DMA request. Reading an
877 * empty data register to clear one of the flags of the S1 register causes the FIFO
878 * pointers to become misaligned. A receive FIFO flush reinitializes the
879 * pointers. A better way to prevent this situation is to always leave one byte in FIFO
880 * and this byte will be read eventually in clearing the flag bit.
882 typedef union _hw_uart_s1
885 struct _hw_uart_s1_bitfields
887 uint8_t PF
: 1; /*!< [0] Parity Error Flag */
888 uint8_t FE
: 1; /*!< [1] Framing Error Flag */
889 uint8_t NF
: 1; /*!< [2] Noise Flag */
890 uint8_t OR
: 1; /*!< [3] Receiver Overrun Flag */
891 uint8_t IDLE
: 1; /*!< [4] Idle Line Flag */
892 uint8_t RDRF
: 1; /*!< [5] Receive Data Register Full Flag */
893 uint8_t TC
: 1; /*!< [6] Transmit Complete Flag */
894 uint8_t TDRE
: 1; /*!< [7] Transmit Data Register Empty Flag */
899 * @name Constants and macros for entire UART_S1 register
902 #define HW_UART_S1_ADDR(x) ((x) + 0x4U)
904 #define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x))
905 #define HW_UART_S1_RD(x) (HW_UART_S1(x).U)
909 * Constants & macros for individual UART_S1 bitfields
913 * @name Register UART_S1, field PF[0] (RO)
915 * PF is set when PE is set and the parity of the received data does not match
916 * its parity bit. The PF is not set in the case of an overrun condition. When PF
917 * is set, it indicates only that a dataword was received with parity error since
918 * the last time it was cleared. There is no guarantee that the first dataword
919 * read from the receive buffer has a parity error or that there is only one
920 * dataword in the buffer that was received with a parity error, unless the receive
921 * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
922 * disabled, Within the receive buffer structure the received dataword is tagged
923 * if it is received with a parity error. This information is available by reading
924 * the ED register prior to reading the D register.
927 * - 0 - No parity error detected since the last time this flag was cleared. If
928 * the receive buffer has a depth greater than 1, then there may be data in
929 * the receive buffer what was received with a parity error.
930 * - 1 - At least one dataword was received with a parity error since the last
931 * time this flag was cleared.
934 #define BP_UART_S1_PF (0U) /*!< Bit position for UART_S1_PF. */
935 #define BM_UART_S1_PF (0x01U) /*!< Bit mask for UART_S1_PF. */
936 #define BS_UART_S1_PF (1U) /*!< Bit field size in bits for UART_S1_PF. */
938 /*! @brief Read current value of the UART_S1_PF field. */
939 #define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
943 * @name Register UART_S1, field FE[1] (RO)
945 * FE is set when a logic 0 is accepted as the stop bit. FE does not set in the
946 * case of an overrun or while the LIN break detect feature is enabled (S2[LBKDE]
947 * = 1). FE inhibits further data reception until it is cleared. To clear FE,
948 * read S1 with FE set and then read D. The last data in the receive buffer
949 * represents the data that was received with the frame error enabled. Framing errors
950 * are not supported when 7816E is set/enabled. However, if this flag is set, data
951 * is still not received in 7816 mode.
954 * - 0 - No framing error detected.
955 * - 1 - Framing error.
958 #define BP_UART_S1_FE (1U) /*!< Bit position for UART_S1_FE. */
959 #define BM_UART_S1_FE (0x02U) /*!< Bit mask for UART_S1_FE. */
960 #define BS_UART_S1_FE (1U) /*!< Bit field size in bits for UART_S1_FE. */
962 /*! @brief Read current value of the UART_S1_FE field. */
963 #define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
967 * @name Register UART_S1, field NF[2] (RO)
969 * NF is set when the UART detects noise on the receiver input. NF does not
970 * become set in the case of an overrun or while the LIN break detect feature is
971 * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
972 * been received with noise since the last time it was cleared. There is no
973 * guarantee that the first dataword read from the receive buffer has noise or that there
974 * is only one dataword in the buffer that was received with noise unless the
975 * receive buffer has a depth of one. To clear NF, read S1 and then read D.
978 * - 0 - No noise detected since the last time this flag was cleared. If the
979 * receive buffer has a depth greater than 1 then there may be data in the
980 * receiver buffer that was received with noise.
981 * - 1 - At least one dataword was received with noise detected since the last
982 * time the flag was cleared.
985 #define BP_UART_S1_NF (2U) /*!< Bit position for UART_S1_NF. */
986 #define BM_UART_S1_NF (0x04U) /*!< Bit mask for UART_S1_NF. */
987 #define BS_UART_S1_NF (1U) /*!< Bit field size in bits for UART_S1_NF. */
989 /*! @brief Read current value of the UART_S1_NF field. */
990 #define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
994 * @name Register UART_S1, field OR[3] (RO)
996 * OR is set when software fails to prevent the receive data register from
997 * overflowing with data. The OR bit is set immediately after the stop bit has been
998 * completely received for the dataword that overflows the buffer and all the other
999 * error flags (FE, NF, and PF) are prevented from setting. The data in the
1000 * shift register is lost, but the data already in the UART data registers is not
1001 * affected. If the OR flag is set, no data is stored in the data buffer even if
1002 * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
1003 * flags are blocked from asserting, that is, transition from an inactive to an
1004 * active state. To clear OR, read S1 when OR is set and then read D. See
1005 * functional description for more details regarding the operation of the OR bit.If
1006 * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
1007 * is not cleared before the next data character is received. In 7816 mode, it is
1008 * possible to configure a NACK to be returned by programing C7816[ONACK].
1011 * - 0 - No overrun has occurred since the last time the flag was cleared.
1012 * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
1013 * last overrun occured.
1016 #define BP_UART_S1_OR (3U) /*!< Bit position for UART_S1_OR. */
1017 #define BM_UART_S1_OR (0x08U) /*!< Bit mask for UART_S1_OR. */
1018 #define BS_UART_S1_OR (1U) /*!< Bit field size in bits for UART_S1_OR. */
1020 /*! @brief Read current value of the UART_S1_OR field. */
1021 #define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
1025 * @name Register UART_S1, field IDLE[4] (RO)
1027 * After the IDLE flag is cleared, a frame must be received (although not
1028 * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
1029 * break character must set the S2[LBKDIF] flag before an idle condition can set the
1030 * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
1031 * IDLE is set when either of the following appear on the receiver input: 10
1032 * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
1033 * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
1034 * detection is not supported when 7816E is set/enabled and hence this flag is
1035 * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
1036 * flag if RWUID is set, else the IDLE flag does not become set.
1039 * - 0 - Receiver input is either active now or has never become active since
1040 * the IDLE flag was last cleared.
1041 * - 1 - Receiver input has become idle or the flag has not been cleared since
1045 #define BP_UART_S1_IDLE (4U) /*!< Bit position for UART_S1_IDLE. */
1046 #define BM_UART_S1_IDLE (0x10U) /*!< Bit mask for UART_S1_IDLE. */
1047 #define BS_UART_S1_IDLE (1U) /*!< Bit field size in bits for UART_S1_IDLE. */
1049 /*! @brief Read current value of the UART_S1_IDLE field. */
1050 #define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
1054 * @name Register UART_S1, field RDRF[5] (RO)
1056 * RDRF is set when the number of datawords in the receive buffer is equal to or
1057 * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
1058 * process of being received is not included in the count. To clear RDRF, read S1
1059 * when RDRF is set and then read D. For more efficient interrupt and DMA
1060 * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
1061 * Then read S1 and the final data value, resulting in the clearing of the RDRF
1062 * flag. Even if RDRF is set, data will continue to be received until an overrun
1063 * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
1064 * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
1065 * buffer but over-write each other.
1068 * - 0 - The number of datawords in the receive buffer is less than the number
1069 * indicated by RXWATER.
1070 * - 1 - The number of datawords in the receive buffer is equal to or greater
1071 * than the number indicated by RXWATER at some point in time since this flag
1075 #define BP_UART_S1_RDRF (5U) /*!< Bit position for UART_S1_RDRF. */
1076 #define BM_UART_S1_RDRF (0x20U) /*!< Bit mask for UART_S1_RDRF. */
1077 #define BS_UART_S1_RDRF (1U) /*!< Bit field size in bits for UART_S1_RDRF. */
1079 /*! @brief Read current value of the UART_S1_RDRF field. */
1080 #define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
1084 * @name Register UART_S1, field TC[6] (RO)
1086 * TC is set when the transmit buffer is empty and no data, preamble, or break
1087 * character is being transmitted. When TC is set, the transmit data output signal
1088 * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
1089 * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
1090 * set after any NACK signal has been received, but prior to any corresponding
1091 * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
1092 * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
1096 * - 0 - Transmitter active (sending data, a preamble, or a break).
1097 * - 1 - Transmitter idle (transmission activity complete).
1100 #define BP_UART_S1_TC (6U) /*!< Bit position for UART_S1_TC. */
1101 #define BM_UART_S1_TC (0x40U) /*!< Bit mask for UART_S1_TC. */
1102 #define BS_UART_S1_TC (1U) /*!< Bit field size in bits for UART_S1_TC. */
1104 /*! @brief Read current value of the UART_S1_TC field. */
1105 #define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
1109 * @name Register UART_S1, field TDRE[7] (RO)
1111 * TDRE will set when the number of datawords in the transmit buffer (D and
1112 * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
1113 * character that is in the process of being transmitted is not included in the count.
1114 * To clear TDRE, read S1 when TDRE is set and then write to the UART data
1115 * register (D). For more efficient interrupt servicing, all data except the final value
1116 * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
1117 * before writing the final data value, resulting in the clearing of the TRDE
1118 * flag. This is more efficient because the TDRE reasserts until the watermark has
1119 * been exceeded. So, attempting to clear the TDRE with every write will be
1120 * ineffective until sufficient data has been written.
1123 * - 0 - The amount of data in the transmit buffer is greater than the value
1124 * indicated by TWFIFO[TXWATER].
1125 * - 1 - The amount of data in the transmit buffer is less than or equal to the
1126 * value indicated by TWFIFO[TXWATER] at some point in time since the flag
1130 #define BP_UART_S1_TDRE (7U) /*!< Bit position for UART_S1_TDRE. */
1131 #define BM_UART_S1_TDRE (0x80U) /*!< Bit mask for UART_S1_TDRE. */
1132 #define BS_UART_S1_TDRE (1U) /*!< Bit field size in bits for UART_S1_TDRE. */
1134 /*! @brief Read current value of the UART_S1_TDRE field. */
1135 #define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
1138 /*******************************************************************************
1139 * HW_UART_S2 - UART Status Register 2
1140 ******************************************************************************/
1143 * @brief HW_UART_S2 - UART Status Register 2 (RW)
1145 * Reset value: 0x00U
1147 * The S2 register provides inputs to the MCU for generation of UART interrupts
1148 * or DMA requests. Also, this register can be polled by the MCU to check the
1149 * status of these bits. This register can be read or written at any time, with the
1150 * exception of the MSBF and RXINV bits, which should be changed by the user only
1151 * between transmit and receive packets.
1153 typedef union _hw_uart_s2
1156 struct _hw_uart_s2_bitfields
1158 uint8_t RAF
: 1; /*!< [0] Receiver Active Flag */
1159 uint8_t LBKDE
: 1; /*!< [1] LIN Break Detection Enable */
1160 uint8_t BRK13
: 1; /*!< [2] Break Transmit Character Length */
1161 uint8_t RWUID
: 1; /*!< [3] Receive Wakeup Idle Detect */
1162 uint8_t RXINV
: 1; /*!< [4] Receive Data Inversion */
1163 uint8_t MSBF
: 1; /*!< [5] Most Significant Bit First */
1164 uint8_t RXEDGIF
: 1; /*!< [6] RxD Pin Active Edge Interrupt Flag */
1165 uint8_t LBKDIF
: 1; /*!< [7] LIN Break Detect Interrupt Flag */
1170 * @name Constants and macros for entire UART_S2 register
1173 #define HW_UART_S2_ADDR(x) ((x) + 0x5U)
1175 #define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x))
1176 #define HW_UART_S2_RD(x) (HW_UART_S2(x).U)
1177 #define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v))
1178 #define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v)))
1179 #define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
1180 #define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v)))
1184 * Constants & macros for individual UART_S2 bitfields
1188 * @name Register UART_S2, field RAF[0] (RO)
1190 * RAF is set when the UART receiver detects a logic 0 during the RT1 time
1191 * period of the start bit search. RAF is cleared when the receiver detects an idle
1192 * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
1193 * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
1194 * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
1195 * to configure the guard time to 12. However, if a NACK is required to be
1196 * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
1197 * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
1198 * prior to actually being inactive.
1201 * - 0 - UART receiver idle/inactive waiting for a start bit.
1202 * - 1 - UART receiver active, RxD input not idle.
1205 #define BP_UART_S2_RAF (0U) /*!< Bit position for UART_S2_RAF. */
1206 #define BM_UART_S2_RAF (0x01U) /*!< Bit mask for UART_S2_RAF. */
1207 #define BS_UART_S2_RAF (1U) /*!< Bit field size in bits for UART_S2_RAF. */
1209 /*! @brief Read current value of the UART_S2_RAF field. */
1210 #define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
1214 * @name Register UART_S2, field LBKDE[1] (RW)
1216 * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
1217 * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
1218 * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
1221 * - 0 - Break character detection is disabled.
1222 * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
1223 * 12 bits time if C1[M] = 1.
1226 #define BP_UART_S2_LBKDE (1U) /*!< Bit position for UART_S2_LBKDE. */
1227 #define BM_UART_S2_LBKDE (0x02U) /*!< Bit mask for UART_S2_LBKDE. */
1228 #define BS_UART_S2_LBKDE (1U) /*!< Bit field size in bits for UART_S2_LBKDE. */
1230 /*! @brief Read current value of the UART_S2_LBKDE field. */
1231 #define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
1233 /*! @brief Format value for bitfield UART_S2_LBKDE. */
1234 #define BF_UART_S2_LBKDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE)
1236 /*! @brief Set the LBKDE field to a new value. */
1237 #define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
1241 * @name Register UART_S2, field BRK13[2] (RW)
1243 * Determines whether the transmit break character is 10, 11, or 12 bits long,
1244 * or 13 or 14 bits long. See for the length of the break character for the
1245 * different configurations. The detection of a framing error is not affected by this
1246 * field. Transmitting break characters
1249 * - 0 - Break character is 10, 11, or 12 bits long.
1250 * - 1 - Break character is 13 or 14 bits long.
1253 #define BP_UART_S2_BRK13 (2U) /*!< Bit position for UART_S2_BRK13. */
1254 #define BM_UART_S2_BRK13 (0x04U) /*!< Bit mask for UART_S2_BRK13. */
1255 #define BS_UART_S2_BRK13 (1U) /*!< Bit field size in bits for UART_S2_BRK13. */
1257 /*! @brief Read current value of the UART_S2_BRK13 field. */
1258 #define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
1260 /*! @brief Format value for bitfield UART_S2_BRK13. */
1261 #define BF_UART_S2_BRK13(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13)
1263 /*! @brief Set the BRK13 field to a new value. */
1264 #define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
1268 * @name Register UART_S2, field RWUID[3] (RW)
1270 * When RWU is set and WAKE is cleared, this field controls whether the idle
1271 * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
1272 * C7816[ISO7816E] is set/enabled.
1275 * - 0 - S1[IDLE] is not set upon detection of an idle character.
1276 * - 1 - S1[IDLE] is set upon detection of an idle character.
1279 #define BP_UART_S2_RWUID (3U) /*!< Bit position for UART_S2_RWUID. */
1280 #define BM_UART_S2_RWUID (0x08U) /*!< Bit mask for UART_S2_RWUID. */
1281 #define BS_UART_S2_RWUID (1U) /*!< Bit field size in bits for UART_S2_RWUID. */
1283 /*! @brief Read current value of the UART_S2_RWUID field. */
1284 #define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
1286 /*! @brief Format value for bitfield UART_S2_RWUID. */
1287 #define BF_UART_S2_RWUID(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID)
1289 /*! @brief Set the RWUID field to a new value. */
1290 #define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
1294 * @name Register UART_S2, field RXINV[4] (RW)
1296 * Setting this field reverses the polarity of the received data input. In NRZ
1297 * format, a one is represented by a mark and a zero is represented by a space for
1298 * normal polarity, and the opposite for inverted polarity. In IrDA format, a
1299 * zero is represented by short high pulse in the middle of a bit time remaining
1300 * idle low for a one for normal polarity. A zero is represented by a short low
1301 * pulse in the middle of a bit time remaining idle high for a one for inverted
1302 * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
1303 * enabled and an initial character is detected in T = 0 protocol mode. Setting
1304 * RXINV inverts the RxD input for data bits, start and stop bits, break, and
1305 * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
1309 * - 0 - Receive data is not inverted.
1310 * - 1 - Receive data is inverted.
1313 #define BP_UART_S2_RXINV (4U) /*!< Bit position for UART_S2_RXINV. */
1314 #define BM_UART_S2_RXINV (0x10U) /*!< Bit mask for UART_S2_RXINV. */
1315 #define BS_UART_S2_RXINV (1U) /*!< Bit field size in bits for UART_S2_RXINV. */
1317 /*! @brief Read current value of the UART_S2_RXINV field. */
1318 #define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
1320 /*! @brief Format value for bitfield UART_S2_RXINV. */
1321 #define BF_UART_S2_RXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV)
1323 /*! @brief Set the RXINV field to a new value. */
1324 #define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
1328 * @name Register UART_S2, field MSBF[5] (RW)
1330 * Setting this field reverses the order of the bits that are transmitted and
1331 * received on the wire. This field does not affect the polarity of the bits, the
1332 * location of the parity bit, or the location of the start or stop bits. This
1333 * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
1334 * an initial character is detected in T = 0 protocol mode.
1337 * - 0 - LSB (bit0) is the first bit that is transmitted following the start
1338 * bit. Further, the first bit received after the start bit is identified as
1340 * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
1341 * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
1342 * first bit received after the start bit is identified as bit8, bit7, or
1343 * bit6, depending on the setting of C1[M] and C1[PE].
1346 #define BP_UART_S2_MSBF (5U) /*!< Bit position for UART_S2_MSBF. */
1347 #define BM_UART_S2_MSBF (0x20U) /*!< Bit mask for UART_S2_MSBF. */
1348 #define BS_UART_S2_MSBF (1U) /*!< Bit field size in bits for UART_S2_MSBF. */
1350 /*! @brief Read current value of the UART_S2_MSBF field. */
1351 #define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
1353 /*! @brief Format value for bitfield UART_S2_MSBF. */
1354 #define BF_UART_S2_MSBF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF)
1356 /*! @brief Set the MSBF field to a new value. */
1357 #define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
1361 * @name Register UART_S2, field RXEDGIF[6] (W1C)
1363 * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
1364 * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
1365 * to it. See for additional details. RXEDGIF description The active edge is
1366 * detected only in two wire mode and on receiving data coming from the RxD pin.
1369 * - 0 - No active edge on the receive pin has occurred.
1370 * - 1 - An active edge on the receive pin has occurred.
1373 #define BP_UART_S2_RXEDGIF (6U) /*!< Bit position for UART_S2_RXEDGIF. */
1374 #define BM_UART_S2_RXEDGIF (0x40U) /*!< Bit mask for UART_S2_RXEDGIF. */
1375 #define BS_UART_S2_RXEDGIF (1U) /*!< Bit field size in bits for UART_S2_RXEDGIF. */
1377 /*! @brief Read current value of the UART_S2_RXEDGIF field. */
1378 #define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
1380 /*! @brief Format value for bitfield UART_S2_RXEDGIF. */
1381 #define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF)
1383 /*! @brief Set the RXEDGIF field to a new value. */
1384 #define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
1388 * @name Register UART_S2, field LBKDIF[7] (W1C)
1390 * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
1391 * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
1392 * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
1393 * last LIN break character. LBKDIF is cleared by writing a 1 to it.
1396 * - 0 - No LIN break character detected.
1397 * - 1 - LIN break character detected.
1400 #define BP_UART_S2_LBKDIF (7U) /*!< Bit position for UART_S2_LBKDIF. */
1401 #define BM_UART_S2_LBKDIF (0x80U) /*!< Bit mask for UART_S2_LBKDIF. */
1402 #define BS_UART_S2_LBKDIF (1U) /*!< Bit field size in bits for UART_S2_LBKDIF. */
1404 /*! @brief Read current value of the UART_S2_LBKDIF field. */
1405 #define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
1407 /*! @brief Format value for bitfield UART_S2_LBKDIF. */
1408 #define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF)
1410 /*! @brief Set the LBKDIF field to a new value. */
1411 #define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
1414 /*******************************************************************************
1415 * HW_UART_C3 - UART Control Register 3
1416 ******************************************************************************/
1419 * @brief HW_UART_C3 - UART Control Register 3 (RW)
1421 * Reset value: 0x00U
1423 * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
1424 * between transmit and receive packets.
1426 typedef union _hw_uart_c3
1429 struct _hw_uart_c3_bitfields
1431 uint8_t PEIE
: 1; /*!< [0] Parity Error Interrupt Enable */
1432 uint8_t FEIE
: 1; /*!< [1] Framing Error Interrupt Enable */
1433 uint8_t NEIE
: 1; /*!< [2] Noise Error Interrupt Enable */
1434 uint8_t ORIE
: 1; /*!< [3] Overrun Error Interrupt Enable */
1435 uint8_t TXINV
: 1; /*!< [4] Transmit Data Inversion. */
1436 uint8_t TXDIR
: 1; /*!< [5] Transmitter Pin Data Direction in
1437 * Single-Wire mode */
1438 uint8_t T8
: 1; /*!< [6] Transmit Bit 8 */
1439 uint8_t R8
: 1; /*!< [7] Received Bit 8 */
1444 * @name Constants and macros for entire UART_C3 register
1447 #define HW_UART_C3_ADDR(x) ((x) + 0x6U)
1449 #define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x))
1450 #define HW_UART_C3_RD(x) (HW_UART_C3(x).U)
1451 #define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v))
1452 #define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v)))
1453 #define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
1454 #define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v)))
1458 * Constants & macros for individual UART_C3 bitfields
1462 * @name Register UART_C3, field PEIE[0] (RW)
1464 * Enables the parity error flag, S1[PF], to generate interrupt requests.
1467 * - 0 - PF interrupt requests are disabled.
1468 * - 1 - PF interrupt requests are enabled.
1471 #define BP_UART_C3_PEIE (0U) /*!< Bit position for UART_C3_PEIE. */
1472 #define BM_UART_C3_PEIE (0x01U) /*!< Bit mask for UART_C3_PEIE. */
1473 #define BS_UART_C3_PEIE (1U) /*!< Bit field size in bits for UART_C3_PEIE. */
1475 /*! @brief Read current value of the UART_C3_PEIE field. */
1476 #define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
1478 /*! @brief Format value for bitfield UART_C3_PEIE. */
1479 #define BF_UART_C3_PEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE)
1481 /*! @brief Set the PEIE field to a new value. */
1482 #define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
1486 * @name Register UART_C3, field FEIE[1] (RW)
1488 * Enables the framing error flag, S1[FE], to generate interrupt requests.
1491 * - 0 - FE interrupt requests are disabled.
1492 * - 1 - FE interrupt requests are enabled.
1495 #define BP_UART_C3_FEIE (1U) /*!< Bit position for UART_C3_FEIE. */
1496 #define BM_UART_C3_FEIE (0x02U) /*!< Bit mask for UART_C3_FEIE. */
1497 #define BS_UART_C3_FEIE (1U) /*!< Bit field size in bits for UART_C3_FEIE. */
1499 /*! @brief Read current value of the UART_C3_FEIE field. */
1500 #define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
1502 /*! @brief Format value for bitfield UART_C3_FEIE. */
1503 #define BF_UART_C3_FEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE)
1505 /*! @brief Set the FEIE field to a new value. */
1506 #define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
1510 * @name Register UART_C3, field NEIE[2] (RW)
1512 * Enables the noise flag, S1[NF], to generate interrupt requests.
1515 * - 0 - NF interrupt requests are disabled.
1516 * - 1 - NF interrupt requests are enabled.
1519 #define BP_UART_C3_NEIE (2U) /*!< Bit position for UART_C3_NEIE. */
1520 #define BM_UART_C3_NEIE (0x04U) /*!< Bit mask for UART_C3_NEIE. */
1521 #define BS_UART_C3_NEIE (1U) /*!< Bit field size in bits for UART_C3_NEIE. */
1523 /*! @brief Read current value of the UART_C3_NEIE field. */
1524 #define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
1526 /*! @brief Format value for bitfield UART_C3_NEIE. */
1527 #define BF_UART_C3_NEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE)
1529 /*! @brief Set the NEIE field to a new value. */
1530 #define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
1534 * @name Register UART_C3, field ORIE[3] (RW)
1536 * Enables the overrun error flag, S1[OR], to generate interrupt requests.
1539 * - 0 - OR interrupts are disabled.
1540 * - 1 - OR interrupt requests are enabled.
1543 #define BP_UART_C3_ORIE (3U) /*!< Bit position for UART_C3_ORIE. */
1544 #define BM_UART_C3_ORIE (0x08U) /*!< Bit mask for UART_C3_ORIE. */
1545 #define BS_UART_C3_ORIE (1U) /*!< Bit field size in bits for UART_C3_ORIE. */
1547 /*! @brief Read current value of the UART_C3_ORIE field. */
1548 #define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
1550 /*! @brief Format value for bitfield UART_C3_ORIE. */
1551 #define BF_UART_C3_ORIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE)
1553 /*! @brief Set the ORIE field to a new value. */
1554 #define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
1558 * @name Register UART_C3, field TXINV[4] (RW)
1560 * Setting this field reverses the polarity of the transmitted data output. In
1561 * NRZ format, a one is represented by a mark and a zero is represented by a space
1562 * for normal polarity, and the opposite for inverted polarity. In IrDA format,
1563 * a zero is represented by short high pulse in the middle of a bit time
1564 * remaining idle low for a one for normal polarity, and a zero is represented by short
1565 * low pulse in the middle of a bit time remaining idle high for a one for
1566 * inverted polarity. This field is automatically set when C7816[INIT] and
1567 * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
1568 * Setting TXINV inverts all transmitted values, including idle, break, start, and
1569 * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
1570 * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
1571 * the transmitted data bits and parity bit are inverted.
1574 * - 0 - Transmit data is not inverted.
1575 * - 1 - Transmit data is inverted.
1578 #define BP_UART_C3_TXINV (4U) /*!< Bit position for UART_C3_TXINV. */
1579 #define BM_UART_C3_TXINV (0x10U) /*!< Bit mask for UART_C3_TXINV. */
1580 #define BS_UART_C3_TXINV (1U) /*!< Bit field size in bits for UART_C3_TXINV. */
1582 /*! @brief Read current value of the UART_C3_TXINV field. */
1583 #define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
1585 /*! @brief Format value for bitfield UART_C3_TXINV. */
1586 #define BF_UART_C3_TXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV)
1588 /*! @brief Set the TXINV field to a new value. */
1589 #define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
1593 * @name Register UART_C3, field TXDIR[5] (RW)
1595 * Determines whether the TXD pin is used as an input or output in the
1596 * single-wire mode of operation. This field is relevant only to the single wire mode.
1597 * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
1598 * automatically cleared after the requested block is transmitted. This condition is
1599 * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
1600 * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
1601 * being transmitted, the hardware automatically overrides this field as needed. In
1602 * this situation, TXDIR does not reflect the temporary state associated with
1606 * - 0 - TXD pin is an input in single wire mode.
1607 * - 1 - TXD pin is an output in single wire mode.
1610 #define BP_UART_C3_TXDIR (5U) /*!< Bit position for UART_C3_TXDIR. */
1611 #define BM_UART_C3_TXDIR (0x20U) /*!< Bit mask for UART_C3_TXDIR. */
1612 #define BS_UART_C3_TXDIR (1U) /*!< Bit field size in bits for UART_C3_TXDIR. */
1614 /*! @brief Read current value of the UART_C3_TXDIR field. */
1615 #define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
1617 /*! @brief Format value for bitfield UART_C3_TXDIR. */
1618 #define BF_UART_C3_TXDIR(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR)
1620 /*! @brief Set the TXDIR field to a new value. */
1621 #define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
1625 * @name Register UART_C3, field T8[6] (RW)
1627 * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
1628 * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
1629 * same as in the previous transmission, T8 does not have to be rewritten. The same
1630 * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
1631 * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
1632 * the remaining data.
1635 #define BP_UART_C3_T8 (6U) /*!< Bit position for UART_C3_T8. */
1636 #define BM_UART_C3_T8 (0x40U) /*!< Bit mask for UART_C3_T8. */
1637 #define BS_UART_C3_T8 (1U) /*!< Bit field size in bits for UART_C3_T8. */
1639 /*! @brief Read current value of the UART_C3_T8 field. */
1640 #define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
1642 /*! @brief Format value for bitfield UART_C3_T8. */
1643 #define BF_UART_C3_T8(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8)
1645 /*! @brief Set the T8 field to a new value. */
1646 #define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
1650 * @name Register UART_C3, field R8[7] (RO)
1652 * R8 is the ninth data bit received when the UART is configured for 9-bit data
1653 * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
1654 * current data value in the UARTx_D register. To read the 9th bit, read the
1655 * value of UARTx_C3[R8], then read the UARTx_D register.
1658 #define BP_UART_C3_R8 (7U) /*!< Bit position for UART_C3_R8. */
1659 #define BM_UART_C3_R8 (0x80U) /*!< Bit mask for UART_C3_R8. */
1660 #define BS_UART_C3_R8 (1U) /*!< Bit field size in bits for UART_C3_R8. */
1662 /*! @brief Read current value of the UART_C3_R8 field. */
1663 #define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
1666 /*******************************************************************************
1667 * HW_UART_D - UART Data Register
1668 ******************************************************************************/
1671 * @brief HW_UART_D - UART Data Register (RW)
1673 * Reset value: 0x00U
1675 * This register is actually two separate registers. Reads return the contents
1676 * of the read-only receive data register and writes go to the write-only transmit
1677 * data register. In 8-bit or 9-bit data format, only UART data register (D)
1678 * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
1679 * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
1680 * register, only if the ninth bit of data needs to be captured. Similarly, the
1681 * ED register needs to be read, prior to the D register, only if the additional
1682 * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
1683 * bit cleared) if the parity is enabled, you get seven data bits and one parity
1684 * bit. That one parity bit is loaded into the D register. So, for the data bits,
1685 * mask off the parity bit from the value you read out of this register. When
1686 * transmitting in 9-bit data format and using 8-bit write instructions, write first
1687 * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
1688 * C3[T8] stores the data in a temporary register. If D register is written first,
1689 * and then the new data on data bus is stored in D, the temporary value written by
1690 * the last write to C3[T8] gets stored in the C3[T8] register.
1692 typedef union _hw_uart_d
1695 struct _hw_uart_d_bitfields
1697 uint8_t RT
: 8; /*!< [7:0] */
1702 * @name Constants and macros for entire UART_D register
1705 #define HW_UART_D_ADDR(x) ((x) + 0x7U)
1707 #define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x))
1708 #define HW_UART_D_RD(x) (HW_UART_D(x).U)
1709 #define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v))
1710 #define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v)))
1711 #define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
1712 #define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v)))
1716 * Constants & macros for individual UART_D bitfields
1720 * @name Register UART_D, field RT[7:0] (RW)
1722 * Reads return the contents of the read-only receive data register and writes
1723 * go to the write-only transmit data register.
1726 #define BP_UART_D_RT (0U) /*!< Bit position for UART_D_RT. */
1727 #define BM_UART_D_RT (0xFFU) /*!< Bit mask for UART_D_RT. */
1728 #define BS_UART_D_RT (8U) /*!< Bit field size in bits for UART_D_RT. */
1730 /*! @brief Read current value of the UART_D_RT field. */
1731 #define BR_UART_D_RT(x) (HW_UART_D(x).U)
1733 /*! @brief Format value for bitfield UART_D_RT. */
1734 #define BF_UART_D_RT(v) ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT)
1736 /*! @brief Set the RT field to a new value. */
1737 #define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v))
1740 /*******************************************************************************
1741 * HW_UART_MA1 - UART Match Address Registers 1
1742 ******************************************************************************/
1745 * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
1747 * Reset value: 0x00U
1749 * The MA1 and MA2 registers are compared to input data addresses when the most
1750 * significant bit is set and the associated C4[MAEN] field is set. If a match
1751 * occurs, the following data is transferred to the data register. If a match
1752 * fails, the following data is discarded. These registers can be read and written at
1755 typedef union _hw_uart_ma1
1758 struct _hw_uart_ma1_bitfields
1760 uint8_t MA
: 8; /*!< [7:0] Match Address */
1765 * @name Constants and macros for entire UART_MA1 register
1768 #define HW_UART_MA1_ADDR(x) ((x) + 0x8U)
1770 #define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x))
1771 #define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U)
1772 #define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v))
1773 #define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v)))
1774 #define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
1775 #define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v)))
1779 * Constants & macros for individual UART_MA1 bitfields
1783 * @name Register UART_MA1, field MA[7:0] (RW)
1786 #define BP_UART_MA1_MA (0U) /*!< Bit position for UART_MA1_MA. */
1787 #define BM_UART_MA1_MA (0xFFU) /*!< Bit mask for UART_MA1_MA. */
1788 #define BS_UART_MA1_MA (8U) /*!< Bit field size in bits for UART_MA1_MA. */
1790 /*! @brief Read current value of the UART_MA1_MA field. */
1791 #define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U)
1793 /*! @brief Format value for bitfield UART_MA1_MA. */
1794 #define BF_UART_MA1_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA)
1796 /*! @brief Set the MA field to a new value. */
1797 #define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
1800 /*******************************************************************************
1801 * HW_UART_MA2 - UART Match Address Registers 2
1802 ******************************************************************************/
1805 * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
1807 * Reset value: 0x00U
1809 * These registers can be read and written at anytime. The MA1 and MA2 registers
1810 * are compared to input data addresses when the most significant bit is set and
1811 * the associated C4[MAEN] field is set. If a match occurs, the following data
1812 * is transferred to the data register. If a match fails, the following data is
1815 typedef union _hw_uart_ma2
1818 struct _hw_uart_ma2_bitfields
1820 uint8_t MA
: 8; /*!< [7:0] Match Address */
1825 * @name Constants and macros for entire UART_MA2 register
1828 #define HW_UART_MA2_ADDR(x) ((x) + 0x9U)
1830 #define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x))
1831 #define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U)
1832 #define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v))
1833 #define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v)))
1834 #define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
1835 #define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v)))
1839 * Constants & macros for individual UART_MA2 bitfields
1843 * @name Register UART_MA2, field MA[7:0] (RW)
1846 #define BP_UART_MA2_MA (0U) /*!< Bit position for UART_MA2_MA. */
1847 #define BM_UART_MA2_MA (0xFFU) /*!< Bit mask for UART_MA2_MA. */
1848 #define BS_UART_MA2_MA (8U) /*!< Bit field size in bits for UART_MA2_MA. */
1850 /*! @brief Read current value of the UART_MA2_MA field. */
1851 #define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U)
1853 /*! @brief Format value for bitfield UART_MA2_MA. */
1854 #define BF_UART_MA2_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA)
1856 /*! @brief Set the MA field to a new value. */
1857 #define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
1860 /*******************************************************************************
1861 * HW_UART_C4 - UART Control Register 4
1862 ******************************************************************************/
1865 * @brief HW_UART_C4 - UART Control Register 4 (RW)
1867 * Reset value: 0x00U
1869 typedef union _hw_uart_c4
1872 struct _hw_uart_c4_bitfields
1874 uint8_t BRFA
: 5; /*!< [4:0] Baud Rate Fine Adjust */
1875 uint8_t M10
: 1; /*!< [5] 10-bit Mode select */
1876 uint8_t MAEN2
: 1; /*!< [6] Match Address Mode Enable 2 */
1877 uint8_t MAEN1
: 1; /*!< [7] Match Address Mode Enable 1 */
1882 * @name Constants and macros for entire UART_C4 register
1885 #define HW_UART_C4_ADDR(x) ((x) + 0xAU)
1887 #define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x))
1888 #define HW_UART_C4_RD(x) (HW_UART_C4(x).U)
1889 #define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v))
1890 #define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v)))
1891 #define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
1892 #define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v)))
1896 * Constants & macros for individual UART_C4 bitfields
1900 * @name Register UART_C4, field BRFA[4:0] (RW)
1902 * This bit field is used to add more timing resolution to the average baud
1903 * frequency, in increments of 1/32. See Baud rate generation for more information.
1906 #define BP_UART_C4_BRFA (0U) /*!< Bit position for UART_C4_BRFA. */
1907 #define BM_UART_C4_BRFA (0x1FU) /*!< Bit mask for UART_C4_BRFA. */
1908 #define BS_UART_C4_BRFA (5U) /*!< Bit field size in bits for UART_C4_BRFA. */
1910 /*! @brief Read current value of the UART_C4_BRFA field. */
1911 #define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA)
1913 /*! @brief Format value for bitfield UART_C4_BRFA. */
1914 #define BF_UART_C4_BRFA(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA)
1916 /*! @brief Set the BRFA field to a new value. */
1917 #define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v)))
1921 * @name Register UART_C4, field M10[5] (RW)
1923 * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
1924 * This tenth bit is generated and interpreted as a parity bit. The M10 field
1925 * does not affect the LIN send or detect break behavior. If M10 is set, then both
1926 * C1[M] and C1[PE] must also be set. This field must be cleared when
1927 * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
1930 * - 0 - The parity bit is the ninth bit in the serial transmission.
1931 * - 1 - The parity bit is the tenth bit in the serial transmission.
1934 #define BP_UART_C4_M10 (5U) /*!< Bit position for UART_C4_M10. */
1935 #define BM_UART_C4_M10 (0x20U) /*!< Bit mask for UART_C4_M10. */
1936 #define BS_UART_C4_M10 (1U) /*!< Bit field size in bits for UART_C4_M10. */
1938 /*! @brief Read current value of the UART_C4_M10 field. */
1939 #define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
1941 /*! @brief Format value for bitfield UART_C4_M10. */
1942 #define BF_UART_C4_M10(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10)
1944 /*! @brief Set the M10 field to a new value. */
1945 #define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
1949 * @name Register UART_C4, field MAEN2[6] (RW)
1951 * See Match address operation for more information.
1954 * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
1955 * - 1 - All data received with the most significant bit cleared, is discarded.
1956 * All data received with the most significant bit set, is compared with
1957 * contents of MA2 register. If no match occurs, the data is discarded. If a
1958 * match occurs, data is transferred to the data buffer. This field must be
1959 * cleared when C7816[ISO7816E] is set/enabled.
1962 #define BP_UART_C4_MAEN2 (6U) /*!< Bit position for UART_C4_MAEN2. */
1963 #define BM_UART_C4_MAEN2 (0x40U) /*!< Bit mask for UART_C4_MAEN2. */
1964 #define BS_UART_C4_MAEN2 (1U) /*!< Bit field size in bits for UART_C4_MAEN2. */
1966 /*! @brief Read current value of the UART_C4_MAEN2 field. */
1967 #define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
1969 /*! @brief Format value for bitfield UART_C4_MAEN2. */
1970 #define BF_UART_C4_MAEN2(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2)
1972 /*! @brief Set the MAEN2 field to a new value. */
1973 #define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
1977 * @name Register UART_C4, field MAEN1[7] (RW)
1979 * See Match address operation for more information.
1982 * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
1983 * - 1 - All data received with the most significant bit cleared, is discarded.
1984 * All data received with the most significant bit set, is compared with
1985 * contents of MA1 register. If no match occurs, the data is discarded. If match
1986 * occurs, data is transferred to the data buffer. This field must be cleared
1987 * when C7816[ISO7816E] is set/enabled.
1990 #define BP_UART_C4_MAEN1 (7U) /*!< Bit position for UART_C4_MAEN1. */
1991 #define BM_UART_C4_MAEN1 (0x80U) /*!< Bit mask for UART_C4_MAEN1. */
1992 #define BS_UART_C4_MAEN1 (1U) /*!< Bit field size in bits for UART_C4_MAEN1. */
1994 /*! @brief Read current value of the UART_C4_MAEN1 field. */
1995 #define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
1997 /*! @brief Format value for bitfield UART_C4_MAEN1. */
1998 #define BF_UART_C4_MAEN1(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1)
2000 /*! @brief Set the MAEN1 field to a new value. */
2001 #define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
2004 /*******************************************************************************
2005 * HW_UART_C5 - UART Control Register 5
2006 ******************************************************************************/
2009 * @brief HW_UART_C5 - UART Control Register 5 (RW)
2011 * Reset value: 0x00U
2013 typedef union _hw_uart_c5
2016 struct _hw_uart_c5_bitfields
2018 uint8_t RESERVED0
: 5; /*!< [4:0] */
2019 uint8_t RDMAS
: 1; /*!< [5] Receiver Full DMA Select */
2020 uint8_t RESERVED1
: 1; /*!< [6] */
2021 uint8_t TDMAS
: 1; /*!< [7] Transmitter DMA Select */
2026 * @name Constants and macros for entire UART_C5 register
2029 #define HW_UART_C5_ADDR(x) ((x) + 0xBU)
2031 #define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x))
2032 #define HW_UART_C5_RD(x) (HW_UART_C5(x).U)
2033 #define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v))
2034 #define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v)))
2035 #define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
2036 #define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v)))
2040 * Constants & macros for individual UART_C5 bitfields
2044 * @name Register UART_C5, field RDMAS[5] (RW)
2046 * Configures the receiver data register full flag, S1[RDRF], to generate
2047 * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
2048 * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
2049 * regardless of the state of RDMAS.
2052 * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
2053 * asserted to request an interrupt service.
2054 * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
2055 * asserted to request a DMA transfer.
2058 #define BP_UART_C5_RDMAS (5U) /*!< Bit position for UART_C5_RDMAS. */
2059 #define BM_UART_C5_RDMAS (0x20U) /*!< Bit mask for UART_C5_RDMAS. */
2060 #define BS_UART_C5_RDMAS (1U) /*!< Bit field size in bits for UART_C5_RDMAS. */
2062 /*! @brief Read current value of the UART_C5_RDMAS field. */
2063 #define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
2065 /*! @brief Format value for bitfield UART_C5_RDMAS. */
2066 #define BF_UART_C5_RDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS)
2068 /*! @brief Set the RDMAS field to a new value. */
2069 #define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
2073 * @name Register UART_C5, field TDMAS[7] (RW)
2075 * Configures the transmit data register empty flag, S1[TDRE], to generate
2076 * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
2077 * TDRE interrupt request signals are not asserted when the TDRE flag is set,
2078 * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
2079 * must be cleared, and D must not be written unless a DMA request is being
2083 * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
2084 * request signal is asserted to request interrupt service.
2085 * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
2086 * signal is asserted to request a DMA transfer.
2089 #define BP_UART_C5_TDMAS (7U) /*!< Bit position for UART_C5_TDMAS. */
2090 #define BM_UART_C5_TDMAS (0x80U) /*!< Bit mask for UART_C5_TDMAS. */
2091 #define BS_UART_C5_TDMAS (1U) /*!< Bit field size in bits for UART_C5_TDMAS. */
2093 /*! @brief Read current value of the UART_C5_TDMAS field. */
2094 #define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
2096 /*! @brief Format value for bitfield UART_C5_TDMAS. */
2097 #define BF_UART_C5_TDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS)
2099 /*! @brief Set the TDMAS field to a new value. */
2100 #define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
2103 /*******************************************************************************
2104 * HW_UART_ED - UART Extended Data Register
2105 ******************************************************************************/
2108 * @brief HW_UART_ED - UART Extended Data Register (RO)
2110 * Reset value: 0x00U
2112 * This register contains additional information flags that are stored with a
2113 * received dataword. This register may be read at any time but contains valid data
2114 * only if there is a dataword in the receive FIFO. The data contained in this
2115 * register represents additional information regarding the conditions on which a
2116 * dataword was received. The importance of this data varies with the
2117 * application, and in some cases maybe completely optional. These fields automatically
2118 * update to reflect the conditions of the next dataword whenever D is read. If
2119 * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
2120 * empty, the NOISY and PARITYE fields will be zero.
2122 typedef union _hw_uart_ed
2125 struct _hw_uart_ed_bitfields
2127 uint8_t RESERVED0
: 6; /*!< [5:0] */
2128 uint8_t PARITYE
: 1; /*!< [6] */
2129 uint8_t NOISY
: 1; /*!< [7] */
2134 * @name Constants and macros for entire UART_ED register
2137 #define HW_UART_ED_ADDR(x) ((x) + 0xCU)
2139 #define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x))
2140 #define HW_UART_ED_RD(x) (HW_UART_ED(x).U)
2144 * Constants & macros for individual UART_ED bitfields
2148 * @name Register UART_ED, field PARITYE[6] (RO)
2150 * The current received dataword contained in D and C3[R8] was received with a
2154 * - 0 - The dataword was received without a parity error.
2155 * - 1 - The dataword was received with a parity error.
2158 #define BP_UART_ED_PARITYE (6U) /*!< Bit position for UART_ED_PARITYE. */
2159 #define BM_UART_ED_PARITYE (0x40U) /*!< Bit mask for UART_ED_PARITYE. */
2160 #define BS_UART_ED_PARITYE (1U) /*!< Bit field size in bits for UART_ED_PARITYE. */
2162 /*! @brief Read current value of the UART_ED_PARITYE field. */
2163 #define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
2167 * @name Register UART_ED, field NOISY[7] (RO)
2169 * The current received dataword contained in D and C3[R8] was received with
2173 * - 0 - The dataword was received without noise.
2174 * - 1 - The data was received with noise.
2177 #define BP_UART_ED_NOISY (7U) /*!< Bit position for UART_ED_NOISY. */
2178 #define BM_UART_ED_NOISY (0x80U) /*!< Bit mask for UART_ED_NOISY. */
2179 #define BS_UART_ED_NOISY (1U) /*!< Bit field size in bits for UART_ED_NOISY. */
2181 /*! @brief Read current value of the UART_ED_NOISY field. */
2182 #define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
2185 /*******************************************************************************
2186 * HW_UART_MODEM - UART Modem Register
2187 ******************************************************************************/
2190 * @brief HW_UART_MODEM - UART Modem Register (RW)
2192 * Reset value: 0x00U
2194 * The MODEM register controls options for setting the modem configuration.
2195 * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
2196 * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
2197 * ISO-7816 protocol does not use the RTS and CTS signals.
2199 typedef union _hw_uart_modem
2202 struct _hw_uart_modem_bitfields
2204 uint8_t TXCTSE
: 1; /*!< [0] Transmitter clear-to-send enable */
2205 uint8_t TXRTSE
: 1; /*!< [1] Transmitter request-to-send enable */
2206 uint8_t TXRTSPOL
: 1; /*!< [2] Transmitter request-to-send polarity */
2207 uint8_t RXRTSE
: 1; /*!< [3] Receiver request-to-send enable */
2208 uint8_t RESERVED0
: 4; /*!< [7:4] */
2213 * @name Constants and macros for entire UART_MODEM register
2216 #define HW_UART_MODEM_ADDR(x) ((x) + 0xDU)
2218 #define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x))
2219 #define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U)
2220 #define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v))
2221 #define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v)))
2222 #define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
2223 #define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v)))
2227 * Constants & macros for individual UART_MODEM bitfields
2231 * @name Register UART_MODEM, field TXCTSE[0] (RW)
2233 * TXCTSE controls the operation of the transmitter. TXCTSE can be set
2234 * independently from the state of TXRTSE and RXRTSE.
2237 * - 0 - CTS has no effect on the transmitter.
2238 * - 1 - Enables clear-to-send operation. The transmitter checks the state of
2239 * CTS each time it is ready to send a character. If CTS is asserted, the
2240 * character is sent. If CTS is deasserted, the signal TXD remains in the mark
2241 * state and transmission is delayed until CTS is asserted. Changes in CTS as a
2242 * character is being sent do not affect its transmission.
2245 #define BP_UART_MODEM_TXCTSE (0U) /*!< Bit position for UART_MODEM_TXCTSE. */
2246 #define BM_UART_MODEM_TXCTSE (0x01U) /*!< Bit mask for UART_MODEM_TXCTSE. */
2247 #define BS_UART_MODEM_TXCTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXCTSE. */
2249 /*! @brief Read current value of the UART_MODEM_TXCTSE field. */
2250 #define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
2252 /*! @brief Format value for bitfield UART_MODEM_TXCTSE. */
2253 #define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE)
2255 /*! @brief Set the TXCTSE field to a new value. */
2256 #define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
2260 * @name Register UART_MODEM, field TXRTSE[1] (RW)
2262 * Controls RTS before and after a transmission.
2265 * - 0 - The transmitter has no effect on RTS.
2266 * - 1 - When a character is placed into an empty transmitter data buffer , RTS
2267 * asserts one bit time before the start bit is transmitted. RTS deasserts
2268 * one bit time after all characters in the transmitter data buffer and shift
2269 * register are completely sent, including the last stop bit. (FIFO) (FIFO)
2272 #define BP_UART_MODEM_TXRTSE (1U) /*!< Bit position for UART_MODEM_TXRTSE. */
2273 #define BM_UART_MODEM_TXRTSE (0x02U) /*!< Bit mask for UART_MODEM_TXRTSE. */
2274 #define BS_UART_MODEM_TXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSE. */
2276 /*! @brief Read current value of the UART_MODEM_TXRTSE field. */
2277 #define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
2279 /*! @brief Format value for bitfield UART_MODEM_TXRTSE. */
2280 #define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE)
2282 /*! @brief Set the TXRTSE field to a new value. */
2283 #define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
2287 * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
2289 * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
2290 * polarity of the receiver RTS. RTS will remain negated in the active low state
2291 * unless TXRTSE is set.
2294 * - 0 - Transmitter RTS is active low.
2295 * - 1 - Transmitter RTS is active high.
2298 #define BP_UART_MODEM_TXRTSPOL (2U) /*!< Bit position for UART_MODEM_TXRTSPOL. */
2299 #define BM_UART_MODEM_TXRTSPOL (0x04U) /*!< Bit mask for UART_MODEM_TXRTSPOL. */
2300 #define BS_UART_MODEM_TXRTSPOL (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSPOL. */
2302 /*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
2303 #define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
2305 /*! @brief Format value for bitfield UART_MODEM_TXRTSPOL. */
2306 #define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL)
2308 /*! @brief Set the TXRTSPOL field to a new value. */
2309 #define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
2313 * @name Register UART_MODEM, field RXRTSE[3] (RW)
2315 * Allows the RTS output to control the CTS input of the transmitting device to
2316 * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
2319 * - 0 - The receiver has no effect on RTS.
2320 * - 1 - RTS is deasserted if the number of characters in the receiver data
2321 * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
2322 * when the number of characters in the receiver data register (FIFO) is less
2323 * than RWFIFO[RXWATER].
2326 #define BP_UART_MODEM_RXRTSE (3U) /*!< Bit position for UART_MODEM_RXRTSE. */
2327 #define BM_UART_MODEM_RXRTSE (0x08U) /*!< Bit mask for UART_MODEM_RXRTSE. */
2328 #define BS_UART_MODEM_RXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_RXRTSE. */
2330 /*! @brief Read current value of the UART_MODEM_RXRTSE field. */
2331 #define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
2333 /*! @brief Format value for bitfield UART_MODEM_RXRTSE. */
2334 #define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE)
2336 /*! @brief Set the RXRTSE field to a new value. */
2337 #define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
2340 /*******************************************************************************
2341 * HW_UART_IR - UART Infrared Register
2342 ******************************************************************************/
2345 * @brief HW_UART_IR - UART Infrared Register (RW)
2347 * Reset value: 0x00U
2349 * The IR register controls options for setting the infrared configuration.
2351 typedef union _hw_uart_ir
2354 struct _hw_uart_ir_bitfields
2356 uint8_t TNP
: 2; /*!< [1:0] Transmitter narrow pulse */
2357 uint8_t IREN
: 1; /*!< [2] Infrared enable */
2358 uint8_t RESERVED0
: 5; /*!< [7:3] */
2363 * @name Constants and macros for entire UART_IR register
2366 #define HW_UART_IR_ADDR(x) ((x) + 0xEU)
2368 #define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x))
2369 #define HW_UART_IR_RD(x) (HW_UART_IR(x).U)
2370 #define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v))
2371 #define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v)))
2372 #define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
2373 #define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v)))
2377 * Constants & macros for individual UART_IR bitfields
2381 * @name Register UART_IR, field TNP[1:0] (RW)
2383 * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
2392 #define BP_UART_IR_TNP (0U) /*!< Bit position for UART_IR_TNP. */
2393 #define BM_UART_IR_TNP (0x03U) /*!< Bit mask for UART_IR_TNP. */
2394 #define BS_UART_IR_TNP (2U) /*!< Bit field size in bits for UART_IR_TNP. */
2396 /*! @brief Read current value of the UART_IR_TNP field. */
2397 #define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP)
2399 /*! @brief Format value for bitfield UART_IR_TNP. */
2400 #define BF_UART_IR_TNP(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP)
2402 /*! @brief Set the TNP field to a new value. */
2403 #define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v)))
2407 * @name Register UART_IR, field IREN[2] (RW)
2409 * Enables/disables the infrared modulation/demodulation.
2412 * - 0 - IR disabled.
2416 #define BP_UART_IR_IREN (2U) /*!< Bit position for UART_IR_IREN. */
2417 #define BM_UART_IR_IREN (0x04U) /*!< Bit mask for UART_IR_IREN. */
2418 #define BS_UART_IR_IREN (1U) /*!< Bit field size in bits for UART_IR_IREN. */
2420 /*! @brief Read current value of the UART_IR_IREN field. */
2421 #define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
2423 /*! @brief Format value for bitfield UART_IR_IREN. */
2424 #define BF_UART_IR_IREN(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN)
2426 /*! @brief Set the IREN field to a new value. */
2427 #define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
2430 /*******************************************************************************
2431 * HW_UART_PFIFO - UART FIFO Parameters
2432 ******************************************************************************/
2435 * @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
2437 * Reset value: 0x00U
2439 * This register provides the ability for the programmer to turn on and off FIFO
2440 * functionality. It also provides the size of the FIFO that has been
2441 * implemented. This register may be read at any time. This register must be written only
2442 * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
2445 typedef union _hw_uart_pfifo
2448 struct _hw_uart_pfifo_bitfields
2450 uint8_t RXFIFOSIZE
: 3; /*!< [2:0] Receive FIFO. Buffer Depth */
2451 uint8_t RXFE
: 1; /*!< [3] Receive FIFO Enable */
2452 uint8_t TXFIFOSIZE
: 3; /*!< [6:4] Transmit FIFO. Buffer Depth */
2453 uint8_t TXFE
: 1; /*!< [7] Transmit FIFO Enable */
2458 * @name Constants and macros for entire UART_PFIFO register
2461 #define HW_UART_PFIFO_ADDR(x) ((x) + 0x10U)
2463 #define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x))
2464 #define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U)
2465 #define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v))
2466 #define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v)))
2467 #define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
2468 #define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v)))
2472 * Constants & macros for individual UART_PFIFO bitfields
2476 * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
2478 * The maximum number of receive datawords that can be stored in the receive
2479 * buffer before an overrun occurs. This field is read only.
2482 * - 000 - Receive FIFO/Buffer depth = 1 dataword.
2483 * - 001 - Receive FIFO/Buffer depth = 4 datawords.
2484 * - 010 - Receive FIFO/Buffer depth = 8 datawords.
2485 * - 011 - Receive FIFO/Buffer depth = 16 datawords.
2486 * - 100 - Receive FIFO/Buffer depth = 32 datawords.
2487 * - 101 - Receive FIFO/Buffer depth = 64 datawords.
2488 * - 110 - Receive FIFO/Buffer depth = 128 datawords.
2492 #define BP_UART_PFIFO_RXFIFOSIZE (0U) /*!< Bit position for UART_PFIFO_RXFIFOSIZE. */
2493 #define BM_UART_PFIFO_RXFIFOSIZE (0x07U) /*!< Bit mask for UART_PFIFO_RXFIFOSIZE. */
2494 #define BS_UART_PFIFO_RXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. */
2496 /*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
2497 #define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
2501 * @name Register UART_PFIFO, field RXFE[3] (RW)
2503 * When this field is set, the built in FIFO structure for the receive buffer is
2504 * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
2505 * If this field is not set, the receive buffer operates as a FIFO of depth one
2506 * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
2507 * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
2508 * commands must be issued immediately after changing this field.
2511 * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
2512 * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
2515 #define BP_UART_PFIFO_RXFE (3U) /*!< Bit position for UART_PFIFO_RXFE. */
2516 #define BM_UART_PFIFO_RXFE (0x08U) /*!< Bit mask for UART_PFIFO_RXFE. */
2517 #define BS_UART_PFIFO_RXFE (1U) /*!< Bit field size in bits for UART_PFIFO_RXFE. */
2519 /*! @brief Read current value of the UART_PFIFO_RXFE field. */
2520 #define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
2522 /*! @brief Format value for bitfield UART_PFIFO_RXFE. */
2523 #define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE)
2525 /*! @brief Set the RXFE field to a new value. */
2526 #define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
2530 * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
2532 * The maximum number of transmit datawords that can be stored in the transmit
2533 * buffer. This field is read only.
2536 * - 000 - Transmit FIFO/Buffer depth = 1 dataword.
2537 * - 001 - Transmit FIFO/Buffer depth = 4 datawords.
2538 * - 010 - Transmit FIFO/Buffer depth = 8 datawords.
2539 * - 011 - Transmit FIFO/Buffer depth = 16 datawords.
2540 * - 100 - Transmit FIFO/Buffer depth = 32 datawords.
2541 * - 101 - Transmit FIFO/Buffer depth = 64 datawords.
2542 * - 110 - Transmit FIFO/Buffer depth = 128 datawords.
2546 #define BP_UART_PFIFO_TXFIFOSIZE (4U) /*!< Bit position for UART_PFIFO_TXFIFOSIZE. */
2547 #define BM_UART_PFIFO_TXFIFOSIZE (0x70U) /*!< Bit mask for UART_PFIFO_TXFIFOSIZE. */
2548 #define BS_UART_PFIFO_TXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. */
2550 /*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
2551 #define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
2555 * @name Register UART_PFIFO, field TXFE[7] (RW)
2557 * When this field is set, the built in FIFO structure for the transmit buffer
2558 * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
2559 * field is not set, the transmit buffer operates as a FIFO of depth one dataword
2560 * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
2561 * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
2562 * be issued immediately after changing this field.
2565 * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
2566 * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
2569 #define BP_UART_PFIFO_TXFE (7U) /*!< Bit position for UART_PFIFO_TXFE. */
2570 #define BM_UART_PFIFO_TXFE (0x80U) /*!< Bit mask for UART_PFIFO_TXFE. */
2571 #define BS_UART_PFIFO_TXFE (1U) /*!< Bit field size in bits for UART_PFIFO_TXFE. */
2573 /*! @brief Read current value of the UART_PFIFO_TXFE field. */
2574 #define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
2576 /*! @brief Format value for bitfield UART_PFIFO_TXFE. */
2577 #define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE)
2579 /*! @brief Set the TXFE field to a new value. */
2580 #define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
2583 /*******************************************************************************
2584 * HW_UART_CFIFO - UART FIFO Control Register
2585 ******************************************************************************/
2588 * @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
2590 * Reset value: 0x00U
2592 * This register provides the ability to program various control fields for FIFO
2593 * operation. This register may be read or written at any time. Note that
2594 * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
2595 * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
2596 * TE and RE be cleared prior to flushing the corresponding FIFO.
2598 typedef union _hw_uart_cfifo
2601 struct _hw_uart_cfifo_bitfields
2603 uint8_t RXUFE
: 1; /*!< [0] Receive FIFO Underflow Interrupt Enable */
2604 uint8_t TXOFE
: 1; /*!< [1] Transmit FIFO Overflow Interrupt Enable */
2605 uint8_t RXOFE
: 1; /*!< [2] Receive FIFO Overflow Interrupt Enable */
2606 uint8_t RESERVED0
: 3; /*!< [5:3] */
2607 uint8_t RXFLUSH
: 1; /*!< [6] Receive FIFO/Buffer Flush */
2608 uint8_t TXFLUSH
: 1; /*!< [7] Transmit FIFO/Buffer Flush */
2613 * @name Constants and macros for entire UART_CFIFO register
2616 #define HW_UART_CFIFO_ADDR(x) ((x) + 0x11U)
2618 #define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x))
2619 #define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U)
2620 #define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v))
2621 #define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v)))
2622 #define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
2623 #define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v)))
2627 * Constants & macros for individual UART_CFIFO bitfields
2631 * @name Register UART_CFIFO, field RXUFE[0] (RW)
2633 * When this field is set, the RXUF flag generates an interrupt to the host.
2636 * - 0 - RXUF flag does not generate an interrupt to the host.
2637 * - 1 - RXUF flag generates an interrupt to the host.
2640 #define BP_UART_CFIFO_RXUFE (0U) /*!< Bit position for UART_CFIFO_RXUFE. */
2641 #define BM_UART_CFIFO_RXUFE (0x01U) /*!< Bit mask for UART_CFIFO_RXUFE. */
2642 #define BS_UART_CFIFO_RXUFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXUFE. */
2644 /*! @brief Read current value of the UART_CFIFO_RXUFE field. */
2645 #define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
2647 /*! @brief Format value for bitfield UART_CFIFO_RXUFE. */
2648 #define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE)
2650 /*! @brief Set the RXUFE field to a new value. */
2651 #define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
2655 * @name Register UART_CFIFO, field TXOFE[1] (RW)
2657 * When this field is set, the TXOF flag generates an interrupt to the host.
2660 * - 0 - TXOF flag does not generate an interrupt to the host.
2661 * - 1 - TXOF flag generates an interrupt to the host.
2664 #define BP_UART_CFIFO_TXOFE (1U) /*!< Bit position for UART_CFIFO_TXOFE. */
2665 #define BM_UART_CFIFO_TXOFE (0x02U) /*!< Bit mask for UART_CFIFO_TXOFE. */
2666 #define BS_UART_CFIFO_TXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_TXOFE. */
2668 /*! @brief Read current value of the UART_CFIFO_TXOFE field. */
2669 #define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
2671 /*! @brief Format value for bitfield UART_CFIFO_TXOFE. */
2672 #define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE)
2674 /*! @brief Set the TXOFE field to a new value. */
2675 #define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
2679 * @name Register UART_CFIFO, field RXOFE[2] (RW)
2681 * When this field is set, the RXOF flag generates an interrupt to the host.
2684 * - 0 - RXOF flag does not generate an interrupt to the host.
2685 * - 1 - RXOF flag generates an interrupt to the host.
2688 #define BP_UART_CFIFO_RXOFE (2U) /*!< Bit position for UART_CFIFO_RXOFE. */
2689 #define BM_UART_CFIFO_RXOFE (0x04U) /*!< Bit mask for UART_CFIFO_RXOFE. */
2690 #define BS_UART_CFIFO_RXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXOFE. */
2692 /*! @brief Read current value of the UART_CFIFO_RXOFE field. */
2693 #define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
2695 /*! @brief Format value for bitfield UART_CFIFO_RXOFE. */
2696 #define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE)
2698 /*! @brief Set the RXOFE field to a new value. */
2699 #define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
2703 * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
2705 * Writing to this field causes all data that is stored in the receive
2706 * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
2710 * - 0 - No flush operation occurs.
2711 * - 1 - All data in the receive FIFO/buffer is cleared out.
2714 #define BP_UART_CFIFO_RXFLUSH (6U) /*!< Bit position for UART_CFIFO_RXFLUSH. */
2715 #define BM_UART_CFIFO_RXFLUSH (0x40U) /*!< Bit mask for UART_CFIFO_RXFLUSH. */
2716 #define BS_UART_CFIFO_RXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_RXFLUSH. */
2718 /*! @brief Format value for bitfield UART_CFIFO_RXFLUSH. */
2719 #define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH)
2721 /*! @brief Set the RXFLUSH field to a new value. */
2722 #define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
2726 * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
2728 * Writing to this field causes all data that is stored in the transmit
2729 * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
2733 * - 0 - No flush operation occurs.
2734 * - 1 - All data in the transmit FIFO/Buffer is cleared out.
2737 #define BP_UART_CFIFO_TXFLUSH (7U) /*!< Bit position for UART_CFIFO_TXFLUSH. */
2738 #define BM_UART_CFIFO_TXFLUSH (0x80U) /*!< Bit mask for UART_CFIFO_TXFLUSH. */
2739 #define BS_UART_CFIFO_TXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_TXFLUSH. */
2741 /*! @brief Format value for bitfield UART_CFIFO_TXFLUSH. */
2742 #define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH)
2744 /*! @brief Set the TXFLUSH field to a new value. */
2745 #define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
2748 /*******************************************************************************
2749 * HW_UART_SFIFO - UART FIFO Status Register
2750 ******************************************************************************/
2753 * @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
2755 * Reset value: 0xC0U
2757 * This register provides status information regarding the transmit and receiver
2758 * buffers/FIFOs, including interrupt information. This register may be written
2759 * to or read at any time.
2761 typedef union _hw_uart_sfifo
2764 struct _hw_uart_sfifo_bitfields
2766 uint8_t RXUF
: 1; /*!< [0] Receiver Buffer Underflow Flag */
2767 uint8_t TXOF
: 1; /*!< [1] Transmitter Buffer Overflow Flag */
2768 uint8_t RXOF
: 1; /*!< [2] Receiver Buffer Overflow Flag */
2769 uint8_t RESERVED0
: 3; /*!< [5:3] */
2770 uint8_t RXEMPT
: 1; /*!< [6] Receive Buffer/FIFO Empty */
2771 uint8_t TXEMPT
: 1; /*!< [7] Transmit Buffer/FIFO Empty */
2776 * @name Constants and macros for entire UART_SFIFO register
2779 #define HW_UART_SFIFO_ADDR(x) ((x) + 0x12U)
2781 #define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x))
2782 #define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U)
2783 #define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v))
2784 #define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v)))
2785 #define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
2786 #define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v)))
2790 * Constants & macros for individual UART_SFIFO bitfields
2794 * @name Register UART_SFIFO, field RXUF[0] (W1C)
2796 * Indicates that more data has been read from the receive buffer than was
2797 * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
2798 * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
2799 * is cleared by writing a 1.
2802 * - 0 - No receive buffer underflow has occurred since the last time the flag
2804 * - 1 - At least one receive buffer underflow has occurred since the last time
2805 * the flag was cleared.
2808 #define BP_UART_SFIFO_RXUF (0U) /*!< Bit position for UART_SFIFO_RXUF. */
2809 #define BM_UART_SFIFO_RXUF (0x01U) /*!< Bit mask for UART_SFIFO_RXUF. */
2810 #define BS_UART_SFIFO_RXUF (1U) /*!< Bit field size in bits for UART_SFIFO_RXUF. */
2812 /*! @brief Read current value of the UART_SFIFO_RXUF field. */
2813 #define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
2815 /*! @brief Format value for bitfield UART_SFIFO_RXUF. */
2816 #define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF)
2818 /*! @brief Set the RXUF field to a new value. */
2819 #define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
2823 * @name Register UART_SFIFO, field TXOF[1] (W1C)
2825 * Indicates that more data has been written to the transmit buffer than it can
2826 * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
2827 * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
2828 * flag is cleared by writing a 1.
2831 * - 0 - No transmit buffer overflow has occurred since the last time the flag
2833 * - 1 - At least one transmit buffer overflow has occurred since the last time
2834 * the flag was cleared.
2837 #define BP_UART_SFIFO_TXOF (1U) /*!< Bit position for UART_SFIFO_TXOF. */
2838 #define BM_UART_SFIFO_TXOF (0x02U) /*!< Bit mask for UART_SFIFO_TXOF. */
2839 #define BS_UART_SFIFO_TXOF (1U) /*!< Bit field size in bits for UART_SFIFO_TXOF. */
2841 /*! @brief Read current value of the UART_SFIFO_TXOF field. */
2842 #define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
2844 /*! @brief Format value for bitfield UART_SFIFO_TXOF. */
2845 #define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF)
2847 /*! @brief Set the TXOF field to a new value. */
2848 #define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
2852 * @name Register UART_SFIFO, field RXOF[2] (W1C)
2854 * Indicates that more data has been written to the receive buffer than it can
2855 * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
2856 * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
2857 * is cleared by writing a 1.
2860 * - 0 - No receive buffer overflow has occurred since the last time the flag
2862 * - 1 - At least one receive buffer overflow has occurred since the last time
2863 * the flag was cleared.
2866 #define BP_UART_SFIFO_RXOF (2U) /*!< Bit position for UART_SFIFO_RXOF. */
2867 #define BM_UART_SFIFO_RXOF (0x04U) /*!< Bit mask for UART_SFIFO_RXOF. */
2868 #define BS_UART_SFIFO_RXOF (1U) /*!< Bit field size in bits for UART_SFIFO_RXOF. */
2870 /*! @brief Read current value of the UART_SFIFO_RXOF field. */
2871 #define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
2873 /*! @brief Format value for bitfield UART_SFIFO_RXOF. */
2874 #define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF)
2876 /*! @brief Set the RXOF field to a new value. */
2877 #define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
2881 * @name Register UART_SFIFO, field RXEMPT[6] (RO)
2883 * Asserts when there is no data in the receive FIFO/Buffer. This field does not
2884 * take into account data that is in the receive shift register.
2887 * - 0 - Receive buffer is not empty.
2888 * - 1 - Receive buffer is empty.
2891 #define BP_UART_SFIFO_RXEMPT (6U) /*!< Bit position for UART_SFIFO_RXEMPT. */
2892 #define BM_UART_SFIFO_RXEMPT (0x40U) /*!< Bit mask for UART_SFIFO_RXEMPT. */
2893 #define BS_UART_SFIFO_RXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_RXEMPT. */
2895 /*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
2896 #define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
2900 * @name Register UART_SFIFO, field TXEMPT[7] (RO)
2902 * Asserts when there is no data in the Transmit FIFO/buffer. This field does
2903 * not take into account data that is in the transmit shift register.
2906 * - 0 - Transmit buffer is not empty.
2907 * - 1 - Transmit buffer is empty.
2910 #define BP_UART_SFIFO_TXEMPT (7U) /*!< Bit position for UART_SFIFO_TXEMPT. */
2911 #define BM_UART_SFIFO_TXEMPT (0x80U) /*!< Bit mask for UART_SFIFO_TXEMPT. */
2912 #define BS_UART_SFIFO_TXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_TXEMPT. */
2914 /*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
2915 #define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
2918 /*******************************************************************************
2919 * HW_UART_TWFIFO - UART FIFO Transmit Watermark
2920 ******************************************************************************/
2923 * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
2925 * Reset value: 0x00U
2927 * This register provides the ability to set a programmable threshold for
2928 * notification of needing additional transmit data. This register may be read at any
2929 * time but must be written only when C2[TE] is not set. Changing the value of the
2930 * watermark will not clear the S1[TDRE] flag.
2932 typedef union _hw_uart_twfifo
2935 struct _hw_uart_twfifo_bitfields
2937 uint8_t TXWATER
: 8; /*!< [7:0] Transmit Watermark */
2942 * @name Constants and macros for entire UART_TWFIFO register
2945 #define HW_UART_TWFIFO_ADDR(x) ((x) + 0x13U)
2947 #define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x))
2948 #define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U)
2949 #define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v))
2950 #define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v)))
2951 #define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
2952 #define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v)))
2956 * Constants & macros for individual UART_TWFIFO bitfields
2960 * @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
2962 * When the number of datawords in the transmit FIFO/buffer is equal to or less
2963 * than the value in this register field, an interrupt via S1[TDRE] or a DMA
2964 * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
2965 * proper operation, the value in TXWATER must be set to be less than the size of
2966 * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
2969 #define BP_UART_TWFIFO_TXWATER (0U) /*!< Bit position for UART_TWFIFO_TXWATER. */
2970 #define BM_UART_TWFIFO_TXWATER (0xFFU) /*!< Bit mask for UART_TWFIFO_TXWATER. */
2971 #define BS_UART_TWFIFO_TXWATER (8U) /*!< Bit field size in bits for UART_TWFIFO_TXWATER. */
2973 /*! @brief Read current value of the UART_TWFIFO_TXWATER field. */
2974 #define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
2976 /*! @brief Format value for bitfield UART_TWFIFO_TXWATER. */
2977 #define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER)
2979 /*! @brief Set the TXWATER field to a new value. */
2980 #define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
2983 /*******************************************************************************
2984 * HW_UART_TCFIFO - UART FIFO Transmit Count
2985 ******************************************************************************/
2988 * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
2990 * Reset value: 0x00U
2992 * This is a read only register that indicates how many datawords are currently
2993 * in the transmit buffer/FIFO. It may be read at any time.
2995 typedef union _hw_uart_tcfifo
2998 struct _hw_uart_tcfifo_bitfields
3000 uint8_t TXCOUNT
: 8; /*!< [7:0] Transmit Counter */
3005 * @name Constants and macros for entire UART_TCFIFO register
3008 #define HW_UART_TCFIFO_ADDR(x) ((x) + 0x14U)
3010 #define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x))
3011 #define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U)
3015 * Constants & macros for individual UART_TCFIFO bitfields
3019 * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
3021 * The value in this register indicates the number of datawords that are in the
3022 * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
3023 * transmit shift register, it is not included in the count. This value may be used
3024 * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
3025 * transmit FIFO/buffer.
3028 #define BP_UART_TCFIFO_TXCOUNT (0U) /*!< Bit position for UART_TCFIFO_TXCOUNT. */
3029 #define BM_UART_TCFIFO_TXCOUNT (0xFFU) /*!< Bit mask for UART_TCFIFO_TXCOUNT. */
3030 #define BS_UART_TCFIFO_TXCOUNT (8U) /*!< Bit field size in bits for UART_TCFIFO_TXCOUNT. */
3032 /*! @brief Read current value of the UART_TCFIFO_TXCOUNT field. */
3033 #define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
3036 /*******************************************************************************
3037 * HW_UART_RWFIFO - UART FIFO Receive Watermark
3038 ******************************************************************************/
3041 * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
3043 * Reset value: 0x01U
3045 * This register provides the ability to set a programmable threshold for
3046 * notification of the need to remove data from the receiver FIFO/buffer. This register
3047 * may be read at any time but must be written only when C2[RE] is not asserted.
3048 * Changing the value in this register will not clear S1[RDRF].
3050 typedef union _hw_uart_rwfifo
3053 struct _hw_uart_rwfifo_bitfields
3055 uint8_t RXWATER
: 8; /*!< [7:0] Receive Watermark */
3060 * @name Constants and macros for entire UART_RWFIFO register
3063 #define HW_UART_RWFIFO_ADDR(x) ((x) + 0x15U)
3065 #define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x))
3066 #define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U)
3067 #define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v))
3068 #define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v)))
3069 #define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
3070 #define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v)))
3074 * Constants & macros for individual UART_RWFIFO bitfields
3078 * @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
3080 * When the number of datawords in the receive FIFO/buffer is equal to or
3081 * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
3082 * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
3083 * proper operation, the value in RXWATER must be set to be less than the receive
3084 * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
3088 #define BP_UART_RWFIFO_RXWATER (0U) /*!< Bit position for UART_RWFIFO_RXWATER. */
3089 #define BM_UART_RWFIFO_RXWATER (0xFFU) /*!< Bit mask for UART_RWFIFO_RXWATER. */
3090 #define BS_UART_RWFIFO_RXWATER (8U) /*!< Bit field size in bits for UART_RWFIFO_RXWATER. */
3092 /*! @brief Read current value of the UART_RWFIFO_RXWATER field. */
3093 #define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
3095 /*! @brief Format value for bitfield UART_RWFIFO_RXWATER. */
3096 #define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER)
3098 /*! @brief Set the RXWATER field to a new value. */
3099 #define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
3102 /*******************************************************************************
3103 * HW_UART_RCFIFO - UART FIFO Receive Count
3104 ******************************************************************************/
3107 * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
3109 * Reset value: 0x00U
3111 * This is a read only register that indicates how many datawords are currently
3112 * in the receive FIFO/buffer. It may be read at any time.
3114 typedef union _hw_uart_rcfifo
3117 struct _hw_uart_rcfifo_bitfields
3119 uint8_t RXCOUNT
: 8; /*!< [7:0] Receive Counter */
3124 * @name Constants and macros for entire UART_RCFIFO register
3127 #define HW_UART_RCFIFO_ADDR(x) ((x) + 0x16U)
3129 #define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x))
3130 #define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U)
3134 * Constants & macros for individual UART_RCFIFO bitfields
3138 * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
3140 * The value in this register indicates the number of datawords that are in the
3141 * receive FIFO/buffer. If a dataword is being received, that is, in the receive
3142 * shift register, it is not included in the count. This value may be used in
3143 * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
3144 * receive FIFO/buffer.
3147 #define BP_UART_RCFIFO_RXCOUNT (0U) /*!< Bit position for UART_RCFIFO_RXCOUNT. */
3148 #define BM_UART_RCFIFO_RXCOUNT (0xFFU) /*!< Bit mask for UART_RCFIFO_RXCOUNT. */
3149 #define BS_UART_RCFIFO_RXCOUNT (8U) /*!< Bit field size in bits for UART_RCFIFO_RXCOUNT. */
3151 /*! @brief Read current value of the UART_RCFIFO_RXCOUNT field. */
3152 #define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
3155 /*******************************************************************************
3156 * HW_UART_C7816 - UART 7816 Control Register
3157 ******************************************************************************/
3160 * @brief HW_UART_C7816 - UART 7816 Control Register (RW)
3162 * Reset value: 0x00U
3164 * The C7816 register is the primary control register for ISO-7816 specific
3165 * functionality. This register is specific to 7816 functionality and the values in
3166 * this register have no effect on UART operation and should be ignored if
3167 * ISO_7816E is not set/enabled. This register may be read at any time but values must
3168 * be changed only when ISO_7816E is not set.
3170 typedef union _hw_uart_c7816
3173 struct _hw_uart_c7816_bitfields
3175 uint8_t ISO_7816E
: 1; /*!< [0] ISO-7816 Functionality Enabled */
3176 uint8_t TTYPE
: 1; /*!< [1] Transfer Type */
3177 uint8_t INIT
: 1; /*!< [2] Detect Initial Character */
3178 uint8_t ANACK
: 1; /*!< [3] Generate NACK on Error */
3179 uint8_t ONACK
: 1; /*!< [4] Generate NACK on Overflow */
3180 uint8_t RESERVED0
: 3; /*!< [7:5] */
3185 * @name Constants and macros for entire UART_C7816 register
3188 #define HW_UART_C7816_ADDR(x) ((x) + 0x18U)
3190 #define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x))
3191 #define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U)
3192 #define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v))
3193 #define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v)))
3194 #define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
3195 #define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v)))
3199 * Constants & macros for individual UART_C7816 bitfields
3203 * @name Register UART_C7816, field ISO_7816E[0] (RW)
3205 * Indicates that the UART is operating according to the ISO-7816 protocol. This
3206 * field must be modified only when no transmit or receive is occurring. If this
3207 * field is changed during a data transfer, the data being transmitted or
3208 * received may be transferred incorrectly.
3211 * - 0 - ISO-7816 functionality is turned off/not enabled.
3212 * - 1 - ISO-7816 functionality is turned on/enabled.
3215 #define BP_UART_C7816_ISO_7816E (0U) /*!< Bit position for UART_C7816_ISO_7816E. */
3216 #define BM_UART_C7816_ISO_7816E (0x01U) /*!< Bit mask for UART_C7816_ISO_7816E. */
3217 #define BS_UART_C7816_ISO_7816E (1U) /*!< Bit field size in bits for UART_C7816_ISO_7816E. */
3219 /*! @brief Read current value of the UART_C7816_ISO_7816E field. */
3220 #define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
3222 /*! @brief Format value for bitfield UART_C7816_ISO_7816E. */
3223 #define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E)
3225 /*! @brief Set the ISO_7816E field to a new value. */
3226 #define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
3230 * @name Register UART_C7816, field TTYPE[1] (RW)
3232 * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
3236 * - 0 - T = 0 per the ISO-7816 specification.
3237 * - 1 - T = 1 per the ISO-7816 specification.
3240 #define BP_UART_C7816_TTYPE (1U) /*!< Bit position for UART_C7816_TTYPE. */
3241 #define BM_UART_C7816_TTYPE (0x02U) /*!< Bit mask for UART_C7816_TTYPE. */
3242 #define BS_UART_C7816_TTYPE (1U) /*!< Bit field size in bits for UART_C7816_TTYPE. */
3244 /*! @brief Read current value of the UART_C7816_TTYPE field. */
3245 #define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
3247 /*! @brief Format value for bitfield UART_C7816_TTYPE. */
3248 #define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE)
3250 /*! @brief Set the TTYPE field to a new value. */
3251 #define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
3255 * @name Register UART_C7816, field INIT[2] (RW)
3257 * When this field is set, all received characters are searched for a valid
3258 * initial character. If an invalid initial character is identified, and ANACK is
3259 * set, a NACK is sent. All received data is discarded and error flags blocked
3260 * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[ADT],
3261 * IS7816[GTV]) until a valid initial character is detected. Upon detecting a
3262 * valid initial character, the configuration values S2[MSBF], C3[TXINV], and
3263 * S2[RXINV] are automatically updated to reflect the initial character that was
3264 * received. The actual INIT data value is not stored in the receive buffer.
3265 * Additionally, upon detection of a valid initial character, IS7816[INITD] is set and an
3266 * interrupt issued as programmed by IE7816[INITDE]. When a valid initial
3267 * character is detected, INIT is automatically cleared. This Initial Character Detect
3268 * feature is supported only in T = 0 protocol mode.
3271 * - 0 - Normal operating mode. Receiver does not seek to identify initial
3273 * - 1 - Receiver searches for initial character.
3276 #define BP_UART_C7816_INIT (2U) /*!< Bit position for UART_C7816_INIT. */
3277 #define BM_UART_C7816_INIT (0x04U) /*!< Bit mask for UART_C7816_INIT. */
3278 #define BS_UART_C7816_INIT (1U) /*!< Bit field size in bits for UART_C7816_INIT. */
3280 /*! @brief Read current value of the UART_C7816_INIT field. */
3281 #define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
3283 /*! @brief Format value for bitfield UART_C7816_INIT. */
3284 #define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT)
3286 /*! @brief Set the INIT field to a new value. */
3287 #define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
3291 * @name Register UART_C7816, field ANACK[3] (RW)
3293 * When this field is set, the receiver automatically generates a NACK response
3294 * if a parity error occurs or if INIT is set and an invalid initial character is
3295 * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
3296 * attempts to retransmit the data indefinitely. To stop retransmission attempts,
3297 * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
3300 * - 0 - No NACK is automatically generated.
3301 * - 1 - A NACK is automatically generated if a parity error is detected or if
3302 * an invalid initial character is detected.
3305 #define BP_UART_C7816_ANACK (3U) /*!< Bit position for UART_C7816_ANACK. */
3306 #define BM_UART_C7816_ANACK (0x08U) /*!< Bit mask for UART_C7816_ANACK. */
3307 #define BS_UART_C7816_ANACK (1U) /*!< Bit field size in bits for UART_C7816_ANACK. */
3309 /*! @brief Read current value of the UART_C7816_ANACK field. */
3310 #define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
3312 /*! @brief Format value for bitfield UART_C7816_ANACK. */
3313 #define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK)
3315 /*! @brief Set the ANACK field to a new value. */
3316 #define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
3320 * @name Register UART_C7816, field ONACK[4] (RW)
3322 * When this field is set, the receiver automatically generates a NACK response
3323 * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
3324 * this results in the transmitter resending the packet that overflowed until the
3325 * retransmit threshold for that transmitter is reached. A NACK is generated only
3326 * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
3330 * - 0 - The received data does not generate a NACK when the receipt of the data
3331 * results in an overflow event.
3332 * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
3333 * received character.
3336 #define BP_UART_C7816_ONACK (4U) /*!< Bit position for UART_C7816_ONACK. */
3337 #define BM_UART_C7816_ONACK (0x10U) /*!< Bit mask for UART_C7816_ONACK. */
3338 #define BS_UART_C7816_ONACK (1U) /*!< Bit field size in bits for UART_C7816_ONACK. */
3340 /*! @brief Read current value of the UART_C7816_ONACK field. */
3341 #define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
3343 /*! @brief Format value for bitfield UART_C7816_ONACK. */
3344 #define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK)
3346 /*! @brief Set the ONACK field to a new value. */
3347 #define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
3350 /*******************************************************************************
3351 * HW_UART_IE7816 - UART 7816 Interrupt Enable Register
3352 ******************************************************************************/
3355 * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
3357 * Reset value: 0x00U
3359 * The IE7816 register controls which flags result in an interrupt being issued.
3360 * This register is specific to 7816 functionality, the corresponding flags that
3361 * drive the interrupts are not asserted when 7816E is not set/enabled. However,
3362 * these flags may remain set if they are asserted while 7816E was set and not
3363 * subsequently cleared. This register may be read or written to at any time.
3365 typedef union _hw_uart_ie7816
3368 struct _hw_uart_ie7816_bitfields
3370 uint8_t RXTE
: 1; /*!< [0] Receive Threshold Exceeded Interrupt
3372 uint8_t TXTE
: 1; /*!< [1] Transmit Threshold Exceeded Interrupt
3374 uint8_t GTVE
: 1; /*!< [2] Guard Timer Violated Interrupt Enable */
3375 uint8_t ADTE
: 1; /*!< [3] ATR Duration Timer Interrupt Enable */
3376 uint8_t INITDE
: 1; /*!< [4] Initial Character Detected Interrupt
3378 uint8_t BWTE
: 1; /*!< [5] Block Wait Timer Interrupt Enable */
3379 uint8_t CWTE
: 1; /*!< [6] Character Wait Timer Interrupt Enable */
3380 uint8_t WTE
: 1; /*!< [7] Wait Timer Interrupt Enable */
3385 * @name Constants and macros for entire UART_IE7816 register
3388 #define HW_UART_IE7816_ADDR(x) ((x) + 0x19U)
3390 #define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x))
3391 #define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U)
3392 #define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v))
3393 #define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v)))
3394 #define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
3395 #define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v)))
3399 * Constants & macros for individual UART_IE7816 bitfields
3403 * @name Register UART_IE7816, field RXTE[0] (RW)
3406 * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
3408 * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
3411 #define BP_UART_IE7816_RXTE (0U) /*!< Bit position for UART_IE7816_RXTE. */
3412 #define BM_UART_IE7816_RXTE (0x01U) /*!< Bit mask for UART_IE7816_RXTE. */
3413 #define BS_UART_IE7816_RXTE (1U) /*!< Bit field size in bits for UART_IE7816_RXTE. */
3415 /*! @brief Read current value of the UART_IE7816_RXTE field. */
3416 #define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
3418 /*! @brief Format value for bitfield UART_IE7816_RXTE. */
3419 #define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE)
3421 /*! @brief Set the RXTE field to a new value. */
3422 #define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
3426 * @name Register UART_IE7816, field TXTE[1] (RW)
3429 * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
3431 * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
3434 #define BP_UART_IE7816_TXTE (1U) /*!< Bit position for UART_IE7816_TXTE. */
3435 #define BM_UART_IE7816_TXTE (0x02U) /*!< Bit mask for UART_IE7816_TXTE. */
3436 #define BS_UART_IE7816_TXTE (1U) /*!< Bit field size in bits for UART_IE7816_TXTE. */
3438 /*! @brief Read current value of the UART_IE7816_TXTE field. */
3439 #define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
3441 /*! @brief Format value for bitfield UART_IE7816_TXTE. */
3442 #define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE)
3444 /*! @brief Set the TXTE field to a new value. */
3445 #define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
3449 * @name Register UART_IE7816, field GTVE[2] (RW)
3452 * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
3454 * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
3457 #define BP_UART_IE7816_GTVE (2U) /*!< Bit position for UART_IE7816_GTVE. */
3458 #define BM_UART_IE7816_GTVE (0x04U) /*!< Bit mask for UART_IE7816_GTVE. */
3459 #define BS_UART_IE7816_GTVE (1U) /*!< Bit field size in bits for UART_IE7816_GTVE. */
3461 /*! @brief Read current value of the UART_IE7816_GTVE field. */
3462 #define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
3464 /*! @brief Format value for bitfield UART_IE7816_GTVE. */
3465 #define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE)
3467 /*! @brief Set the GTVE field to a new value. */
3468 #define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
3472 * @name Register UART_IE7816, field ADTE[3] (RW)
3475 * - 0 - The assertion of IS7816[ADT] does not result in the generation of an
3477 * - 1 - The assertion of IS7816[ADT] results in the generation of an interrupt.
3480 #define BP_UART_IE7816_ADTE (3U) /*!< Bit position for UART_IE7816_ADTE. */
3481 #define BM_UART_IE7816_ADTE (0x08U) /*!< Bit mask for UART_IE7816_ADTE. */
3482 #define BS_UART_IE7816_ADTE (1U) /*!< Bit field size in bits for UART_IE7816_ADTE. */
3484 /*! @brief Read current value of the UART_IE7816_ADTE field. */
3485 #define BR_UART_IE7816_ADTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_ADTE))
3487 /*! @brief Format value for bitfield UART_IE7816_ADTE. */
3488 #define BF_UART_IE7816_ADTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_ADTE) & BM_UART_IE7816_ADTE)
3490 /*! @brief Set the ADTE field to a new value. */
3491 #define BW_UART_IE7816_ADTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_ADTE) = (v))
3495 * @name Register UART_IE7816, field INITDE[4] (RW)
3498 * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
3500 * - 1 - The assertion of IS7816[INITD] results in the generation of an
3504 #define BP_UART_IE7816_INITDE (4U) /*!< Bit position for UART_IE7816_INITDE. */
3505 #define BM_UART_IE7816_INITDE (0x10U) /*!< Bit mask for UART_IE7816_INITDE. */
3506 #define BS_UART_IE7816_INITDE (1U) /*!< Bit field size in bits for UART_IE7816_INITDE. */
3508 /*! @brief Read current value of the UART_IE7816_INITDE field. */
3509 #define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
3511 /*! @brief Format value for bitfield UART_IE7816_INITDE. */
3512 #define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE)
3514 /*! @brief Set the INITDE field to a new value. */
3515 #define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
3519 * @name Register UART_IE7816, field BWTE[5] (RW)
3522 * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
3524 * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
3527 #define BP_UART_IE7816_BWTE (5U) /*!< Bit position for UART_IE7816_BWTE. */
3528 #define BM_UART_IE7816_BWTE (0x20U) /*!< Bit mask for UART_IE7816_BWTE. */
3529 #define BS_UART_IE7816_BWTE (1U) /*!< Bit field size in bits for UART_IE7816_BWTE. */
3531 /*! @brief Read current value of the UART_IE7816_BWTE field. */
3532 #define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
3534 /*! @brief Format value for bitfield UART_IE7816_BWTE. */
3535 #define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE)
3537 /*! @brief Set the BWTE field to a new value. */
3538 #define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
3542 * @name Register UART_IE7816, field CWTE[6] (RW)
3545 * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
3547 * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
3550 #define BP_UART_IE7816_CWTE (6U) /*!< Bit position for UART_IE7816_CWTE. */
3551 #define BM_UART_IE7816_CWTE (0x40U) /*!< Bit mask for UART_IE7816_CWTE. */
3552 #define BS_UART_IE7816_CWTE (1U) /*!< Bit field size in bits for UART_IE7816_CWTE. */
3554 /*! @brief Read current value of the UART_IE7816_CWTE field. */
3555 #define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
3557 /*! @brief Format value for bitfield UART_IE7816_CWTE. */
3558 #define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE)
3560 /*! @brief Set the CWTE field to a new value. */
3561 #define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
3565 * @name Register UART_IE7816, field WTE[7] (RW)
3568 * - 0 - The assertion of IS7816[WT] does not result in the generation of an
3570 * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
3573 #define BP_UART_IE7816_WTE (7U) /*!< Bit position for UART_IE7816_WTE. */
3574 #define BM_UART_IE7816_WTE (0x80U) /*!< Bit mask for UART_IE7816_WTE. */
3575 #define BS_UART_IE7816_WTE (1U) /*!< Bit field size in bits for UART_IE7816_WTE. */
3577 /*! @brief Read current value of the UART_IE7816_WTE field. */
3578 #define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
3580 /*! @brief Format value for bitfield UART_IE7816_WTE. */
3581 #define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE)
3583 /*! @brief Set the WTE field to a new value. */
3584 #define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
3587 /*******************************************************************************
3588 * HW_UART_IS7816 - UART 7816 Interrupt Status Register
3589 ******************************************************************************/
3592 * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (W1C)
3594 * Reset value: 0x00U
3596 * The IS7816 register provides a mechanism to read and clear the interrupt
3597 * flags. All flags/interrupts are cleared by writing a 1 to the field location.
3598 * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
3599 * the flag condition that occurred since the last time the bit was cleared, not
3600 * that the condition currently exists. The status flags are set regardless of
3601 * whether the corresponding field in the IE7816 is set or cleared. The IE7816
3602 * controls only if an interrupt is issued to the host processor. This register is
3603 * specific to 7816 functionality and the values in this register have no affect on
3604 * UART operation and should be ignored if 7816E is not set/enabled. This
3605 * register may be read or written at anytime.
3607 typedef union _hw_uart_is7816
3610 struct _hw_uart_is7816_bitfields
3612 uint8_t RXT
: 1; /*!< [0] Receive Threshold Exceeded Interrupt */
3613 uint8_t TXT
: 1; /*!< [1] Transmit Threshold Exceeded Interrupt */
3614 uint8_t GTV
: 1; /*!< [2] Guard Timer Violated Interrupt */
3615 uint8_t ADT
: 1; /*!< [3] ATR Duration Time Interrupt */
3616 uint8_t INITD
: 1; /*!< [4] Initial Character Detected Interrupt */
3617 uint8_t BWT
: 1; /*!< [5] Block Wait Timer Interrupt */
3618 uint8_t CWT
: 1; /*!< [6] Character Wait Timer Interrupt */
3619 uint8_t WT
: 1; /*!< [7] Wait Timer Interrupt */
3624 * @name Constants and macros for entire UART_IS7816 register
3627 #define HW_UART_IS7816_ADDR(x) ((x) + 0x1AU)
3629 #define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x))
3630 #define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U)
3631 #define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v))
3632 #define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v)))
3633 #define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
3634 #define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v)))
3638 * Constants & macros for individual UART_IS7816 bitfields
3642 * @name Register UART_IS7816, field RXT[0] (W1C)
3644 * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
3645 * generated in response to parity errors on received data. This flag requires ANACK
3646 * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
3647 * Clearing this field also resets the counter keeping track of consecutive NACKS. The
3648 * UART will continue to attempt to receive data regardless of whether this flag
3649 * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
3650 * or packet is received without needing to issue a NACK, the internal NACK
3651 * detection counter is cleared and the count restarts from zero on the next
3652 * transmitted NACK. This interrupt is cleared by writing 1.
3655 * - 0 - The number of consecutive NACKS generated as a result of parity errors
3656 * and buffer overruns is less than or equal to the value in
3657 * ET7816[RXTHRESHOLD].
3658 * - 1 - The number of consecutive NACKS generated as a result of parity errors
3659 * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
3662 #define BP_UART_IS7816_RXT (0U) /*!< Bit position for UART_IS7816_RXT. */
3663 #define BM_UART_IS7816_RXT (0x01U) /*!< Bit mask for UART_IS7816_RXT. */
3664 #define BS_UART_IS7816_RXT (1U) /*!< Bit field size in bits for UART_IS7816_RXT. */
3666 /*! @brief Read current value of the UART_IS7816_RXT field. */
3667 #define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
3669 /*! @brief Format value for bitfield UART_IS7816_RXT. */
3670 #define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT)
3672 /*! @brief Set the RXT field to a new value. */
3673 #define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
3677 * @name Register UART_IS7816, field TXT[1] (W1C)
3679 * Indicates that the transmit NACK threshold has been exceeded as indicated by
3680 * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
3681 * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
3682 * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
3683 * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
3684 * internal NACK detection counter is cleared and the count restarts from zero on
3685 * the next received NACK. This interrupt is cleared by writing 1.
3688 * - 0 - The number of retries and corresponding NACKS does not exceed the value
3689 * in ET7816[TXTHRESHOLD].
3690 * - 1 - The number of retries and corresponding NACKS exceeds the value in
3691 * ET7816[TXTHRESHOLD].
3694 #define BP_UART_IS7816_TXT (1U) /*!< Bit position for UART_IS7816_TXT. */
3695 #define BM_UART_IS7816_TXT (0x02U) /*!< Bit mask for UART_IS7816_TXT. */
3696 #define BS_UART_IS7816_TXT (1U) /*!< Bit field size in bits for UART_IS7816_TXT. */
3698 /*! @brief Read current value of the UART_IS7816_TXT field. */
3699 #define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
3701 /*! @brief Format value for bitfield UART_IS7816_TXT. */
3702 #define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT)
3704 /*! @brief Set the TXT field to a new value. */
3705 #define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
3709 * @name Register UART_IS7816, field GTV[2] (W1C)
3711 * Indicates that one or more of the character guard time, block guard time, or
3712 * guard time are violated. This interrupt is cleared by writing 1.
3715 * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
3716 * - 1 - A guard time (GT, CGT, or BGT) has been violated.
3719 #define BP_UART_IS7816_GTV (2U) /*!< Bit position for UART_IS7816_GTV. */
3720 #define BM_UART_IS7816_GTV (0x04U) /*!< Bit mask for UART_IS7816_GTV. */
3721 #define BS_UART_IS7816_GTV (1U) /*!< Bit field size in bits for UART_IS7816_GTV. */
3723 /*! @brief Read current value of the UART_IS7816_GTV field. */
3724 #define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
3726 /*! @brief Format value for bitfield UART_IS7816_GTV. */
3727 #define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV)
3729 /*! @brief Set the GTV field to a new value. */
3730 #define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
3734 * @name Register UART_IS7816, field ADT[3] (W1C)
3736 * Indicates that the ATR duration time, the time between the leading edge of
3737 * the TS character being received and the leading edge of the next response
3738 * character, has exceeded the programmed value. This flag asserts only when
3739 * C7816[TTYPE] = 0. This interrupt is cleared by writing 1.
3742 * - 0 - ATR Duration time (ADT) has not been violated.
3743 * - 1 - ATR Duration time (ADT) has been violated.
3746 #define BP_UART_IS7816_ADT (3U) /*!< Bit position for UART_IS7816_ADT. */
3747 #define BM_UART_IS7816_ADT (0x08U) /*!< Bit mask for UART_IS7816_ADT. */
3748 #define BS_UART_IS7816_ADT (1U) /*!< Bit field size in bits for UART_IS7816_ADT. */
3750 /*! @brief Read current value of the UART_IS7816_ADT field. */
3751 #define BR_UART_IS7816_ADT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_ADT))
3753 /*! @brief Format value for bitfield UART_IS7816_ADT. */
3754 #define BF_UART_IS7816_ADT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_ADT) & BM_UART_IS7816_ADT)
3756 /*! @brief Set the ADT field to a new value. */
3757 #define BW_UART_IS7816_ADT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_ADT) = (v))
3761 * @name Register UART_IS7816, field INITD[4] (W1C)
3763 * Indicates that a valid initial character is received. This interrupt is
3764 * cleared by writing 1.
3767 * - 0 - A valid initial character has not been received.
3768 * - 1 - A valid initial character has been received.
3771 #define BP_UART_IS7816_INITD (4U) /*!< Bit position for UART_IS7816_INITD. */
3772 #define BM_UART_IS7816_INITD (0x10U) /*!< Bit mask for UART_IS7816_INITD. */
3773 #define BS_UART_IS7816_INITD (1U) /*!< Bit field size in bits for UART_IS7816_INITD. */
3775 /*! @brief Read current value of the UART_IS7816_INITD field. */
3776 #define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
3778 /*! @brief Format value for bitfield UART_IS7816_INITD. */
3779 #define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD)
3781 /*! @brief Set the INITD field to a new value. */
3782 #define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
3786 * @name Register UART_IS7816, field BWT[5] (W1C)
3788 * Indicates that the block wait time, the time between the leading edge of
3789 * first received character of a block and the leading edge of the last character the
3790 * previously transmitted block, has exceeded the programmed value. This flag
3791 * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
3794 * - 0 - Block wait time (BWT) has not been violated.
3795 * - 1 - Block wait time (BWT) has been violated.
3798 #define BP_UART_IS7816_BWT (5U) /*!< Bit position for UART_IS7816_BWT. */
3799 #define BM_UART_IS7816_BWT (0x20U) /*!< Bit mask for UART_IS7816_BWT. */
3800 #define BS_UART_IS7816_BWT (1U) /*!< Bit field size in bits for UART_IS7816_BWT. */
3802 /*! @brief Read current value of the UART_IS7816_BWT field. */
3803 #define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
3805 /*! @brief Format value for bitfield UART_IS7816_BWT. */
3806 #define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT)
3808 /*! @brief Set the BWT field to a new value. */
3809 #define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
3813 * @name Register UART_IS7816, field CWT[6] (W1C)
3815 * Indicates that the character wait time, the time between the leading edges of
3816 * two consecutive characters in a block, has exceeded the programmed value.
3817 * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
3821 * - 0 - Character wait time (CWT) has not been violated.
3822 * - 1 - Character wait time (CWT) has been violated.
3825 #define BP_UART_IS7816_CWT (6U) /*!< Bit position for UART_IS7816_CWT. */
3826 #define BM_UART_IS7816_CWT (0x40U) /*!< Bit mask for UART_IS7816_CWT. */
3827 #define BS_UART_IS7816_CWT (1U) /*!< Bit field size in bits for UART_IS7816_CWT. */
3829 /*! @brief Read current value of the UART_IS7816_CWT field. */
3830 #define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
3832 /*! @brief Format value for bitfield UART_IS7816_CWT. */
3833 #define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT)
3835 /*! @brief Set the CWT field to a new value. */
3836 #define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
3840 * @name Register UART_IS7816, field WT[7] (W1C)
3842 * Indicates that the wait time, the time between the leading edge of a
3843 * character being transmitted and the leading edge of the next response character, has
3844 * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
3845 * This interrupt is cleared by writing 1.
3848 * - 0 - Wait time (WT) has not been violated.
3849 * - 1 - Wait time (WT) has been violated.
3852 #define BP_UART_IS7816_WT (7U) /*!< Bit position for UART_IS7816_WT. */
3853 #define BM_UART_IS7816_WT (0x80U) /*!< Bit mask for UART_IS7816_WT. */
3854 #define BS_UART_IS7816_WT (1U) /*!< Bit field size in bits for UART_IS7816_WT. */
3856 /*! @brief Read current value of the UART_IS7816_WT field. */
3857 #define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
3859 /*! @brief Format value for bitfield UART_IS7816_WT. */
3860 #define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT)
3862 /*! @brief Set the WT field to a new value. */
3863 #define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
3866 /*******************************************************************************
3867 * HW_UART_WP7816 - UART 7816 Wait Parameter Register
3868 ******************************************************************************/
3871 * @brief HW_UART_WP7816 - UART 7816 Wait Parameter Register (RW)
3873 * Reset value: 0x00U
3875 * The WP7816 register contains the WTX variable used in the generation of the
3876 * block wait timer. This register may be read at any time. This register must be
3877 * written to only when C7816[ISO_7816E] is not set.
3879 typedef union _hw_uart_wp7816
3882 struct _hw_uart_wp7816_bitfields
3884 uint8_t WTX
: 8; /*!< [7:0] Wait Time Multiplier (C7816[TTYPE] = 1) */
3889 * @name Constants and macros for entire UART_WP7816 register
3892 #define HW_UART_WP7816_ADDR(x) ((x) + 0x1BU)
3894 #define HW_UART_WP7816(x) (*(__IO hw_uart_wp7816_t *) HW_UART_WP7816_ADDR(x))
3895 #define HW_UART_WP7816_RD(x) (HW_UART_WP7816(x).U)
3896 #define HW_UART_WP7816_WR(x, v) (HW_UART_WP7816(x).U = (v))
3897 #define HW_UART_WP7816_SET(x, v) (HW_UART_WP7816_WR(x, HW_UART_WP7816_RD(x) | (v)))
3898 #define HW_UART_WP7816_CLR(x, v) (HW_UART_WP7816_WR(x, HW_UART_WP7816_RD(x) & ~(v)))
3899 #define HW_UART_WP7816_TOG(x, v) (HW_UART_WP7816_WR(x, HW_UART_WP7816_RD(x) ^ (v)))
3903 * Constants & macros for individual UART_WP7816 bitfields
3907 * @name Register UART_WP7816, field WTX[7:0] (RW)
3909 * Used to calculate the value used for the BWT counter. It represents a value
3910 * between 0 and 255. This value is used only when C7816[TTYPE] = 1. See Wait time
3911 * and guard time parameters.
3914 #define BP_UART_WP7816_WTX (0U) /*!< Bit position for UART_WP7816_WTX. */
3915 #define BM_UART_WP7816_WTX (0xFFU) /*!< Bit mask for UART_WP7816_WTX. */
3916 #define BS_UART_WP7816_WTX (8U) /*!< Bit field size in bits for UART_WP7816_WTX. */
3918 /*! @brief Read current value of the UART_WP7816_WTX field. */
3919 #define BR_UART_WP7816_WTX(x) (HW_UART_WP7816(x).U)
3921 /*! @brief Format value for bitfield UART_WP7816_WTX. */
3922 #define BF_UART_WP7816_WTX(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816_WTX) & BM_UART_WP7816_WTX)
3924 /*! @brief Set the WTX field to a new value. */
3925 #define BW_UART_WP7816_WTX(x, v) (HW_UART_WP7816_WR(x, v))
3928 /*******************************************************************************
3929 * HW_UART_WN7816 - UART 7816 Wait N Register
3930 ******************************************************************************/
3933 * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
3935 * Reset value: 0x00U
3937 * The WN7816 register contains a parameter that is used in the calculation of
3938 * the guard time counter. This register may be read at any time. This register
3939 * must be written to only when C7816[ISO_7816E] is not set.
3941 typedef union _hw_uart_wn7816
3944 struct _hw_uart_wn7816_bitfields
3946 uint8_t GTN
: 8; /*!< [7:0] Guard Band N */
3951 * @name Constants and macros for entire UART_WN7816 register
3954 #define HW_UART_WN7816_ADDR(x) ((x) + 0x1CU)
3956 #define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x))
3957 #define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U)
3958 #define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v))
3959 #define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v)))
3960 #define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
3961 #define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v)))
3965 * Constants & macros for individual UART_WN7816 bitfields
3969 * @name Register UART_WN7816, field GTN[7:0] (RW)
3971 * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
3972 * value represents an integer number between 0 and 255. See Wait time and guard
3976 #define BP_UART_WN7816_GTN (0U) /*!< Bit position for UART_WN7816_GTN. */
3977 #define BM_UART_WN7816_GTN (0xFFU) /*!< Bit mask for UART_WN7816_GTN. */
3978 #define BS_UART_WN7816_GTN (8U) /*!< Bit field size in bits for UART_WN7816_GTN. */
3980 /*! @brief Read current value of the UART_WN7816_GTN field. */
3981 #define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
3983 /*! @brief Format value for bitfield UART_WN7816_GTN. */
3984 #define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN)
3986 /*! @brief Set the GTN field to a new value. */
3987 #define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
3990 /*******************************************************************************
3991 * HW_UART_WF7816 - UART 7816 Wait FD Register
3992 ******************************************************************************/
3995 * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
3997 * Reset value: 0x01U
3999 * The WF7816 contains parameters that are used in the generation of various
4000 * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
4001 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4003 typedef union _hw_uart_wf7816
4006 struct _hw_uart_wf7816_bitfields
4008 uint8_t GTFD
: 8; /*!< [7:0] FD Multiplier */
4013 * @name Constants and macros for entire UART_WF7816 register
4016 #define HW_UART_WF7816_ADDR(x) ((x) + 0x1DU)
4018 #define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x))
4019 #define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U)
4020 #define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v))
4021 #define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v)))
4022 #define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
4023 #define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v)))
4027 * Constants & macros for individual UART_WF7816 bitfields
4031 * @name Register UART_WF7816, field GTFD[7:0] (RW)
4033 * Used as another multiplier in the calculation of BWT. This value represents a
4034 * number between 1 and 255. The value of 0 is invalid. This value is not used
4035 * in baud rate generation. See Wait time and guard time parameters and Baud rate
4039 #define BP_UART_WF7816_GTFD (0U) /*!< Bit position for UART_WF7816_GTFD. */
4040 #define BM_UART_WF7816_GTFD (0xFFU) /*!< Bit mask for UART_WF7816_GTFD. */
4041 #define BS_UART_WF7816_GTFD (8U) /*!< Bit field size in bits for UART_WF7816_GTFD. */
4043 /*! @brief Read current value of the UART_WF7816_GTFD field. */
4044 #define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
4046 /*! @brief Format value for bitfield UART_WF7816_GTFD. */
4047 #define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD)
4049 /*! @brief Set the GTFD field to a new value. */
4050 #define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
4053 /*******************************************************************************
4054 * HW_UART_ET7816 - UART 7816 Error Threshold Register
4055 ******************************************************************************/
4058 * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
4060 * Reset value: 0x00U
4062 * The ET7816 register contains fields that determine the number of NACKs that
4063 * must be received or transmitted before the host processor is notified. This
4064 * register may be read at anytime. This register must be written to only when
4065 * C7816[ISO_7816E] is not set.
4067 typedef union _hw_uart_et7816
4070 struct _hw_uart_et7816_bitfields
4072 uint8_t RXTHRESHOLD
: 4; /*!< [3:0] Receive NACK Threshold */
4073 uint8_t TXTHRESHOLD
: 4; /*!< [7:4] Transmit NACK Threshold */
4078 * @name Constants and macros for entire UART_ET7816 register
4081 #define HW_UART_ET7816_ADDR(x) ((x) + 0x1EU)
4083 #define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x))
4084 #define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U)
4085 #define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v))
4086 #define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v)))
4087 #define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
4088 #define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v)))
4092 * Constants & macros for individual UART_ET7816 bitfields
4096 * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
4098 * The value written to this field indicates the maximum number of consecutive
4099 * NACKs generated as a result of a parity error or receiver buffer overruns
4100 * before the host processor is notified. After the counter exceeds that value in the
4101 * field, the IS7816[RXT] is asserted. This field is meaningful only when
4102 * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
4103 * NACKs that have been transmitted since the last successful reception. This
4104 * counter saturates at 4'hF and does not wrap around. Regardless of the number of
4105 * NACKs sent, the UART continues to receive valid packets indefinitely. For
4106 * additional information, see IS7816[RXT] field description.
4109 #define BP_UART_ET7816_RXTHRESHOLD (0U) /*!< Bit position for UART_ET7816_RXTHRESHOLD. */
4110 #define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /*!< Bit mask for UART_ET7816_RXTHRESHOLD. */
4111 #define BS_UART_ET7816_RXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. */
4113 /*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
4114 #define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
4116 /*! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. */
4117 #define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD)
4119 /*! @brief Set the RXTHRESHOLD field to a new value. */
4120 #define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v)))
4124 * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
4126 * The value written to this field indicates the maximum number of failed
4127 * attempts (NACKs) a transmitted character can have before the host processor is
4128 * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
4129 * The value read from this field represents the number of consecutive NACKs
4130 * that have been received since the last successful transmission. This counter
4131 * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
4132 * received, the UART continues to retransmit indefinitely. This flag only
4133 * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
4137 * - 0 - TXT asserts on the first NACK that is received.
4138 * - 1 - TXT asserts on the second NACK that is received.
4141 #define BP_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit position for UART_ET7816_TXTHRESHOLD. */
4142 #define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /*!< Bit mask for UART_ET7816_TXTHRESHOLD. */
4143 #define BS_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. */
4145 /*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
4146 #define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
4148 /*! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. */
4149 #define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD)
4151 /*! @brief Set the TXTHRESHOLD field to a new value. */
4152 #define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v)))
4155 /*******************************************************************************
4156 * HW_UART_TL7816 - UART 7816 Transmit Length Register
4157 ******************************************************************************/
4160 * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
4162 * Reset value: 0x00U
4164 * The TL7816 register is used to indicate the number of characters contained in
4165 * the block being transmitted. This register is used only when C7816[TTYPE] =
4166 * 1. This register may be read at anytime. This register must be written only
4167 * when C2[TE] is not enabled.
4169 typedef union _hw_uart_tl7816
4172 struct _hw_uart_tl7816_bitfields
4174 uint8_t TLEN
: 8; /*!< [7:0] Transmit Length */
4179 * @name Constants and macros for entire UART_TL7816 register
4182 #define HW_UART_TL7816_ADDR(x) ((x) + 0x1FU)
4184 #define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x))
4185 #define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U)
4186 #define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v))
4187 #define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v)))
4188 #define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
4189 #define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v)))
4193 * Constants & macros for individual UART_TL7816 bitfields
4197 * @name Register UART_TL7816, field TLEN[7:0] (RW)
4199 * This value plus four indicates the number of characters contained in the
4200 * block being transmitted. This register is automatically decremented by 1 for each
4201 * character in the information field portion of the block. Additionally, this
4202 * register is automatically decremented by 1 for the first character of a CRC in
4203 * the epilogue field. Therefore, this register must be programmed with the number
4204 * of bytes in the data packet if an LRC is being transmitted, and the number of
4205 * bytes + 1 if a CRC is being transmitted. This register is not decremented for
4206 * characters that are assumed to be part of the Prologue field, that is, the
4207 * first three characters transmitted in a block, or the LRC or last CRC character
4208 * in the Epilogue field, that is, the last character transmitted. This field
4209 * must be programed or adjusted only when C2[TE] is cleared.
4212 #define BP_UART_TL7816_TLEN (0U) /*!< Bit position for UART_TL7816_TLEN. */
4213 #define BM_UART_TL7816_TLEN (0xFFU) /*!< Bit mask for UART_TL7816_TLEN. */
4214 #define BS_UART_TL7816_TLEN (8U) /*!< Bit field size in bits for UART_TL7816_TLEN. */
4216 /*! @brief Read current value of the UART_TL7816_TLEN field. */
4217 #define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
4219 /*! @brief Format value for bitfield UART_TL7816_TLEN. */
4220 #define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN)
4222 /*! @brief Set the TLEN field to a new value. */
4223 #define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
4226 /*******************************************************************************
4227 * HW_UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A
4228 ******************************************************************************/
4231 * @brief HW_UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A (RW)
4233 * Reset value: 0x00U
4235 * The AP7816A_T0 register contains variables used in the generation of the ATR
4236 * Duration Timer. This register may be read at any time. This register must be
4237 * written to only when C7816[ISO_7816E] is not set, except when writing 0 to
4238 * clear the ADT Counter. The ADT Counter starts counting on detection of the
4239 * complete TS Character. It must be noted that by this time, exactly 10 ETUs have
4240 * elapsed since the start bit of the TS character. The user must take this into
4241 * account while programming this register.
4243 typedef union _hw_uart_ap7816a_t0
4246 struct _hw_uart_ap7816a_t0_bitfields
4248 uint8_t ADTI_H
: 8; /*!< [7:0] ATR Duration Time Integer High
4249 * (C7816[TTYPE] = 0) */
4251 } hw_uart_ap7816a_t0_t
;
4254 * @name Constants and macros for entire UART_AP7816A_T0 register
4257 #define HW_UART_AP7816A_T0_ADDR(x) ((x) + 0x3AU)
4259 #define HW_UART_AP7816A_T0(x) (*(__IO hw_uart_ap7816a_t0_t *) HW_UART_AP7816A_T0_ADDR(x))
4260 #define HW_UART_AP7816A_T0_RD(x) (HW_UART_AP7816A_T0(x).U)
4261 #define HW_UART_AP7816A_T0_WR(x, v) (HW_UART_AP7816A_T0(x).U = (v))
4262 #define HW_UART_AP7816A_T0_SET(x, v) (HW_UART_AP7816A_T0_WR(x, HW_UART_AP7816A_T0_RD(x) | (v)))
4263 #define HW_UART_AP7816A_T0_CLR(x, v) (HW_UART_AP7816A_T0_WR(x, HW_UART_AP7816A_T0_RD(x) & ~(v)))
4264 #define HW_UART_AP7816A_T0_TOG(x, v) (HW_UART_AP7816A_T0_WR(x, HW_UART_AP7816A_T0_RD(x) ^ (v)))
4268 * Constants & macros for individual UART_AP7816A_T0 bitfields
4272 * @name Register UART_AP7816A_T0, field ADTI_H[7:0] (RW)
4274 * Used to calculate the value used for the ADT Counter. This register field
4275 * provides the most significant byte of the 16 bit ATR Duration Time Integer field
4276 * ADTI formed by {AP7816A_T0[ADTI_H], AP7816B_T0[ADTI_L]}. Programming a value
4277 * of ADTI = 0 disables the ADT counter. This value is used only when C7816[TTYPE]
4278 * = 0. See ATR Duration Time Counter.
4281 #define BP_UART_AP7816A_T0_ADTI_H (0U) /*!< Bit position for UART_AP7816A_T0_ADTI_H. */
4282 #define BM_UART_AP7816A_T0_ADTI_H (0xFFU) /*!< Bit mask for UART_AP7816A_T0_ADTI_H. */
4283 #define BS_UART_AP7816A_T0_ADTI_H (8U) /*!< Bit field size in bits for UART_AP7816A_T0_ADTI_H. */
4285 /*! @brief Read current value of the UART_AP7816A_T0_ADTI_H field. */
4286 #define BR_UART_AP7816A_T0_ADTI_H(x) (HW_UART_AP7816A_T0(x).U)
4288 /*! @brief Format value for bitfield UART_AP7816A_T0_ADTI_H. */
4289 #define BF_UART_AP7816A_T0_ADTI_H(v) ((uint8_t)((uint8_t)(v) << BP_UART_AP7816A_T0_ADTI_H) & BM_UART_AP7816A_T0_ADTI_H)
4291 /*! @brief Set the ADTI_H field to a new value. */
4292 #define BW_UART_AP7816A_T0_ADTI_H(x, v) (HW_UART_AP7816A_T0_WR(x, v))
4295 /*******************************************************************************
4296 * HW_UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B
4297 ******************************************************************************/
4300 * @brief HW_UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B (RW)
4302 * Reset value: 0x00U
4304 * The AP7816B_T0 register contains variables used in the generation of the ATR
4305 * Duration Timer. This register may be read at any time. This register must be
4306 * written to only when C7816[ISO_7816E] is not set, except when writing 0 to
4307 * clear the ADT Counter. The ADT Counter starts counting on detection of the
4308 * complete TS Character. It must be noted that by this time, exactly 10 ETUs have
4309 * elapsed since the start bit of the TS character. The user must take this into
4310 * account while programming this register.
4312 typedef union _hw_uart_ap7816b_t0
4315 struct _hw_uart_ap7816b_t0_bitfields
4317 uint8_t ADTI_L
: 8; /*!< [7:0] ATR Duration Time Integer Low
4318 * (C7816[TTYPE] = 0) */
4320 } hw_uart_ap7816b_t0_t
;
4323 * @name Constants and macros for entire UART_AP7816B_T0 register
4326 #define HW_UART_AP7816B_T0_ADDR(x) ((x) + 0x3BU)
4328 #define HW_UART_AP7816B_T0(x) (*(__IO hw_uart_ap7816b_t0_t *) HW_UART_AP7816B_T0_ADDR(x))
4329 #define HW_UART_AP7816B_T0_RD(x) (HW_UART_AP7816B_T0(x).U)
4330 #define HW_UART_AP7816B_T0_WR(x, v) (HW_UART_AP7816B_T0(x).U = (v))
4331 #define HW_UART_AP7816B_T0_SET(x, v) (HW_UART_AP7816B_T0_WR(x, HW_UART_AP7816B_T0_RD(x) | (v)))
4332 #define HW_UART_AP7816B_T0_CLR(x, v) (HW_UART_AP7816B_T0_WR(x, HW_UART_AP7816B_T0_RD(x) & ~(v)))
4333 #define HW_UART_AP7816B_T0_TOG(x, v) (HW_UART_AP7816B_T0_WR(x, HW_UART_AP7816B_T0_RD(x) ^ (v)))
4337 * Constants & macros for individual UART_AP7816B_T0 bitfields
4341 * @name Register UART_AP7816B_T0, field ADTI_L[7:0] (RW)
4343 * Used to calculate the value used for the ADT counter. This register field
4344 * provides the least significant byte of the 16 bit ATR Duration Time Integer field
4345 * ADTI formed by {AP7816A_T0[ADTI_H], AP7816B_T0[ADTI_L]}. Programming a value
4346 * of ADTI = 0 disables the ADT counter. This value is used only when
4347 * C7816[TTYPE] = 0. See ATR Duration Time Counter.
4350 #define BP_UART_AP7816B_T0_ADTI_L (0U) /*!< Bit position for UART_AP7816B_T0_ADTI_L. */
4351 #define BM_UART_AP7816B_T0_ADTI_L (0xFFU) /*!< Bit mask for UART_AP7816B_T0_ADTI_L. */
4352 #define BS_UART_AP7816B_T0_ADTI_L (8U) /*!< Bit field size in bits for UART_AP7816B_T0_ADTI_L. */
4354 /*! @brief Read current value of the UART_AP7816B_T0_ADTI_L field. */
4355 #define BR_UART_AP7816B_T0_ADTI_L(x) (HW_UART_AP7816B_T0(x).U)
4357 /*! @brief Format value for bitfield UART_AP7816B_T0_ADTI_L. */
4358 #define BF_UART_AP7816B_T0_ADTI_L(v) ((uint8_t)((uint8_t)(v) << BP_UART_AP7816B_T0_ADTI_L) & BM_UART_AP7816B_T0_ADTI_L)
4360 /*! @brief Set the ADTI_L field to a new value. */
4361 #define BW_UART_AP7816B_T0_ADTI_L(x, v) (HW_UART_AP7816B_T0_WR(x, v))
4364 /*******************************************************************************
4365 * HW_UART_WP7816A_T0 - UART 7816 Wait Parameter Register A
4366 ******************************************************************************/
4369 * @brief HW_UART_WP7816A_T0 - UART 7816 Wait Parameter Register A (RW)
4371 * Reset value: 0x00U
4373 * The WP7816A_T0 register contains constants used in the generation of various
4374 * wait time counters. To save register space, this register is used differently
4375 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
4376 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4378 typedef union _hw_uart_wp7816a_t0
4381 struct _hw_uart_wp7816a_t0_bitfields
4383 uint8_t WI_H
: 8; /*!< [7:0] Wait Time Integer High (C7816[TTYPE] =
4386 } hw_uart_wp7816a_t0_t
;
4389 * @name Constants and macros for entire UART_WP7816A_T0 register
4392 #define HW_UART_WP7816A_T0_ADDR(x) ((x) + 0x3CU)
4394 #define HW_UART_WP7816A_T0(x) (*(__IO hw_uart_wp7816a_t0_t *) HW_UART_WP7816A_T0_ADDR(x))
4395 #define HW_UART_WP7816A_T0_RD(x) (HW_UART_WP7816A_T0(x).U)
4396 #define HW_UART_WP7816A_T0_WR(x, v) (HW_UART_WP7816A_T0(x).U = (v))
4397 #define HW_UART_WP7816A_T0_SET(x, v) (HW_UART_WP7816A_T0_WR(x, HW_UART_WP7816A_T0_RD(x) | (v)))
4398 #define HW_UART_WP7816A_T0_CLR(x, v) (HW_UART_WP7816A_T0_WR(x, HW_UART_WP7816A_T0_RD(x) & ~(v)))
4399 #define HW_UART_WP7816A_T0_TOG(x, v) (HW_UART_WP7816A_T0_WR(x, HW_UART_WP7816A_T0_RD(x) ^ (v)))
4403 * Constants & macros for individual UART_WP7816A_T0 bitfields
4407 * @name Register UART_WP7816A_T0, field WI_H[7:0] (RW)
4409 * Used to calculate the value used for the WT counter. This register field
4410 * provides the most significant byte of the 16 bit Wait Time Integer field WI formed
4411 * by {WP7816A_T0[WI_H], WP7816B_T0[WI_L]}. The value of WI = 0 is invalid and
4412 * must not be programmed. This value is used only when C7816[TTYPE] = 0. See Wait
4413 * time and guard time parameters.
4416 #define BP_UART_WP7816A_T0_WI_H (0U) /*!< Bit position for UART_WP7816A_T0_WI_H. */
4417 #define BM_UART_WP7816A_T0_WI_H (0xFFU) /*!< Bit mask for UART_WP7816A_T0_WI_H. */
4418 #define BS_UART_WP7816A_T0_WI_H (8U) /*!< Bit field size in bits for UART_WP7816A_T0_WI_H. */
4420 /*! @brief Read current value of the UART_WP7816A_T0_WI_H field. */
4421 #define BR_UART_WP7816A_T0_WI_H(x) (HW_UART_WP7816A_T0(x).U)
4423 /*! @brief Format value for bitfield UART_WP7816A_T0_WI_H. */
4424 #define BF_UART_WP7816A_T0_WI_H(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816A_T0_WI_H) & BM_UART_WP7816A_T0_WI_H)
4426 /*! @brief Set the WI_H field to a new value. */
4427 #define BW_UART_WP7816A_T0_WI_H(x, v) (HW_UART_WP7816A_T0_WR(x, v))
4429 /*******************************************************************************
4430 * HW_UART_WP7816B_T0 - UART 7816 Wait Parameter Register B
4431 ******************************************************************************/
4434 * @brief HW_UART_WP7816B_T0 - UART 7816 Wait Parameter Register B (RW)
4436 * Reset value: 0x14U
4438 * The WP7816B_T0 register contains constants used in the generation of various
4439 * wait time counters. To save register space, this register is used differently
4440 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
4441 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4443 typedef union _hw_uart_wp7816b_t0
4446 struct _hw_uart_wp7816b_t0_bitfields
4448 uint8_t WI_L
: 8; /*!< [7:0] Wait Time Integer Low (C7816[TTYPE] = 0)
4451 } hw_uart_wp7816b_t0_t
;
4454 * @name Constants and macros for entire UART_WP7816B_T0 register
4457 #define HW_UART_WP7816B_T0_ADDR(x) ((x) + 0x3DU)
4459 #define HW_UART_WP7816B_T0(x) (*(__IO hw_uart_wp7816b_t0_t *) HW_UART_WP7816B_T0_ADDR(x))
4460 #define HW_UART_WP7816B_T0_RD(x) (HW_UART_WP7816B_T0(x).U)
4461 #define HW_UART_WP7816B_T0_WR(x, v) (HW_UART_WP7816B_T0(x).U = (v))
4462 #define HW_UART_WP7816B_T0_SET(x, v) (HW_UART_WP7816B_T0_WR(x, HW_UART_WP7816B_T0_RD(x) | (v)))
4463 #define HW_UART_WP7816B_T0_CLR(x, v) (HW_UART_WP7816B_T0_WR(x, HW_UART_WP7816B_T0_RD(x) & ~(v)))
4464 #define HW_UART_WP7816B_T0_TOG(x, v) (HW_UART_WP7816B_T0_WR(x, HW_UART_WP7816B_T0_RD(x) ^ (v)))
4468 * Constants & macros for individual UART_WP7816B_T0 bitfields
4472 * @name Register UART_WP7816B_T0, field WI_L[7:0] (RW)
4474 * Used to calculate the value used for the WT counter. This register field
4475 * provides the least significant byte of the 16 bit Wait Time Integer field WI
4476 * formed by {WP7816A_T0[WI_H], WP7816B_T0[WI_L]} . The value of WI = 0 is invalid and
4477 * must not be programmed. This value is used only when C7816[TTYPE] = 0. See
4478 * Wait time and guard time parameters.
4481 #define BP_UART_WP7816B_T0_WI_L (0U) /*!< Bit position for UART_WP7816B_T0_WI_L. */
4482 #define BM_UART_WP7816B_T0_WI_L (0xFFU) /*!< Bit mask for UART_WP7816B_T0_WI_L. */
4483 #define BS_UART_WP7816B_T0_WI_L (8U) /*!< Bit field size in bits for UART_WP7816B_T0_WI_L. */
4485 /*! @brief Read current value of the UART_WP7816B_T0_WI_L field. */
4486 #define BR_UART_WP7816B_T0_WI_L(x) (HW_UART_WP7816B_T0(x).U)
4488 /*! @brief Format value for bitfield UART_WP7816B_T0_WI_L. */
4489 #define BF_UART_WP7816B_T0_WI_L(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816B_T0_WI_L) & BM_UART_WP7816B_T0_WI_L)
4491 /*! @brief Set the WI_L field to a new value. */
4492 #define BW_UART_WP7816B_T0_WI_L(x, v) (HW_UART_WP7816B_T0_WR(x, v))
4494 /*******************************************************************************
4495 * HW_UART_WP7816A_T1 - UART 7816 Wait Parameter Register A
4496 ******************************************************************************/
4499 * @brief HW_UART_WP7816A_T1 - UART 7816 Wait Parameter Register A (RW)
4501 * Reset value: 0x00U
4503 * The WP7816A_T1 register contains constants used in the generation of various
4504 * wait time counters. To save register space, this register is used differently
4505 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
4506 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4508 typedef union _hw_uart_wp7816a_t1
4511 struct _hw_uart_wp7816a_t1_bitfields
4513 uint8_t BWI_H
: 8; /*!< [7:0] Block Wait Time Integer High
4514 * (C7816[TTYPE] = 1) */
4516 } hw_uart_wp7816a_t1_t
;
4519 * @name Constants and macros for entire UART_WP7816A_T1 register
4522 #define HW_UART_WP7816A_T1_ADDR(x) ((x) + 0x3CU)
4524 #define HW_UART_WP7816A_T1(x) (*(__IO hw_uart_wp7816a_t1_t *) HW_UART_WP7816A_T1_ADDR(x))
4525 #define HW_UART_WP7816A_T1_RD(x) (HW_UART_WP7816A_T1(x).U)
4526 #define HW_UART_WP7816A_T1_WR(x, v) (HW_UART_WP7816A_T1(x).U = (v))
4527 #define HW_UART_WP7816A_T1_SET(x, v) (HW_UART_WP7816A_T1_WR(x, HW_UART_WP7816A_T1_RD(x) | (v)))
4528 #define HW_UART_WP7816A_T1_CLR(x, v) (HW_UART_WP7816A_T1_WR(x, HW_UART_WP7816A_T1_RD(x) & ~(v)))
4529 #define HW_UART_WP7816A_T1_TOG(x, v) (HW_UART_WP7816A_T1_WR(x, HW_UART_WP7816A_T1_RD(x) ^ (v)))
4533 * Constants & macros for individual UART_WP7816A_T1 bitfields
4537 * @name Register UART_WP7816A_T1, field BWI_H[7:0] (RW)
4539 * Used to calculate the value used for the BWT counter. This register field
4540 * provides the most significant byte of the 16 bit Block Wait Time Integer field
4541 * BWI formed by {WP7816A_T1[BWI_H], WP7816B_T1[BWI_L]}. The value of BWI = 0 is
4542 * invalid and should not be programmed. This value is used only when C7816[TTYPE]
4543 * = 1. See Wait time and guard time parameters.
4546 #define BP_UART_WP7816A_T1_BWI_H (0U) /*!< Bit position for UART_WP7816A_T1_BWI_H. */
4547 #define BM_UART_WP7816A_T1_BWI_H (0xFFU) /*!< Bit mask for UART_WP7816A_T1_BWI_H. */
4548 #define BS_UART_WP7816A_T1_BWI_H (8U) /*!< Bit field size in bits for UART_WP7816A_T1_BWI_H. */
4550 /*! @brief Read current value of the UART_WP7816A_T1_BWI_H field. */
4551 #define BR_UART_WP7816A_T1_BWI_H(x) (HW_UART_WP7816A_T1(x).U)
4553 /*! @brief Format value for bitfield UART_WP7816A_T1_BWI_H. */
4554 #define BF_UART_WP7816A_T1_BWI_H(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816A_T1_BWI_H) & BM_UART_WP7816A_T1_BWI_H)
4556 /*! @brief Set the BWI_H field to a new value. */
4557 #define BW_UART_WP7816A_T1_BWI_H(x, v) (HW_UART_WP7816A_T1_WR(x, v))
4559 /*******************************************************************************
4560 * HW_UART_WP7816B_T1 - UART 7816 Wait Parameter Register B
4561 ******************************************************************************/
4564 * @brief HW_UART_WP7816B_T1 - UART 7816 Wait Parameter Register B (RW)
4566 * Reset value: 0x14U
4568 * The WP7816B_T1 register contains constants used in the generation of various
4569 * wait time counters. To save register space, this register is used differently
4570 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
4571 * time. This register must be written to only when C7816[ISO_7816E] is not set.
4573 typedef union _hw_uart_wp7816b_t1
4576 struct _hw_uart_wp7816b_t1_bitfields
4578 uint8_t BWI_L
: 8; /*!< [7:0] Block Wait Time Integer Low
4579 * (C7816[TTYPE] = 1) */
4581 } hw_uart_wp7816b_t1_t
;
4584 * @name Constants and macros for entire UART_WP7816B_T1 register
4587 #define HW_UART_WP7816B_T1_ADDR(x) ((x) + 0x3DU)
4589 #define HW_UART_WP7816B_T1(x) (*(__IO hw_uart_wp7816b_t1_t *) HW_UART_WP7816B_T1_ADDR(x))
4590 #define HW_UART_WP7816B_T1_RD(x) (HW_UART_WP7816B_T1(x).U)
4591 #define HW_UART_WP7816B_T1_WR(x, v) (HW_UART_WP7816B_T1(x).U = (v))
4592 #define HW_UART_WP7816B_T1_SET(x, v) (HW_UART_WP7816B_T1_WR(x, HW_UART_WP7816B_T1_RD(x) | (v)))
4593 #define HW_UART_WP7816B_T1_CLR(x, v) (HW_UART_WP7816B_T1_WR(x, HW_UART_WP7816B_T1_RD(x) & ~(v)))
4594 #define HW_UART_WP7816B_T1_TOG(x, v) (HW_UART_WP7816B_T1_WR(x, HW_UART_WP7816B_T1_RD(x) ^ (v)))
4598 * Constants & macros for individual UART_WP7816B_T1 bitfields
4602 * @name Register UART_WP7816B_T1, field BWI_L[7:0] (RW)
4604 * Used to calculate the value used for the BWT counter. This register field
4605 * provides the least significant byte of the 16 bit Block Wait Time Integer field
4606 * BWI formed by {WP7816A_T1[BWI_H], WP7816B_T1[BWI_L]}. The value of BWI = 0 is
4607 * invalid and should not be programmed. This value is used only when C7816[TTYPE]
4608 * = 1. See Wait time and guard time parameters.
4611 #define BP_UART_WP7816B_T1_BWI_L (0U) /*!< Bit position for UART_WP7816B_T1_BWI_L. */
4612 #define BM_UART_WP7816B_T1_BWI_L (0xFFU) /*!< Bit mask for UART_WP7816B_T1_BWI_L. */
4613 #define BS_UART_WP7816B_T1_BWI_L (8U) /*!< Bit field size in bits for UART_WP7816B_T1_BWI_L. */
4615 /*! @brief Read current value of the UART_WP7816B_T1_BWI_L field. */
4616 #define BR_UART_WP7816B_T1_BWI_L(x) (HW_UART_WP7816B_T1(x).U)
4618 /*! @brief Format value for bitfield UART_WP7816B_T1_BWI_L. */
4619 #define BF_UART_WP7816B_T1_BWI_L(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816B_T1_BWI_L) & BM_UART_WP7816B_T1_BWI_L)
4621 /*! @brief Set the BWI_L field to a new value. */
4622 #define BW_UART_WP7816B_T1_BWI_L(x, v) (HW_UART_WP7816B_T1_WR(x, v))
4625 /*******************************************************************************
4626 * HW_UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register
4627 ******************************************************************************/
4630 * @brief HW_UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register (RW)
4632 * Reset value: 0x06U
4634 * The WGP7816_T1 register contains constants used in the generation of various
4635 * wait and guard timer counters. This register may be read at any time. This
4636 * register must be written to only when C7816[ISO_7816E] is not set.
4638 typedef union _hw_uart_wgp7816_t1
4641 struct _hw_uart_wgp7816_t1_bitfields
4643 uint8_t BGI
: 4; /*!< [3:0] Block Guard Time Integer (C7816[TTYPE] =
4645 uint8_t CWI1
: 4; /*!< [7:4] Character Wait Time Integer 1
4646 * (C7816[TTYPE] = 1) */
4648 } hw_uart_wgp7816_t1_t
;
4651 * @name Constants and macros for entire UART_WGP7816_T1 register
4654 #define HW_UART_WGP7816_T1_ADDR(x) ((x) + 0x3EU)
4656 #define HW_UART_WGP7816_T1(x) (*(__IO hw_uart_wgp7816_t1_t *) HW_UART_WGP7816_T1_ADDR(x))
4657 #define HW_UART_WGP7816_T1_RD(x) (HW_UART_WGP7816_T1(x).U)
4658 #define HW_UART_WGP7816_T1_WR(x, v) (HW_UART_WGP7816_T1(x).U = (v))
4659 #define HW_UART_WGP7816_T1_SET(x, v) (HW_UART_WGP7816_T1_WR(x, HW_UART_WGP7816_T1_RD(x) | (v)))
4660 #define HW_UART_WGP7816_T1_CLR(x, v) (HW_UART_WGP7816_T1_WR(x, HW_UART_WGP7816_T1_RD(x) & ~(v)))
4661 #define HW_UART_WGP7816_T1_TOG(x, v) (HW_UART_WGP7816_T1_WR(x, HW_UART_WGP7816_T1_RD(x) ^ (v)))
4665 * Constants & macros for individual UART_WGP7816_T1 bitfields
4669 * @name Register UART_WGP7816_T1, field BGI[3:0] (RW)
4671 * Used to calculate the value used for the BGT counter. It represent a value
4672 * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
4673 * and guard time parameters .
4676 #define BP_UART_WGP7816_T1_BGI (0U) /*!< Bit position for UART_WGP7816_T1_BGI. */
4677 #define BM_UART_WGP7816_T1_BGI (0x0FU) /*!< Bit mask for UART_WGP7816_T1_BGI. */
4678 #define BS_UART_WGP7816_T1_BGI (4U) /*!< Bit field size in bits for UART_WGP7816_T1_BGI. */
4680 /*! @brief Read current value of the UART_WGP7816_T1_BGI field. */
4681 #define BR_UART_WGP7816_T1_BGI(x) (HW_UART_WGP7816_T1(x).B.BGI)
4683 /*! @brief Format value for bitfield UART_WGP7816_T1_BGI. */
4684 #define BF_UART_WGP7816_T1_BGI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WGP7816_T1_BGI) & BM_UART_WGP7816_T1_BGI)
4686 /*! @brief Set the BGI field to a new value. */
4687 #define BW_UART_WGP7816_T1_BGI(x, v) (HW_UART_WGP7816_T1_WR(x, (HW_UART_WGP7816_T1_RD(x) & ~BM_UART_WGP7816_T1_BGI) | BF_UART_WGP7816_T1_BGI(v)))
4691 * @name Register UART_WGP7816_T1, field CWI1[7:4] (RW)
4693 * Used to calculate the value used for the CWT counter. It represents a value
4694 * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
4695 * and guard time parameters .
4698 #define BP_UART_WGP7816_T1_CWI1 (4U) /*!< Bit position for UART_WGP7816_T1_CWI1. */
4699 #define BM_UART_WGP7816_T1_CWI1 (0xF0U) /*!< Bit mask for UART_WGP7816_T1_CWI1. */
4700 #define BS_UART_WGP7816_T1_CWI1 (4U) /*!< Bit field size in bits for UART_WGP7816_T1_CWI1. */
4702 /*! @brief Read current value of the UART_WGP7816_T1_CWI1 field. */
4703 #define BR_UART_WGP7816_T1_CWI1(x) (HW_UART_WGP7816_T1(x).B.CWI1)
4705 /*! @brief Format value for bitfield UART_WGP7816_T1_CWI1. */
4706 #define BF_UART_WGP7816_T1_CWI1(v) ((uint8_t)((uint8_t)(v) << BP_UART_WGP7816_T1_CWI1) & BM_UART_WGP7816_T1_CWI1)
4708 /*! @brief Set the CWI1 field to a new value. */
4709 #define BW_UART_WGP7816_T1_CWI1(x, v) (HW_UART_WGP7816_T1_WR(x, (HW_UART_WGP7816_T1_RD(x) & ~BM_UART_WGP7816_T1_CWI1) | BF_UART_WGP7816_T1_CWI1(v)))
4712 /*******************************************************************************
4713 * HW_UART_WP7816C_T1 - UART 7816 Wait Parameter Register C
4714 ******************************************************************************/
4717 * @brief HW_UART_WP7816C_T1 - UART 7816 Wait Parameter Register C (RW)
4719 * Reset value: 0x0BU
4721 * The WP7816C_T1 register contains constants used in the generation of various
4722 * wait timer counters. This register may be read at any time. This register must
4723 * be written to only when C7816[ISO_7816E] is not set.
4725 typedef union _hw_uart_wp7816c_t1
4728 struct _hw_uart_wp7816c_t1_bitfields
4730 uint8_t CWI2
: 5; /*!< [4:0] Character Wait Time Integer 2
4731 * (C7816[TTYPE] = 1) */
4732 uint8_t RESERVED0
: 3; /*!< [7:5] */
4734 } hw_uart_wp7816c_t1_t
;
4737 * @name Constants and macros for entire UART_WP7816C_T1 register
4740 #define HW_UART_WP7816C_T1_ADDR(x) ((x) + 0x3FU)
4742 #define HW_UART_WP7816C_T1(x) (*(__IO hw_uart_wp7816c_t1_t *) HW_UART_WP7816C_T1_ADDR(x))
4743 #define HW_UART_WP7816C_T1_RD(x) (HW_UART_WP7816C_T1(x).U)
4744 #define HW_UART_WP7816C_T1_WR(x, v) (HW_UART_WP7816C_T1(x).U = (v))
4745 #define HW_UART_WP7816C_T1_SET(x, v) (HW_UART_WP7816C_T1_WR(x, HW_UART_WP7816C_T1_RD(x) | (v)))
4746 #define HW_UART_WP7816C_T1_CLR(x, v) (HW_UART_WP7816C_T1_WR(x, HW_UART_WP7816C_T1_RD(x) & ~(v)))
4747 #define HW_UART_WP7816C_T1_TOG(x, v) (HW_UART_WP7816C_T1_WR(x, HW_UART_WP7816C_T1_RD(x) ^ (v)))
4751 * Constants & macros for individual UART_WP7816C_T1 bitfields
4755 * @name Register UART_WP7816C_T1, field CWI2[4:0] (RW)
4757 * Used to calculate the value used for the CWT counter. It represents a value
4758 * between 0 and 31. This value is used only when C7816[TTYPE] = 1. See Wait time
4759 * and guard time parameters .
4762 #define BP_UART_WP7816C_T1_CWI2 (0U) /*!< Bit position for UART_WP7816C_T1_CWI2. */
4763 #define BM_UART_WP7816C_T1_CWI2 (0x1FU) /*!< Bit mask for UART_WP7816C_T1_CWI2. */
4764 #define BS_UART_WP7816C_T1_CWI2 (5U) /*!< Bit field size in bits for UART_WP7816C_T1_CWI2. */
4766 /*! @brief Read current value of the UART_WP7816C_T1_CWI2 field. */
4767 #define BR_UART_WP7816C_T1_CWI2(x) (HW_UART_WP7816C_T1(x).B.CWI2)
4769 /*! @brief Format value for bitfield UART_WP7816C_T1_CWI2. */
4770 #define BF_UART_WP7816C_T1_CWI2(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816C_T1_CWI2) & BM_UART_WP7816C_T1_CWI2)
4772 /*! @brief Set the CWI2 field to a new value. */
4773 #define BW_UART_WP7816C_T1_CWI2(x, v) (HW_UART_WP7816C_T1_WR(x, (HW_UART_WP7816C_T1_RD(x) & ~BM_UART_WP7816C_T1_CWI2) | BF_UART_WP7816C_T1_CWI2(v)))
4777 ** Start of section using anonymous unions
4780 #if defined(__ARMCC_VERSION)
4783 #elif defined(__CWCC__)
4785 #pragma cpp_extensions on
4786 #elif defined(__GNUC__)
4787 /* anonymous unions are enabled by default */
4788 #elif defined(__IAR_SYSTEMS_ICC__)
4789 #pragma language=extended
4791 #error Not supported compiler type
4794 /*******************************************************************************
4795 * hw_uart_t - module struct
4796 ******************************************************************************/
4798 * @brief All UART module registers.
4801 typedef struct _hw_uart
4803 __IO hw_uart_bdh_t BDH
; /*!< [0x0] UART Baud Rate Registers: High */
4804 __IO hw_uart_bdl_t BDL
; /*!< [0x1] UART Baud Rate Registers: Low */
4805 __IO hw_uart_c1_t C1
; /*!< [0x2] UART Control Register 1 */
4806 __IO hw_uart_c2_t C2
; /*!< [0x3] UART Control Register 2 */
4807 __I hw_uart_s1_t S1
; /*!< [0x4] UART Status Register 1 */
4808 __IO hw_uart_s2_t S2
; /*!< [0x5] UART Status Register 2 */
4809 __IO hw_uart_c3_t C3
; /*!< [0x6] UART Control Register 3 */
4810 __IO hw_uart_d_t D
; /*!< [0x7] UART Data Register */
4811 __IO hw_uart_ma1_t MA1
; /*!< [0x8] UART Match Address Registers 1 */
4812 __IO hw_uart_ma2_t MA2
; /*!< [0x9] UART Match Address Registers 2 */
4813 __IO hw_uart_c4_t C4
; /*!< [0xA] UART Control Register 4 */
4814 __IO hw_uart_c5_t C5
; /*!< [0xB] UART Control Register 5 */
4815 __I hw_uart_ed_t ED
; /*!< [0xC] UART Extended Data Register */
4816 __IO hw_uart_modem_t MODEM
; /*!< [0xD] UART Modem Register */
4817 __IO hw_uart_ir_t IR
; /*!< [0xE] UART Infrared Register */
4818 uint8_t _reserved0
[1];
4819 __IO hw_uart_pfifo_t PFIFO
; /*!< [0x10] UART FIFO Parameters */
4820 __IO hw_uart_cfifo_t CFIFO
; /*!< [0x11] UART FIFO Control Register */
4821 __IO hw_uart_sfifo_t SFIFO
; /*!< [0x12] UART FIFO Status Register */
4822 __IO hw_uart_twfifo_t TWFIFO
; /*!< [0x13] UART FIFO Transmit Watermark */
4823 __I hw_uart_tcfifo_t TCFIFO
; /*!< [0x14] UART FIFO Transmit Count */
4824 __IO hw_uart_rwfifo_t RWFIFO
; /*!< [0x15] UART FIFO Receive Watermark */
4825 __I hw_uart_rcfifo_t RCFIFO
; /*!< [0x16] UART FIFO Receive Count */
4826 uint8_t _reserved1
[1];
4827 __IO hw_uart_c7816_t C7816
; /*!< [0x18] UART 7816 Control Register */
4828 __IO hw_uart_ie7816_t IE7816
; /*!< [0x19] UART 7816 Interrupt Enable Register */
4829 __IO hw_uart_is7816_t IS7816
; /*!< [0x1A] UART 7816 Interrupt Status Register */
4830 __IO hw_uart_wp7816_t WP7816
; /*!< [0x1B] UART 7816 Wait Parameter Register */
4831 __IO hw_uart_wn7816_t WN7816
; /*!< [0x1C] UART 7816 Wait N Register */
4832 __IO hw_uart_wf7816_t WF7816
; /*!< [0x1D] UART 7816 Wait FD Register */
4833 __IO hw_uart_et7816_t ET7816
; /*!< [0x1E] UART 7816 Error Threshold Register */
4834 __IO hw_uart_tl7816_t TL7816
; /*!< [0x1F] UART 7816 Transmit Length Register */
4835 uint8_t _reserved2
[26];
4836 __IO hw_uart_ap7816a_t0_t AP7816A_T0
; /*!< [0x3A] UART 7816 ATR Duration Timer Register A */
4837 __IO hw_uart_ap7816b_t0_t AP7816B_T0
; /*!< [0x3B] UART 7816 ATR Duration Timer Register B */
4840 __IO hw_uart_wp7816a_t0_t WP7816A_T0
; /*!< [0x3C] UART 7816 Wait Parameter Register A */
4841 __IO hw_uart_wp7816b_t0_t WP7816B_T0
; /*!< [0x3D] UART 7816 Wait Parameter Register B */
4844 __IO hw_uart_wp7816a_t1_t WP7816A_T1
; /*!< [0x3C] UART 7816 Wait Parameter Register A */
4845 __IO hw_uart_wp7816b_t1_t WP7816B_T1
; /*!< [0x3D] UART 7816 Wait Parameter Register B */
4848 __IO hw_uart_wgp7816_t1_t WGP7816_T1
; /*!< [0x3E] UART 7816 Wait and Guard Parameter Register */
4849 __IO hw_uart_wp7816c_t1_t WP7816C_T1
; /*!< [0x3F] UART 7816 Wait Parameter Register C */
4853 /*! @brief Macro to access all UART registers. */
4854 /*! @param x UART module instance base address. */
4855 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
4856 * use the '&' operator, like <code>&HW_UART(UART0_BASE)</code>. */
4857 #define HW_UART(x) (*(hw_uart_t *)(x))
4860 ** End of section using anonymous unions
4863 #if defined(__ARMCC_VERSION)
4865 #elif defined(__CWCC__)
4867 #elif defined(__GNUC__)
4868 /* leave anonymous unions enabled */
4869 #elif defined(__IAR_SYSTEMS_ICC__)
4870 #pragma language=default
4872 #error Not supported compiler type
4875 #endif /* __HW_UART_REGISTERS_H__ */