tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_VREF_REGISTERS_H__
  78 #define __HW_VREF_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 VREF
  85  *
  86  * Voltage Reference
  87  *
  88  * Registers defined in this header file:
  89  * - HW_VREF_TRM - VREF Trim Register
  90  * - HW_VREF_SC - VREF Status and Control Register
  91  *
  92  * - hw_vref_t - Struct containing all module registers.
  93  */
  94
  95 #define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
  96
  97 /*******************************************************************************
  98  * HW_VREF_TRM - VREF Trim Register
  99  ******************************************************************************/
 100
 101 /*!
 102  * @brief HW_VREF_TRM - VREF Trim Register (RW)
 103  *
 104  * Reset value: 0x00U
 105  *
 106  * This register contains bits that contain the trim data for the Voltage
 107  * Reference.
 108  */
 109 typedef union _hw_vref_trm
 110 {
 111     uint8_t U;
 112     struct _hw_vref_trm_bitfields
 113     {
 114         uint8_t TRIM : 6;              /*!< [5:0] Trim bits */
 115         uint8_t CHOPEN : 1;            /*!< [6] Chop oscillator enable. When set,
 116                                         * internal chopping operation is enabled and the internal analog offset will be
 117                                         * minimized. */
 118         uint8_t RESERVED0 : 1;         /*!< [7]  */
 119     } B;
 120 } hw_vref_trm_t;
 121
 122 /*!
 123  * @name Constants and macros for entire VREF_TRM register
 124  */
 125 /*@{*/
 126 #define HW_VREF_TRM_ADDR(x)      ((x) + 0x0U)
 127
 128 #define HW_VREF_TRM(x)           (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
 129 #define HW_VREF_TRM_RD(x)        (HW_VREF_TRM(x).U)
 130 #define HW_VREF_TRM_WR(x, v)     (HW_VREF_TRM(x).U = (v))
 131 #define HW_VREF_TRM_SET(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) |  (v)))
 132 #define HW_VREF_TRM_CLR(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
 133 #define HW_VREF_TRM_TOG(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^  (v)))
 134 /*@}*/
 135
 136 /*
 137  * Constants & macros for individual VREF_TRM bitfields
 138  */
 139
 140 /*!
 141  * @name Register VREF_TRM, field TRIM[5:0] (RW)
 142  *
 143  * These bits change the resulting VREF by approximately +/- 0.5 mV for each
 144  * step. Min = minimum and max = maximum voltage reference output. For minimum and
 145  * maximum voltage reference output values, refer to the Data Sheet for this chip.
 146  *
 147  * Values:
 148  * - 000000 - Min
 149  * - 111111 - Max
 150  */
 151 /*@{*/
 152 #define BP_VREF_TRM_TRIM     (0U)          /*!< Bit position for VREF_TRM_TRIM. */
 153 #define BM_VREF_TRM_TRIM     (0x3FU)       /*!< Bit mask for VREF_TRM_TRIM. */
 154 #define BS_VREF_TRM_TRIM     (6U)          /*!< Bit field size in bits for VREF_TRM_TRIM. */
 155
 156 /*! @brief Read current value of the VREF_TRM_TRIM field. */
 157 #define BR_VREF_TRM_TRIM(x)  (HW_VREF_TRM(x).B.TRIM)
 158
 159 /*! @brief Format value for bitfield VREF_TRM_TRIM. */
 160 #define BF_VREF_TRM_TRIM(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
 161
 162 /*! @brief Set the TRIM field to a new value. */
 163 #define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
 164 /*@}*/
 165
 166 /*!
 167  * @name Register VREF_TRM, field CHOPEN[6] (RW)
 168  *
 169  * This bit is set during factory trimming of the VREF voltage. This bit should
 170  * be written to 1 to achieve the performance stated in the data sheet.
 171  *
 172  * Values:
 173  * - 0 - Chop oscillator is disabled.
 174  * - 1 - Chop oscillator is enabled.
 175  */
 176 /*@{*/
 177 #define BP_VREF_TRM_CHOPEN   (6U)          /*!< Bit position for VREF_TRM_CHOPEN. */
 178 #define BM_VREF_TRM_CHOPEN   (0x40U)       /*!< Bit mask for VREF_TRM_CHOPEN. */
 179 #define BS_VREF_TRM_CHOPEN   (1U)          /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
 180
 181 /*! @brief Read current value of the VREF_TRM_CHOPEN field. */
 182 #define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN))
 183
 184 /*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
 185 #define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
 186
 187 /*! @brief Set the CHOPEN field to a new value. */
 188 #define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v))
 189 /*@}*/
 190
 191 /*******************************************************************************
 192  * HW_VREF_SC - VREF Status and Control Register
 193  ******************************************************************************/
 194
 195 /*!
 196  * @brief HW_VREF_SC - VREF Status and Control Register (RW)
 197  *
 198  * Reset value: 0x00U
 199  *
 200  * This register contains the control bits used to enable the internal voltage
 201  * reference and to select the buffer mode to be used.
 202  */
 203 typedef union _hw_vref_sc
 204 {
 205     uint8_t U;
 206     struct _hw_vref_sc_bitfields
 207     {
 208         uint8_t MODE_LV : 2;           /*!< [1:0] Buffer Mode selection */
 209         uint8_t VREFST : 1;            /*!< [2] Internal Voltage Reference stable */
 210         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
 211         uint8_t ICOMPEN : 1;           /*!< [5] Second order curvature compensation
 212                                         * enable */
 213         uint8_t REGEN : 1;             /*!< [6] Regulator enable */
 214         uint8_t VREFEN : 1;            /*!< [7] Internal Voltage Reference enable */
 215     } B;
 216 } hw_vref_sc_t;
 217
 218 /*!
 219  * @name Constants and macros for entire VREF_SC register
 220  */
 221 /*@{*/
 222 #define HW_VREF_SC_ADDR(x)       ((x) + 0x1U)
 223
 224 #define HW_VREF_SC(x)            (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
 225 #define HW_VREF_SC_RD(x)         (HW_VREF_SC(x).U)
 226 #define HW_VREF_SC_WR(x, v)      (HW_VREF_SC(x).U = (v))
 227 #define HW_VREF_SC_SET(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) |  (v)))
 228 #define HW_VREF_SC_CLR(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
 229 #define HW_VREF_SC_TOG(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^  (v)))
 230 /*@}*/
 231
 232 /*
 233  * Constants & macros for individual VREF_SC bitfields
 234  */
 235
 236 /*!
 237  * @name Register VREF_SC, field MODE_LV[1:0] (RW)
 238  *
 239  * These bits select the buffer modes for the Voltage Reference module.
 240  *
 241  * Values:
 242  * - 00 - Bandgap on only, for stabilization and startup
 243  * - 01 - High power buffer mode enabled
 244  * - 10 - Low-power buffer mode enabled
 245  * - 11 - Reserved
 246  */
 247 /*@{*/
 248 #define BP_VREF_SC_MODE_LV   (0U)          /*!< Bit position for VREF_SC_MODE_LV. */
 249 #define BM_VREF_SC_MODE_LV   (0x03U)       /*!< Bit mask for VREF_SC_MODE_LV. */
 250 #define BS_VREF_SC_MODE_LV   (2U)          /*!< Bit field size in bits for VREF_SC_MODE_LV. */
 251
 252 /*! @brief Read current value of the VREF_SC_MODE_LV field. */
 253 #define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV)
 254
 255 /*! @brief Format value for bitfield VREF_SC_MODE_LV. */
 256 #define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
 257
 258 /*! @brief Set the MODE_LV field to a new value. */
 259 #define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
 260 /*@}*/
 261
 262 /*!
 263  * @name Register VREF_SC, field VREFST[2] (RO)
 264  *
 265  * This bit indicates that the bandgap reference within the Voltage Reference
 266  * module has completed its startup and stabilization.
 267  *
 268  * Values:
 269  * - 0 - The module is disabled or not stable.
 270  * - 1 - The module is stable.
 271  */
 272 /*@{*/
 273 #define BP_VREF_SC_VREFST    (2U)          /*!< Bit position for VREF_SC_VREFST. */
 274 #define BM_VREF_SC_VREFST    (0x04U)       /*!< Bit mask for VREF_SC_VREFST. */
 275 #define BS_VREF_SC_VREFST    (1U)          /*!< Bit field size in bits for VREF_SC_VREFST. */
 276
 277 /*! @brief Read current value of the VREF_SC_VREFST field. */
 278 #define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST))
 279 /*@}*/
 280
 281 /*!
 282  * @name Register VREF_SC, field ICOMPEN[5] (RW)
 283  *
 284  * This bit is set during factory trimming of the VREF voltage. This bit should
 285  * be written to 1 to achieve the performance stated in the data sheet.
 286  *
 287  * Values:
 288  * - 0 - Disabled
 289  * - 1 - Enabled
 290  */
 291 /*@{*/
 292 #define BP_VREF_SC_ICOMPEN   (5U)          /*!< Bit position for VREF_SC_ICOMPEN. */
 293 #define BM_VREF_SC_ICOMPEN   (0x20U)       /*!< Bit mask for VREF_SC_ICOMPEN. */
 294 #define BS_VREF_SC_ICOMPEN   (1U)          /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
 295
 296 /*! @brief Read current value of the VREF_SC_ICOMPEN field. */
 297 #define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN))
 298
 299 /*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
 300 #define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
 301
 302 /*! @brief Set the ICOMPEN field to a new value. */
 303 #define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v))
 304 /*@}*/
 305
 306 /*!
 307  * @name Register VREF_SC, field REGEN[6] (RW)
 308  *
 309  * This bit is used to enable the internal 1.75 V regulator to produce a
 310  * constant internal voltage supply in order to reduce the sensitivity to external
 311  * supply noise and variation. If it is desired to keep the regulator enabled in very
 312  * low power modes, refer to the Chip Configuration details for a description on
 313  * how this can be achieved. This bit is set during factory trimming of the VREF
 314  * voltage. This bit should be written to 1 to achieve the performance stated in
 315  * the data sheet.
 316  *
 317  * Values:
 318  * - 0 - Internal 1.75 V regulator is disabled.
 319  * - 1 - Internal 1.75 V regulator is enabled.
 320  */
 321 /*@{*/
 322 #define BP_VREF_SC_REGEN     (6U)          /*!< Bit position for VREF_SC_REGEN. */
 323 #define BM_VREF_SC_REGEN     (0x40U)       /*!< Bit mask for VREF_SC_REGEN. */
 324 #define BS_VREF_SC_REGEN     (1U)          /*!< Bit field size in bits for VREF_SC_REGEN. */
 325
 326 /*! @brief Read current value of the VREF_SC_REGEN field. */
 327 #define BR_VREF_SC_REGEN(x)  (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN))
 328
 329 /*! @brief Format value for bitfield VREF_SC_REGEN. */
 330 #define BF_VREF_SC_REGEN(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
 331
 332 /*! @brief Set the REGEN field to a new value. */
 333 #define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v))
 334 /*@}*/
 335
 336 /*!
 337  * @name Register VREF_SC, field VREFEN[7] (RW)
 338  *
 339  * This bit is used to enable the bandgap reference within the Voltage Reference
 340  * module. After the VREF is enabled, turning off the clock to the VREF module
 341  * via the corresponding clock gate register will not disable the VREF. VREF must
 342  * be disabled via this VREFEN bit.
 343  *
 344  * Values:
 345  * - 0 - The module is disabled.
 346  * - 1 - The module is enabled.
 347  */
 348 /*@{*/
 349 #define BP_VREF_SC_VREFEN    (7U)          /*!< Bit position for VREF_SC_VREFEN. */
 350 #define BM_VREF_SC_VREFEN    (0x80U)       /*!< Bit mask for VREF_SC_VREFEN. */
 351 #define BS_VREF_SC_VREFEN    (1U)          /*!< Bit field size in bits for VREF_SC_VREFEN. */
 352
 353 /*! @brief Read current value of the VREF_SC_VREFEN field. */
 354 #define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN))
 355
 356 /*! @brief Format value for bitfield VREF_SC_VREFEN. */
 357 #define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
 358
 359 /*! @brief Set the VREFEN field to a new value. */
 360 #define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v))
 361 /*@}*/
 362
 363 /*******************************************************************************
 364  * hw_vref_t - module struct
 365  ******************************************************************************/
 366 /*!
 367  * @brief All VREF module registers.
 368  */
 369 #pragma pack(1)
 370 typedef struct _hw_vref
 371 {
 372     __IO hw_vref_trm_t TRM;                /*!< [0x0] VREF Trim Register */
 373     __IO hw_vref_sc_t SC;                  /*!< [0x1] VREF Status and Control Register */
 374 } hw_vref_t;
 375 #pragma pack()
 376
 377 /*! @brief Macro to access all VREF registers. */
 378 /*! @param x VREF module instance base address. */
 379 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 380  *     use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
 381 #define HW_VREF(x)     (*(hw_vref_t *)(x))
 382
 383 #endif /* __HW_VREF_REGISTERS_H__ */
 384 /* EOF */