tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_WDOG_REGISTERS_H__
  78 #define __HW_WDOG_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 WDOG
  85  *
  86  * Generation 2008 Watchdog Timer
  87  *
  88  * Registers defined in this header file:
  89  * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
  90  * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
  91  * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
  92  * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
  93  * - HW_WDOG_WINH - Watchdog Window Register High
  94  * - HW_WDOG_WINL - Watchdog Window Register Low
  95  * - HW_WDOG_REFRESH - Watchdog Refresh register
  96  * - HW_WDOG_UNLOCK - Watchdog Unlock register
  97  * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
  98  * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
  99  * - HW_WDOG_RSTCNT - Watchdog Reset Count register
 100  * - HW_WDOG_PRESC - Watchdog Prescaler register
 101  *
 102  * - hw_wdog_t - Struct containing all module registers.
 103  */
 104
 105 #define HW_WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
 106
 107 /*******************************************************************************
 108  * HW_WDOG_STCTRLH - Watchdog Status and Control Register High
 109  ******************************************************************************/
 110
 111 /*!
 112  * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
 113  *
 114  * Reset value: 0x01D3U
 115  */
 116 typedef union _hw_wdog_stctrlh
 117 {
 118     uint16_t U;
 119     struct _hw_wdog_stctrlh_bitfields
 120     {
 121         uint16_t WDOGEN : 1;           /*!< [0]  */
 122         uint16_t CLKSRC : 1;           /*!< [1]  */
 123         uint16_t IRQRSTEN : 1;         /*!< [2]  */
 124         uint16_t WINEN : 1;            /*!< [3]  */
 125         uint16_t ALLOWUPDATE : 1;      /*!< [4]  */
 126         uint16_t DBGEN : 1;            /*!< [5]  */
 127         uint16_t STOPEN : 1;           /*!< [6]  */
 128         uint16_t WAITEN : 1;           /*!< [7]  */
 129         uint16_t RESERVED0 : 2;        /*!< [9:8]  */
 130         uint16_t TESTWDOG : 1;         /*!< [10]  */
 131         uint16_t TESTSEL : 1;          /*!< [11]  */
 132         uint16_t BYTESEL : 2;          /*!< [13:12]  */
 133         uint16_t DISTESTWDOG : 1;      /*!< [14]  */
 134         uint16_t RESERVED1 : 1;        /*!< [15]  */
 135     } B;
 136 } hw_wdog_stctrlh_t;
 137
 138 /*!
 139  * @name Constants and macros for entire WDOG_STCTRLH register
 140  */
 141 /*@{*/
 142 #define HW_WDOG_STCTRLH_ADDR(x)  ((x) + 0x0U)
 143
 144 #define HW_WDOG_STCTRLH(x)       (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR(x))
 145 #define HW_WDOG_STCTRLH_RD(x)    (HW_WDOG_STCTRLH(x).U)
 146 #define HW_WDOG_STCTRLH_WR(x, v) (HW_WDOG_STCTRLH(x).U = (v))
 147 #define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) |  (v)))
 148 #define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v)))
 149 #define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^  (v)))
 150 /*@}*/
 151
 152 /*
 153  * Constants & macros for individual WDOG_STCTRLH bitfields
 154  */
 155
 156 /*!
 157  * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
 158  *
 159  * Enables or disables the WDOG's operation. In the disabled state, the watchdog
 160  * timer is kept in the reset state, but the other exception conditions can
 161  * still trigger a reset/interrupt. A change in the value of this bit must be held
 162  * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
 163  *
 164  * Values:
 165  * - 0 - WDOG is disabled.
 166  * - 1 - WDOG is enabled.
 167  */
 168 /*@{*/
 169 #define BP_WDOG_STCTRLH_WDOGEN (0U)        /*!< Bit position for WDOG_STCTRLH_WDOGEN. */
 170 #define BM_WDOG_STCTRLH_WDOGEN (0x0001U)   /*!< Bit mask for WDOG_STCTRLH_WDOGEN. */
 171 #define BS_WDOG_STCTRLH_WDOGEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. */
 172
 173 /*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
 174 #define BR_WDOG_STCTRLH_WDOGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN))
 175
 176 /*! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. */
 177 #define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN)
 178
 179 /*! @brief Set the WDOGEN field to a new value. */
 180 #define BW_WDOG_STCTRLH_WDOGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN) = (v))
 181 /*@}*/
 182
 183 /*!
 184  * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
 185  *
 186  * Selects clock source for the WDOG timer and other internal timing operations.
 187  *
 188  * Values:
 189  * - 0 - WDOG clock sourced from LPO .
 190  * - 1 - WDOG clock sourced from alternate clock source.
 191  */
 192 /*@{*/
 193 #define BP_WDOG_STCTRLH_CLKSRC (1U)        /*!< Bit position for WDOG_STCTRLH_CLKSRC. */
 194 #define BM_WDOG_STCTRLH_CLKSRC (0x0002U)   /*!< Bit mask for WDOG_STCTRLH_CLKSRC. */
 195 #define BS_WDOG_STCTRLH_CLKSRC (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. */
 196
 197 /*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
 198 #define BR_WDOG_STCTRLH_CLKSRC(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC))
 199
 200 /*! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. */
 201 #define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC)
 202
 203 /*! @brief Set the CLKSRC field to a new value. */
 204 #define BW_WDOG_STCTRLH_CLKSRC(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC) = (v))
 205 /*@}*/
 206
 207 /*!
 208  * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
 209  *
 210  * Used to enable the debug breadcrumbs feature. A change in this bit is updated
 211  * immediately, as opposed to updating after WCT.
 212  *
 213  * Values:
 214  * - 0 - WDOG time-out generates reset only.
 215  * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
 216  *     a reset.
 217  */
 218 /*@{*/
 219 #define BP_WDOG_STCTRLH_IRQRSTEN (2U)      /*!< Bit position for WDOG_STCTRLH_IRQRSTEN. */
 220 #define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /*!< Bit mask for WDOG_STCTRLH_IRQRSTEN. */
 221 #define BS_WDOG_STCTRLH_IRQRSTEN (1U)      /*!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. */
 222
 223 /*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
 224 #define BR_WDOG_STCTRLH_IRQRSTEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN))
 225
 226 /*! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. */
 227 #define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN)
 228
 229 /*! @brief Set the IRQRSTEN field to a new value. */
 230 #define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN) = (v))
 231 /*@}*/
 232
 233 /*!
 234  * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
 235  *
 236  * Enables Windowing mode.
 237  *
 238  * Values:
 239  * - 0 - Windowing mode is disabled.
 240  * - 1 - Windowing mode is enabled.
 241  */
 242 /*@{*/
 243 #define BP_WDOG_STCTRLH_WINEN (3U)         /*!< Bit position for WDOG_STCTRLH_WINEN. */
 244 #define BM_WDOG_STCTRLH_WINEN (0x0008U)    /*!< Bit mask for WDOG_STCTRLH_WINEN. */
 245 #define BS_WDOG_STCTRLH_WINEN (1U)         /*!< Bit field size in bits for WDOG_STCTRLH_WINEN. */
 246
 247 /*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
 248 #define BR_WDOG_STCTRLH_WINEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN))
 249
 250 /*! @brief Format value for bitfield WDOG_STCTRLH_WINEN. */
 251 #define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN)
 252
 253 /*! @brief Set the WINEN field to a new value. */
 254 #define BW_WDOG_STCTRLH_WINEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN) = (v))
 255 /*@}*/
 256
 257 /*!
 258  * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
 259  *
 260  * Enables updates to watchdog write-once registers, after the reset-triggered
 261  * initial configuration window (WCT) closes, through unlock sequence.
 262  *
 263  * Values:
 264  * - 0 - No further updates allowed to WDOG write-once registers.
 265  * - 1 - WDOG write-once registers can be unlocked for updating.
 266  */
 267 /*@{*/
 268 #define BP_WDOG_STCTRLH_ALLOWUPDATE (4U)   /*!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. */
 269 #define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /*!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. */
 270 #define BS_WDOG_STCTRLH_ALLOWUPDATE (1U)   /*!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. */
 271
 272 /*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
 273 #define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE))
 274
 275 /*! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. */
 276 #define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE)
 277
 278 /*! @brief Set the ALLOWUPDATE field to a new value. */
 279 #define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
 280 /*@}*/
 281
 282 /*!
 283  * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
 284  *
 285  * Enables or disables WDOG in Debug mode.
 286  *
 287  * Values:
 288  * - 0 - WDOG is disabled in CPU Debug mode.
 289  * - 1 - WDOG is enabled in CPU Debug mode.
 290  */
 291 /*@{*/
 292 #define BP_WDOG_STCTRLH_DBGEN (5U)         /*!< Bit position for WDOG_STCTRLH_DBGEN. */
 293 #define BM_WDOG_STCTRLH_DBGEN (0x0020U)    /*!< Bit mask for WDOG_STCTRLH_DBGEN. */
 294 #define BS_WDOG_STCTRLH_DBGEN (1U)         /*!< Bit field size in bits for WDOG_STCTRLH_DBGEN. */
 295
 296 /*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
 297 #define BR_WDOG_STCTRLH_DBGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN))
 298
 299 /*! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. */
 300 #define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN)
 301
 302 /*! @brief Set the DBGEN field to a new value. */
 303 #define BW_WDOG_STCTRLH_DBGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN) = (v))
 304 /*@}*/
 305
 306 /*!
 307  * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
 308  *
 309  * Enables or disables WDOG in Stop mode.
 310  *
 311  * Values:
 312  * - 0 - WDOG is disabled in CPU Stop mode.
 313  * - 1 - WDOG is enabled in CPU Stop mode.
 314  */
 315 /*@{*/
 316 #define BP_WDOG_STCTRLH_STOPEN (6U)        /*!< Bit position for WDOG_STCTRLH_STOPEN. */
 317 #define BM_WDOG_STCTRLH_STOPEN (0x0040U)   /*!< Bit mask for WDOG_STCTRLH_STOPEN. */
 318 #define BS_WDOG_STCTRLH_STOPEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_STOPEN. */
 319
 320 /*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
 321 #define BR_WDOG_STCTRLH_STOPEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN))
 322
 323 /*! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. */
 324 #define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN)
 325
 326 /*! @brief Set the STOPEN field to a new value. */
 327 #define BW_WDOG_STCTRLH_STOPEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN) = (v))
 328 /*@}*/
 329
 330 /*!
 331  * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
 332  *
 333  * Enables or disables WDOG in Wait mode.
 334  *
 335  * Values:
 336  * - 0 - WDOG is disabled in CPU Wait mode.
 337  * - 1 - WDOG is enabled in CPU Wait mode.
 338  */
 339 /*@{*/
 340 #define BP_WDOG_STCTRLH_WAITEN (7U)        /*!< Bit position for WDOG_STCTRLH_WAITEN. */
 341 #define BM_WDOG_STCTRLH_WAITEN (0x0080U)   /*!< Bit mask for WDOG_STCTRLH_WAITEN. */
 342 #define BS_WDOG_STCTRLH_WAITEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_WAITEN. */
 343
 344 /*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
 345 #define BR_WDOG_STCTRLH_WAITEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN))
 346
 347 /*! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. */
 348 #define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN)
 349
 350 /*! @brief Set the WAITEN field to a new value. */
 351 #define BW_WDOG_STCTRLH_WAITEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN) = (v))
 352 /*@}*/
 353
 354 /*!
 355  * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
 356  *
 357  * Puts the watchdog in the functional test mode. In this mode, the watchdog
 358  * timer and the associated compare and reset generation logic is tested for correct
 359  * operation. The clock for the timer is switched from the main watchdog clock
 360  * to the fast clock input for watchdog functional test. The TESTSEL bit selects
 361  * the test to be run.
 362  */
 363 /*@{*/
 364 #define BP_WDOG_STCTRLH_TESTWDOG (10U)     /*!< Bit position for WDOG_STCTRLH_TESTWDOG. */
 365 #define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /*!< Bit mask for WDOG_STCTRLH_TESTWDOG. */
 366 #define BS_WDOG_STCTRLH_TESTWDOG (1U)      /*!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. */
 367
 368 /*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
 369 #define BR_WDOG_STCTRLH_TESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG))
 370
 371 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. */
 372 #define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG)
 373
 374 /*! @brief Set the TESTWDOG field to a new value. */
 375 #define BW_WDOG_STCTRLH_TESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG) = (v))
 376 /*@}*/
 377
 378 /*!
 379  * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
 380  *
 381  * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
 382  * timer.
 383  *
 384  * Values:
 385  * - 0 - Quick test. The timer runs in normal operation. You can load a small
 386  *     time-out value to do a quick test.
 387  * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
 388  *     of the timer are enabled for operation and are compared for time-out
 389  *     against the corresponding byte of the programmed time-out value. Select the
 390  *     byte through BYTESEL[1:0] for testing.
 391  */
 392 /*@{*/
 393 #define BP_WDOG_STCTRLH_TESTSEL (11U)      /*!< Bit position for WDOG_STCTRLH_TESTSEL. */
 394 #define BM_WDOG_STCTRLH_TESTSEL (0x0800U)  /*!< Bit mask for WDOG_STCTRLH_TESTSEL. */
 395 #define BS_WDOG_STCTRLH_TESTSEL (1U)       /*!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. */
 396
 397 /*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
 398 #define BR_WDOG_STCTRLH_TESTSEL(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL))
 399
 400 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. */
 401 #define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL)
 402
 403 /*! @brief Set the TESTSEL field to a new value. */
 404 #define BW_WDOG_STCTRLH_TESTSEL(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL) = (v))
 405 /*@}*/
 406
 407 /*!
 408  * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
 409  *
 410  * This 2-bit field selects the byte to be tested when the watchdog is in the
 411  * byte test mode.
 412  *
 413  * Values:
 414  * - 00 - Byte 0 selected
 415  * - 01 - Byte 1 selected
 416  * - 10 - Byte 2 selected
 417  * - 11 - Byte 3 selected
 418  */
 419 /*@{*/
 420 #define BP_WDOG_STCTRLH_BYTESEL (12U)      /*!< Bit position for WDOG_STCTRLH_BYTESEL. */
 421 #define BM_WDOG_STCTRLH_BYTESEL (0x3000U)  /*!< Bit mask for WDOG_STCTRLH_BYTESEL. */
 422 #define BS_WDOG_STCTRLH_BYTESEL (2U)       /*!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. */
 423
 424 /*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
 425 #define BR_WDOG_STCTRLH_BYTESEL(x) (HW_WDOG_STCTRLH(x).B.BYTESEL)
 426
 427 /*! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. */
 428 #define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL)
 429
 430 /*! @brief Set the BYTESEL field to a new value. */
 431 #define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
 432 /*@}*/
 433
 434 /*!
 435  * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
 436  *
 437  * Allows the WDOG's functional test mode to be disabled permanently. After it
 438  * is set, it can only be cleared by a reset. It cannot be unlocked for editing
 439  * after it is set.
 440  *
 441  * Values:
 442  * - 0 - WDOG functional test mode is not disabled.
 443  * - 1 - WDOG functional test mode is disabled permanently until reset.
 444  */
 445 /*@{*/
 446 #define BP_WDOG_STCTRLH_DISTESTWDOG (14U)  /*!< Bit position for WDOG_STCTRLH_DISTESTWDOG. */
 447 #define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /*!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. */
 448 #define BS_WDOG_STCTRLH_DISTESTWDOG (1U)   /*!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. */
 449
 450 /*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
 451 #define BR_WDOG_STCTRLH_DISTESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG))
 452
 453 /*! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. */
 454 #define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG)
 455
 456 /*! @brief Set the DISTESTWDOG field to a new value. */
 457 #define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
 458 /*@}*/
 459
 460 /*******************************************************************************
 461  * HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
 462  ******************************************************************************/
 463
 464 /*!
 465  * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
 466  *
 467  * Reset value: 0x0001U
 468  */
 469 typedef union _hw_wdog_stctrll
 470 {
 471     uint16_t U;
 472     struct _hw_wdog_stctrll_bitfields
 473     {
 474         uint16_t RESERVED0 : 15;       /*!< [14:0]  */
 475         uint16_t INTFLG : 1;           /*!< [15]  */
 476     } B;
 477 } hw_wdog_stctrll_t;
 478
 479 /*!
 480  * @name Constants and macros for entire WDOG_STCTRLL register
 481  */
 482 /*@{*/
 483 #define HW_WDOG_STCTRLL_ADDR(x)  ((x) + 0x2U)
 484
 485 #define HW_WDOG_STCTRLL(x)       (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR(x))
 486 #define HW_WDOG_STCTRLL_RD(x)    (HW_WDOG_STCTRLL(x).U)
 487 #define HW_WDOG_STCTRLL_WR(x, v) (HW_WDOG_STCTRLL(x).U = (v))
 488 #define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) |  (v)))
 489 #define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v)))
 490 #define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^  (v)))
 491 /*@}*/
 492
 493 /*
 494  * Constants & macros for individual WDOG_STCTRLL bitfields
 495  */
 496
 497 /*!
 498  * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
 499  *
 500  * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
 501  * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
 502  * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
 503  * bit. It also gets cleared on a system reset.
 504  */
 505 /*@{*/
 506 #define BP_WDOG_STCTRLL_INTFLG (15U)       /*!< Bit position for WDOG_STCTRLL_INTFLG. */
 507 #define BM_WDOG_STCTRLL_INTFLG (0x8000U)   /*!< Bit mask for WDOG_STCTRLL_INTFLG. */
 508 #define BS_WDOG_STCTRLL_INTFLG (1U)        /*!< Bit field size in bits for WDOG_STCTRLL_INTFLG. */
 509
 510 /*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
 511 #define BR_WDOG_STCTRLL_INTFLG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG))
 512
 513 /*! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. */
 514 #define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG)
 515
 516 /*! @brief Set the INTFLG field to a new value. */
 517 #define BW_WDOG_STCTRLL_INTFLG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG) = (v))
 518 /*@}*/
 519
 520 /*******************************************************************************
 521  * HW_WDOG_TOVALH - Watchdog Time-out Value Register High
 522  ******************************************************************************/
 523
 524 /*!
 525  * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
 526  *
 527  * Reset value: 0x004CU
 528  */
 529 typedef union _hw_wdog_tovalh
 530 {
 531     uint16_t U;
 532     struct _hw_wdog_tovalh_bitfields
 533     {
 534         uint16_t TOVALHIGH : 16;       /*!< [15:0]  */
 535     } B;
 536 } hw_wdog_tovalh_t;
 537
 538 /*!
 539  * @name Constants and macros for entire WDOG_TOVALH register
 540  */
 541 /*@{*/
 542 #define HW_WDOG_TOVALH_ADDR(x)   ((x) + 0x4U)
 543
 544 #define HW_WDOG_TOVALH(x)        (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR(x))
 545 #define HW_WDOG_TOVALH_RD(x)     (HW_WDOG_TOVALH(x).U)
 546 #define HW_WDOG_TOVALH_WR(x, v)  (HW_WDOG_TOVALH(x).U = (v))
 547 #define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) |  (v)))
 548 #define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v)))
 549 #define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^  (v)))
 550 /*@}*/
 551
 552 /*
 553  * Constants & macros for individual WDOG_TOVALH bitfields
 554  */
 555
 556 /*!
 557  * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
 558  *
 559  * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
 560  * timer. It is defined in terms of cycles of the watchdog clock.
 561  */
 562 /*@{*/
 563 #define BP_WDOG_TOVALH_TOVALHIGH (0U)      /*!< Bit position for WDOG_TOVALH_TOVALHIGH. */
 564 #define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /*!< Bit mask for WDOG_TOVALH_TOVALHIGH. */
 565 #define BS_WDOG_TOVALH_TOVALHIGH (16U)     /*!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. */
 566
 567 /*! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. */
 568 #define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U)
 569
 570 /*! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. */
 571 #define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH)
 572
 573 /*! @brief Set the TOVALHIGH field to a new value. */
 574 #define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v))
 575 /*@}*/
 576
 577 /*******************************************************************************
 578  * HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
 579  ******************************************************************************/
 580
 581 /*!
 582  * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
 583  *
 584  * Reset value: 0x4B4CU
 585  *
 586  * The time-out value of the watchdog must be set to a minimum of four watchdog
 587  * clock cycles. This is to take into account the delay in new settings taking
 588  * effect in the watchdog clock domain.
 589  */
 590 typedef union _hw_wdog_tovall
 591 {
 592     uint16_t U;
 593     struct _hw_wdog_tovall_bitfields
 594     {
 595         uint16_t TOVALLOW : 16;        /*!< [15:0]  */
 596     } B;
 597 } hw_wdog_tovall_t;
 598
 599 /*!
 600  * @name Constants and macros for entire WDOG_TOVALL register
 601  */
 602 /*@{*/
 603 #define HW_WDOG_TOVALL_ADDR(x)   ((x) + 0x6U)
 604
 605 #define HW_WDOG_TOVALL(x)        (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR(x))
 606 #define HW_WDOG_TOVALL_RD(x)     (HW_WDOG_TOVALL(x).U)
 607 #define HW_WDOG_TOVALL_WR(x, v)  (HW_WDOG_TOVALL(x).U = (v))
 608 #define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) |  (v)))
 609 #define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v)))
 610 #define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^  (v)))
 611 /*@}*/
 612
 613 /*
 614  * Constants & macros for individual WDOG_TOVALL bitfields
 615  */
 616
 617 /*!
 618  * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
 619  *
 620  * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
 621  * timer. It is defined in terms of cycles of the watchdog clock.
 622  */
 623 /*@{*/
 624 #define BP_WDOG_TOVALL_TOVALLOW (0U)       /*!< Bit position for WDOG_TOVALL_TOVALLOW. */
 625 #define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU)  /*!< Bit mask for WDOG_TOVALL_TOVALLOW. */
 626 #define BS_WDOG_TOVALL_TOVALLOW (16U)      /*!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. */
 627
 628 /*! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. */
 629 #define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U)
 630
 631 /*! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. */
 632 #define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW)
 633
 634 /*! @brief Set the TOVALLOW field to a new value. */
 635 #define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v))
 636 /*@}*/
 637
 638 /*******************************************************************************
 639  * HW_WDOG_WINH - Watchdog Window Register High
 640  ******************************************************************************/
 641
 642 /*!
 643  * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
 644  *
 645  * Reset value: 0x0000U
 646  *
 647  * You must set the Window Register value lower than the Time-out Value Register.
 648  */
 649 typedef union _hw_wdog_winh
 650 {
 651     uint16_t U;
 652     struct _hw_wdog_winh_bitfields
 653     {
 654         uint16_t WINHIGH : 16;         /*!< [15:0]  */
 655     } B;
 656 } hw_wdog_winh_t;
 657
 658 /*!
 659  * @name Constants and macros for entire WDOG_WINH register
 660  */
 661 /*@{*/
 662 #define HW_WDOG_WINH_ADDR(x)     ((x) + 0x8U)
 663
 664 #define HW_WDOG_WINH(x)          (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR(x))
 665 #define HW_WDOG_WINH_RD(x)       (HW_WDOG_WINH(x).U)
 666 #define HW_WDOG_WINH_WR(x, v)    (HW_WDOG_WINH(x).U = (v))
 667 #define HW_WDOG_WINH_SET(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) |  (v)))
 668 #define HW_WDOG_WINH_CLR(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v)))
 669 #define HW_WDOG_WINH_TOG(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^  (v)))
 670 /*@}*/
 671
 672 /*
 673  * Constants & macros for individual WDOG_WINH bitfields
 674  */
 675
 676 /*!
 677  * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
 678  *
 679  * Defines the upper 16 bits of the 32-bit window for the windowed mode of
 680  * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
 681  * In this mode, the watchdog can be refreshed only when the timer has reached a
 682  * value greater than or equal to this window length. A refresh outside this
 683  * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
 684  * system.
 685  */
 686 /*@{*/
 687 #define BP_WDOG_WINH_WINHIGH (0U)          /*!< Bit position for WDOG_WINH_WINHIGH. */
 688 #define BM_WDOG_WINH_WINHIGH (0xFFFFU)     /*!< Bit mask for WDOG_WINH_WINHIGH. */
 689 #define BS_WDOG_WINH_WINHIGH (16U)         /*!< Bit field size in bits for WDOG_WINH_WINHIGH. */
 690
 691 /*! @brief Read current value of the WDOG_WINH_WINHIGH field. */
 692 #define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U)
 693
 694 /*! @brief Format value for bitfield WDOG_WINH_WINHIGH. */
 695 #define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH)
 696
 697 /*! @brief Set the WINHIGH field to a new value. */
 698 #define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v))
 699 /*@}*/
 700
 701 /*******************************************************************************
 702  * HW_WDOG_WINL - Watchdog Window Register Low
 703  ******************************************************************************/
 704
 705 /*!
 706  * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
 707  *
 708  * Reset value: 0x0010U
 709  *
 710  * You must set the Window Register value lower than the Time-out Value Register.
 711  */
 712 typedef union _hw_wdog_winl
 713 {
 714     uint16_t U;
 715     struct _hw_wdog_winl_bitfields
 716     {
 717         uint16_t WINLOW : 16;          /*!< [15:0]  */
 718     } B;
 719 } hw_wdog_winl_t;
 720
 721 /*!
 722  * @name Constants and macros for entire WDOG_WINL register
 723  */
 724 /*@{*/
 725 #define HW_WDOG_WINL_ADDR(x)     ((x) + 0xAU)
 726
 727 #define HW_WDOG_WINL(x)          (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR(x))
 728 #define HW_WDOG_WINL_RD(x)       (HW_WDOG_WINL(x).U)
 729 #define HW_WDOG_WINL_WR(x, v)    (HW_WDOG_WINL(x).U = (v))
 730 #define HW_WDOG_WINL_SET(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) |  (v)))
 731 #define HW_WDOG_WINL_CLR(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v)))
 732 #define HW_WDOG_WINL_TOG(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^  (v)))
 733 /*@}*/
 734
 735 /*
 736  * Constants & macros for individual WDOG_WINL bitfields
 737  */
 738
 739 /*!
 740  * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
 741  *
 742  * Defines the lower 16 bits of the 32-bit window for the windowed mode of
 743  * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
 744  * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
 745  * reaches a value greater than or equal to this window length value. A refresh
 746  * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
 747  * then resets the system.
 748  */
 749 /*@{*/
 750 #define BP_WDOG_WINL_WINLOW  (0U)          /*!< Bit position for WDOG_WINL_WINLOW. */
 751 #define BM_WDOG_WINL_WINLOW  (0xFFFFU)     /*!< Bit mask for WDOG_WINL_WINLOW. */
 752 #define BS_WDOG_WINL_WINLOW  (16U)         /*!< Bit field size in bits for WDOG_WINL_WINLOW. */
 753
 754 /*! @brief Read current value of the WDOG_WINL_WINLOW field. */
 755 #define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U)
 756
 757 /*! @brief Format value for bitfield WDOG_WINL_WINLOW. */
 758 #define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW)
 759
 760 /*! @brief Set the WINLOW field to a new value. */
 761 #define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v))
 762 /*@}*/
 763
 764 /*******************************************************************************
 765  * HW_WDOG_REFRESH - Watchdog Refresh register
 766  ******************************************************************************/
 767
 768 /*!
 769  * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
 770  *
 771  * Reset value: 0xB480U
 772  */
 773 typedef union _hw_wdog_refresh
 774 {
 775     uint16_t U;
 776     struct _hw_wdog_refresh_bitfields
 777     {
 778         uint16_t WDOGREFRESH : 16;     /*!< [15:0]  */
 779     } B;
 780 } hw_wdog_refresh_t;
 781
 782 /*!
 783  * @name Constants and macros for entire WDOG_REFRESH register
 784  */
 785 /*@{*/
 786 #define HW_WDOG_REFRESH_ADDR(x)  ((x) + 0xCU)
 787
 788 #define HW_WDOG_REFRESH(x)       (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR(x))
 789 #define HW_WDOG_REFRESH_RD(x)    (HW_WDOG_REFRESH(x).U)
 790 #define HW_WDOG_REFRESH_WR(x, v) (HW_WDOG_REFRESH(x).U = (v))
 791 #define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) |  (v)))
 792 #define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v)))
 793 #define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^  (v)))
 794 /*@}*/
 795
 796 /*
 797  * Constants & macros for individual WDOG_REFRESH bitfields
 798  */
 799
 800 /*!
 801  * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
 802  *
 803  * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
 804  * bus clock cycles written to this register refreshes the WDOG and prevents it
 805  * from resetting the system. Writing a value other than the above mentioned
 806  * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
 807  * IRQRSTEN is set, it interrupts and then resets the system.
 808  */
 809 /*@{*/
 810 #define BP_WDOG_REFRESH_WDOGREFRESH (0U)   /*!< Bit position for WDOG_REFRESH_WDOGREFRESH. */
 811 #define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /*!< Bit mask for WDOG_REFRESH_WDOGREFRESH. */
 812 #define BS_WDOG_REFRESH_WDOGREFRESH (16U)  /*!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. */
 813
 814 /*! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. */
 815 #define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U)
 816
 817 /*! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. */
 818 #define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH)
 819
 820 /*! @brief Set the WDOGREFRESH field to a new value. */
 821 #define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v))
 822 /*@}*/
 823
 824 /*******************************************************************************
 825  * HW_WDOG_UNLOCK - Watchdog Unlock register
 826  ******************************************************************************/
 827
 828 /*!
 829  * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
 830  *
 831  * Reset value: 0xD928U
 832  */
 833 typedef union _hw_wdog_unlock
 834 {
 835     uint16_t U;
 836     struct _hw_wdog_unlock_bitfields
 837     {
 838         uint16_t WDOGUNLOCK : 16;      /*!< [15:0]  */
 839     } B;
 840 } hw_wdog_unlock_t;
 841
 842 /*!
 843  * @name Constants and macros for entire WDOG_UNLOCK register
 844  */
 845 /*@{*/
 846 #define HW_WDOG_UNLOCK_ADDR(x)   ((x) + 0xEU)
 847
 848 #define HW_WDOG_UNLOCK(x)        (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR(x))
 849 #define HW_WDOG_UNLOCK_RD(x)     (HW_WDOG_UNLOCK(x).U)
 850 #define HW_WDOG_UNLOCK_WR(x, v)  (HW_WDOG_UNLOCK(x).U = (v))
 851 #define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) |  (v)))
 852 #define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v)))
 853 #define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^  (v)))
 854 /*@}*/
 855
 856 /*
 857  * Constants & macros for individual WDOG_UNLOCK bitfields
 858  */
 859
 860 /*!
 861  * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
 862  *
 863  * Writing the unlock sequence values to this register to makes the watchdog
 864  * write-once registers writable again. The required unlock sequence is 0xC520
 865  * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
 866  * window equal in length to the WCT within which you can update the registers.
 867  * Writing a value other than the above mentioned sequence or if the sequence is
 868  * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
 869  * and then resets the system. The unlock sequence is effective only if
 870  * ALLOWUPDATE is set.
 871  */
 872 /*@{*/
 873 #define BP_WDOG_UNLOCK_WDOGUNLOCK (0U)     /*!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. */
 874 #define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /*!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. */
 875 #define BS_WDOG_UNLOCK_WDOGUNLOCK (16U)    /*!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. */
 876
 877 /*! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. */
 878 #define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U)
 879
 880 /*! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. */
 881 #define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK)
 882
 883 /*! @brief Set the WDOGUNLOCK field to a new value. */
 884 #define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v))
 885 /*@}*/
 886
 887 /*******************************************************************************
 888  * HW_WDOG_TMROUTH - Watchdog Timer Output Register High
 889  ******************************************************************************/
 890
 891 /*!
 892  * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
 893  *
 894  * Reset value: 0x0000U
 895  */
 896 typedef union _hw_wdog_tmrouth
 897 {
 898     uint16_t U;
 899     struct _hw_wdog_tmrouth_bitfields
 900     {
 901         uint16_t TIMEROUTHIGH : 16;    /*!< [15:0]  */
 902     } B;
 903 } hw_wdog_tmrouth_t;
 904
 905 /*!
 906  * @name Constants and macros for entire WDOG_TMROUTH register
 907  */
 908 /*@{*/
 909 #define HW_WDOG_TMROUTH_ADDR(x)  ((x) + 0x10U)
 910
 911 #define HW_WDOG_TMROUTH(x)       (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR(x))
 912 #define HW_WDOG_TMROUTH_RD(x)    (HW_WDOG_TMROUTH(x).U)
 913 #define HW_WDOG_TMROUTH_WR(x, v) (HW_WDOG_TMROUTH(x).U = (v))
 914 #define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) |  (v)))
 915 #define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v)))
 916 #define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^  (v)))
 917 /*@}*/
 918
 919 /*
 920  * Constants & macros for individual WDOG_TMROUTH bitfields
 921  */
 922
 923 /*!
 924  * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
 925  *
 926  * Shows the value of the upper 16 bits of the watchdog timer.
 927  */
 928 /*@{*/
 929 #define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U)  /*!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. */
 930 #define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /*!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. */
 931 #define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /*!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. */
 932
 933 /*! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. */
 934 #define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U)
 935
 936 /*! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. */
 937 #define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
 938
 939 /*! @brief Set the TIMEROUTHIGH field to a new value. */
 940 #define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v))
 941 /*@}*/
 942
 943 /*******************************************************************************
 944  * HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
 945  ******************************************************************************/
 946
 947 /*!
 948  * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
 949  *
 950  * Reset value: 0x0000U
 951  *
 952  * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
 953  * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
 954  * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
 955  * the watchdog timer.
 956  */
 957 typedef union _hw_wdog_tmroutl
 958 {
 959     uint16_t U;
 960     struct _hw_wdog_tmroutl_bitfields
 961     {
 962         uint16_t TIMEROUTLOW : 16;     /*!< [15:0]  */
 963     } B;
 964 } hw_wdog_tmroutl_t;
 965
 966 /*!
 967  * @name Constants and macros for entire WDOG_TMROUTL register
 968  */
 969 /*@{*/
 970 #define HW_WDOG_TMROUTL_ADDR(x)  ((x) + 0x12U)
 971
 972 #define HW_WDOG_TMROUTL(x)       (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR(x))
 973 #define HW_WDOG_TMROUTL_RD(x)    (HW_WDOG_TMROUTL(x).U)
 974 #define HW_WDOG_TMROUTL_WR(x, v) (HW_WDOG_TMROUTL(x).U = (v))
 975 #define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) |  (v)))
 976 #define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v)))
 977 #define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^  (v)))
 978 /*@}*/
 979
 980 /*
 981  * Constants & macros for individual WDOG_TMROUTL bitfields
 982  */
 983
 984 /*!
 985  * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
 986  *
 987  * Shows the value of the lower 16 bits of the watchdog timer.
 988  */
 989 /*@{*/
 990 #define BP_WDOG_TMROUTL_TIMEROUTLOW (0U)   /*!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. */
 991 #define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /*!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. */
 992 #define BS_WDOG_TMROUTL_TIMEROUTLOW (16U)  /*!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. */
 993
 994 /*! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. */
 995 #define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U)
 996
 997 /*! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. */
 998 #define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW)
 999
1000 /*! @brief Set the TIMEROUTLOW field to a new value. */
1001 #define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v))
1002 /*@}*/
1003
1004 /*******************************************************************************
1005  * HW_WDOG_RSTCNT - Watchdog Reset Count register
1006  ******************************************************************************/
1007
1008 /*!
1009  * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
1010  *
1011  * Reset value: 0x0000U
1012  */
1013 typedef union _hw_wdog_rstcnt
1014 {
1015     uint16_t U;
1016     struct _hw_wdog_rstcnt_bitfields
1017     {
1018         uint16_t RSTCNT : 16;          /*!< [15:0]  */
1019     } B;
1020 } hw_wdog_rstcnt_t;
1021
1022 /*!
1023  * @name Constants and macros for entire WDOG_RSTCNT register
1024  */
1025 /*@{*/
1026 #define HW_WDOG_RSTCNT_ADDR(x)   ((x) + 0x14U)
1027
1028 #define HW_WDOG_RSTCNT(x)        (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR(x))
1029 #define HW_WDOG_RSTCNT_RD(x)     (HW_WDOG_RSTCNT(x).U)
1030 #define HW_WDOG_RSTCNT_WR(x, v)  (HW_WDOG_RSTCNT(x).U = (v))
1031 #define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) |  (v)))
1032 #define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v)))
1033 #define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^  (v)))
1034 /*@}*/
1035
1036 /*
1037  * Constants & macros for individual WDOG_RSTCNT bitfields
1038  */
1039
1040 /*!
1041  * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
1042  *
1043  * Counts the number of times the watchdog resets the system. This register is
1044  * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
1045  * the contents of this register.
1046  */
1047 /*@{*/
1048 #define BP_WDOG_RSTCNT_RSTCNT (0U)         /*!< Bit position for WDOG_RSTCNT_RSTCNT. */
1049 #define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU)    /*!< Bit mask for WDOG_RSTCNT_RSTCNT. */
1050 #define BS_WDOG_RSTCNT_RSTCNT (16U)        /*!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. */
1051
1052 /*! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. */
1053 #define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U)
1054
1055 /*! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. */
1056 #define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT)
1057
1058 /*! @brief Set the RSTCNT field to a new value. */
1059 #define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v))
1060 /*@}*/
1061
1062 /*******************************************************************************
1063  * HW_WDOG_PRESC - Watchdog Prescaler register
1064  ******************************************************************************/
1065
1066 /*!
1067  * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
1068  *
1069  * Reset value: 0x0400U
1070  */
1071 typedef union _hw_wdog_presc
1072 {
1073     uint16_t U;
1074     struct _hw_wdog_presc_bitfields
1075     {
1076         uint16_t RESERVED0 : 8;        /*!< [7:0]  */
1077         uint16_t PRESCVAL : 3;         /*!< [10:8]  */
1078         uint16_t RESERVED1 : 5;        /*!< [15:11]  */
1079     } B;
1080 } hw_wdog_presc_t;
1081
1082 /*!
1083  * @name Constants and macros for entire WDOG_PRESC register
1084  */
1085 /*@{*/
1086 #define HW_WDOG_PRESC_ADDR(x)    ((x) + 0x16U)
1087
1088 #define HW_WDOG_PRESC(x)         (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR(x))
1089 #define HW_WDOG_PRESC_RD(x)      (HW_WDOG_PRESC(x).U)
1090 #define HW_WDOG_PRESC_WR(x, v)   (HW_WDOG_PRESC(x).U = (v))
1091 #define HW_WDOG_PRESC_SET(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) |  (v)))
1092 #define HW_WDOG_PRESC_CLR(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v)))
1093 #define HW_WDOG_PRESC_TOG(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^  (v)))
1094 /*@}*/
1095
1096 /*
1097  * Constants & macros for individual WDOG_PRESC bitfields
1098  */
1099
1100 /*!
1101  * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
1102  *
1103  * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
1104  * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
1105  * 1) to provide the prescaled WDOG_CLK.
1106  */
1107 /*@{*/
1108 #define BP_WDOG_PRESC_PRESCVAL (8U)        /*!< Bit position for WDOG_PRESC_PRESCVAL. */
1109 #define BM_WDOG_PRESC_PRESCVAL (0x0700U)   /*!< Bit mask for WDOG_PRESC_PRESCVAL. */
1110 #define BS_WDOG_PRESC_PRESCVAL (3U)        /*!< Bit field size in bits for WDOG_PRESC_PRESCVAL. */
1111
1112 /*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
1113 #define BR_WDOG_PRESC_PRESCVAL(x) (HW_WDOG_PRESC(x).B.PRESCVAL)
1114
1115 /*! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. */
1116 #define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL)
1117
1118 /*! @brief Set the PRESCVAL field to a new value. */
1119 #define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
1120 /*@}*/
1121
1122 /*******************************************************************************
1123  * hw_wdog_t - module struct
1124  ******************************************************************************/
1125 /*!
1126  * @brief All WDOG module registers.
1127  */
1128 #pragma pack(1)
1129 typedef struct _hw_wdog
1130 {
1131     __IO hw_wdog_stctrlh_t STCTRLH;        /*!< [0x0] Watchdog Status and Control Register High */
1132     __IO hw_wdog_stctrll_t STCTRLL;        /*!< [0x2] Watchdog Status and Control Register Low */
1133     __IO hw_wdog_tovalh_t TOVALH;          /*!< [0x4] Watchdog Time-out Value Register High */
1134     __IO hw_wdog_tovall_t TOVALL;          /*!< [0x6] Watchdog Time-out Value Register Low */
1135     __IO hw_wdog_winh_t WINH;              /*!< [0x8] Watchdog Window Register High */
1136     __IO hw_wdog_winl_t WINL;              /*!< [0xA] Watchdog Window Register Low */
1137     __IO hw_wdog_refresh_t REFRESH;        /*!< [0xC] Watchdog Refresh register */
1138     __IO hw_wdog_unlock_t UNLOCK;          /*!< [0xE] Watchdog Unlock register */
1139     __IO hw_wdog_tmrouth_t TMROUTH;        /*!< [0x10] Watchdog Timer Output Register High */
1140     __IO hw_wdog_tmroutl_t TMROUTL;        /*!< [0x12] Watchdog Timer Output Register Low */
1141     __IO hw_wdog_rstcnt_t RSTCNT;          /*!< [0x14] Watchdog Reset Count register */
1142     __IO hw_wdog_presc_t PRESC;            /*!< [0x16] Watchdog Prescaler register */
1143 } hw_wdog_t;
1144 #pragma pack()
1145
1146 /*! @brief Macro to access all WDOG registers. */
1147 /*! @param x WDOG module instance base address. */
1148 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1149  *     use the '&' operator, like <code>&HW_WDOG(WDOG_BASE)</code>. */
1150 #define HW_WDOG(x)     (*(hw_wdog_t *)(x))
1151
1152 #endif /* __HW_WDOG_REGISTERS_H__ */
1153 /* EOF */