2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #ifndef __EDMA_HAL_H__
31 #define __EDMA_HAL_H__
36 #include "fsl_edma_features.h"
37 #include "fsl_device_registers.h"
40 * @addtogroup edma_hal
44 /*******************************************************************************
46 ******************************************************************************/
47 /*! @brief Error code for the eDMA Driver. */
48 typedef enum _edma_status
{
49 kStatus_EDMA_Success
= 0U,
50 kStatus_EDMA_InvalidArgument
= 1U, /*!< Parameter is invalid. */
51 kStatus_EDMA_Fail
= 2U /*!< Failed operation. */
54 /*! @brief eDMA channel arbitration algorithm used for selection among channels. */
55 typedef enum _edma_channel_arbitration
{
56 kEDMAChnArbitrationFixedPriority
= 0U, /*!< Fixed Priority arbitration is used for selection
58 kEDMAChnArbitrationRoundrobin
/*!< Round-Robin arbitration is used for selection among
60 } edma_channel_arbitration_t
;
62 /*! @brief eDMA channel priority setting */
63 typedef enum _edma_chn_priority
{
64 kEDMAChnPriority0
= 0U,
80 } edma_channel_priority_t
;
82 #if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
83 /*! @brief eDMA group arbitration algorithm used for selection among channels. */
84 typedef enum _edma_group_arbitration
86 kEDMAGroupArbitrationFixedPriority
= 0U, /*!< Fixed Priority arbitration is used for
87 selection among eDMA groups. */
88 kEDMAGroupArbitrationRoundrobin
/*!< Round-Robin arbitration is used for selection
89 among eDMA channels. */
90 } edma_group_arbitration_t
;
92 /*! @brief eDMA group priority setting */
93 typedef enum _edma_group_priority
{
94 kEDMAGroup0PriorityLowGroup1PriorityHigh
, /*!< eDMA group 0's priority is lower priority.
95 eDMA group 1's priority is higher priority. */
96 kEDMAGroup0PriorityHighGroup1PriorityLow
/*!< eDMA group 0's priority is higher priority.
97 eDMA group 1's priority is lower priority. */
98 } edma_group_priority_t
;
101 /*! @brief eDMA modulo configuration */
102 typedef enum _edma_modulo
{
103 kEDMAModuloDisable
= 0U,
120 kEDMAModulo128Kbytes
,
121 kEDMAModulo256Kbytes
,
122 kEDMAModulo512Kbytes
,
130 kEDMAModulo128Mbytes
,
131 kEDMAModulo256Mbytes
,
132 kEDMAModulo512Mbytes
,
137 /*! @brief eDMA transfer configuration */
138 typedef enum _edma_transfer_size
{
139 kEDMATransferSize_1Bytes
= 0x0U
,
140 kEDMATransferSize_2Bytes
= 0x1U
,
141 kEDMATransferSize_4Bytes
= 0x2U
,
142 kEDMATransferSize_16Bytes
= 0x4U
,
143 kEDMATransferSize_32Bytes
= 0x5U
144 } edma_transfer_size_t
;
147 * @brief eDMA transfer size configuration.
149 * This structure configures the basic source/destination transfer attribute.
150 * This figure shows the eDMA's transfer model:
151 * _________________________________________________
152 * | Transfer Size | |
153 * Minor Loop |_______________| Major loop Count 1 |
154 * Count | Transfer Size | |
155 * ____________|_______________|____________________|--> Minor loop complete
156 * ____________________________________
158 * |_______________| Major Loop Count 2 |
160 * |_______________|____________________|--> Minor loop Complete
162 * ---------------------------------------------------------> Major loop complete
165 typedef struct EDMATransferConfig
{
166 uint32_t srcAddr
; /*!< Memory address pointing to the source data. */
167 uint32_t destAddr
; /*!< Memory address pointing to the destination data. */
168 edma_transfer_size_t srcTransferSize
; /*!< Source data transfer size. */
169 edma_transfer_size_t destTransferSize
; /*!< Destination data transfer size. */
170 int16_t srcOffset
; /*!< Sign-extended offset applied to the current source address to
171 form the next-state value as each source read/write is
174 uint32_t srcLastAddrAdjust
; /*!< Last source address adjustment. */
175 uint32_t destLastAddrAdjust
; /*!< Last destination address adjustment. Note here it is only
176 valid when scatter/gather feature is not enabled. */
177 edma_modulo_t srcModulo
; /*!< Source address modulo. */
178 edma_modulo_t destModulo
; /*!< Destination address modulo. */
179 uint32_t minorLoopCount
; /*!< Minor bytes transfer count. Number of bytes to be transferred
180 in each service request of the channel. */
181 uint16_t majorLoopCount
; /*!< Major iteration count. */
182 } edma_transfer_config_t
;
184 /*! @brief eDMA channel configuration. */
185 typedef enum _edma_channel_indicator
{
186 kEDMAChannel0
= 0U, /*!< Channel 0. */
190 #if (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U)
197 kEDMAChannel10
= 10U,
198 kEDMAChannel11
= 11U,
199 kEDMAChannel12
= 12U,
200 kEDMAChannel13
= 13U,
201 kEDMAChannel14
= 14U,
202 kEDMAChannel15
= 15U,
204 #if (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U)
205 kEDMAChannel16
= 16U,
206 kEDMAChannel17
= 17U,
207 kEDMAChannel18
= 18U,
208 kEDMAChannel19
= 19U,
209 kEDMAChannel20
= 20U,
210 kEDMAChannel21
= 21U,
211 kEDMAChannel22
= 22U,
212 kEDMAChannel23
= 23U,
213 kEDMAChannel24
= 24U,
214 kEDMAChannel25
= 25U,
215 kEDMAChannel26
= 26U,
216 kEDMAChannel27
= 27U,
217 kEDMAChannel28
= 28U,
218 kEDMAChannel29
= 29U,
219 kEDMAChannel30
= 30U,
220 kEDMAChannel31
= 31U,
222 kEDMAAllChannel
= 64U
223 } edma_channel_indicator_t
;
225 /*! @brief eDMA TCD Minor loop mapping configuration */
226 typedef struct EDMAMinorLoopOffsetConfig
{
227 bool enableSrcMinorloop
; /*!< Enable(true) or Disable(false) source minor loop offset. */
228 bool enableDestMinorloop
; /*!< Enable(true) or Disable(false) destination minor loop offset. */
229 uint32_t offset
; /*!< Offset for minor loop mapping. */
230 } edma_minorloop_offset_config_t
;
232 /*! @brief Error status of the eDMA module */
233 typedef union EDMAErrorStatusAll
{
235 uint32_t destinationBusError
: 1; /*!< Bus error on destination address */
236 uint32_t sourceBusError
: 1; /*!< Bus error on the SRC address */
237 uint32_t scatterOrGatherConfigurationError
: 1; /*!< Error on the Scatter/Gather address */
238 uint32_t nbyteOrCiterConfigurationError
: 1; /*!< NBYTES/CITER configuration error */
239 uint32_t destinationOffsetError
: 1; /*!< Destination offset error */
240 uint32_t destinationAddressError
: 1; /*!< Destination address error */
241 uint32_t sourceOffsetError
: 1; /*!< Source offset error */
242 uint32_t sourceAddressError
: 1; /*!< Source address error */
243 uint32_t errorChannel
: 5; /*!< Error channel number of the cancelled
245 uint32_t _reserved1
: 1;
246 uint32_t channelPriorityError
: 1; /*!< Channel priority error */
247 uint32_t groupPriorityError
: 1; /*!< Group priority error */
248 uint32_t transferCancelledError
: 1; /*!< Transfer cancelled */
249 uint32_t _reserved0
: 14;
250 uint32_t orOfAllError
: 1; /*!< Logical OR all ERR status bits */
253 } edma_error_status_all_t
;
255 /*! @brief Bandwidth control configuration */
256 typedef enum _edma_bandwidth_config
{
257 kEDMABandwidthStallNone
= 0U, /*!< No eDMA engine stalls. */
258 kEDMABandwidthStall4Cycle
= 2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
259 kEDMABandwidthStall8Cycle
= 3U /*!< eDMA engine stalls for 8 cycles after each read/write. */
260 } edma_bandwidth_config_t
;
262 /*! @brief eDMA TCD */
263 typedef struct EDMASoftwareTcd
{
285 } edma_software_tcd_t
;
287 /*******************************************************************************
289 ******************************************************************************/
291 #if defined(__cplusplus)
296 * @name eDMA HAL driver module level operation
301 * @brief Initializes eDMA module to known state.
303 * @param baseAddr Register base address for eDMA module.
305 void EDMA_HAL_Init(uint32_t baseAddr
);
308 * @brief Cancels the remaining data transfer.
310 * This function stops the executing channel and forces the minor loop
311 * to finish. The cancellation takes effect after the last write of the
312 * current read/write sequence. The CX clears itself after the cancel has
313 * been honored. This cancel retires the channel normally as if the minor
314 * loop had completed.
316 * @param baseAddr Register base address for eDMA module.
318 void EDMA_HAL_CancelTransfer(uint32_t baseAddr
);
321 * @brief Cancels the remaining data transfer and treats it as an error condition.
323 * This function stops the executing channel and forces the minor loop
324 * to finish. The cancellation takes effect after the last write of the
325 * current read/write sequence. The CX clears itself after the cancel has
326 * been honored. This cancel retires the channel normally as if the minor
327 * loop had completed. Additional thing is to treat this operation as an error
330 * @param baseAddr Register base address for eDMA module.
332 void EDMA_HAL_ErrorCancelTransfer(uint32_t baseAddr
);
335 * @brief Halts/Un-halts the DMA Operations.
337 * This function stalls/un-stalls the start of any new channels. Executing channels are allowed
340 * @param baseAddr Register base address for eDMA module.
341 * @param halt Halts (true) or un-halts (false) eDMA transfer.
343 static inline void EDMA_HAL_SetHaltCmd(uint32_t baseAddr
, bool halt
)
345 BW_DMA_CR_HALT(baseAddr
, halt
);
349 * @brief Halts or does not halt the eDMA module when an error occurs.
351 * An error causes the HALT bit to be set. Subsequently, all service requests are ignored until the
352 * HALT bit is cleared.
354 * @param baseAddr Register base address for eDMA module.
355 * @param haltOnError Halts (true) or not halt (false) eDMA module when an error occurs.
357 static inline void EDMA_HAL_SetHaltOnErrorCmd(uint32_t baseAddr
, bool haltOnError
)
359 BW_DMA_CR_HOE(baseAddr
, haltOnError
);
363 * @brief Enables/Disables the eDMA DEBUG mode.
365 * This function enables/disables the eDMA Debug mode.
366 * When in debug mode, the DMA stalls the start of a new
367 * channel. Executing channels are allowed to complete. Channel execution resumes
368 * either when the system exits debug mode or when the EDBG bit is cleared.
370 * @param baseAddr Register base address for eDMA module.
371 * @param enable Enables (true) or Disable (false) eDMA module debug mode.
373 static inline void EDMA_HAL_SetDebugCmd(uint32_t baseAddr
, bool enable
)
375 BW_DMA_CR_EDBG(baseAddr
, enable
);
380 * @name eDMA HAL driver channel priority and arbitration configuration.
384 * @brief Sets the preempt and preemption feature for the eDMA channel.
386 * This function sets the preempt and preemption features.
388 * @param baseAddr Register base address for eDMA module.
389 * @param channel eDMA channel number.
390 * @param preempt eDMA channel can't suspend a lower priority channel (true). eDMA channel can
391 * suspend a lower priority channel (false).
392 * @param preemption eDMA channel can be temporarily suspended by the service request of a higher
393 * priority channel (true). eDMA channel can't be suspended by a higher priority channel (false).
395 static inline void EDMA_HAL_SetChannelPreemptMode(
396 uint32_t baseAddr
, uint32_t channel
, bool preempt
, bool preemption
)
398 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
399 BW_DMA_DCHPRIn_DPA(baseAddr
, HW_DMA_DCHPRIn_CHANNEL(channel
), preempt
);
400 BW_DMA_DCHPRIn_ECP(baseAddr
, HW_DMA_DCHPRIn_CHANNEL(channel
), preemption
);
404 * @brief Sets the eDMA channel priority.
406 * @param baseAddr Register base address for eDMA module.
407 * @param channel eDMA channel number.
408 * @param priority Priority of the DMA channel. Different channels should have different priority
409 * setting inside a group.
411 static inline void EDMA_HAL_SetChannelPriority(
412 uint32_t baseAddr
, uint32_t channel
, edma_channel_priority_t priority
)
414 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
415 BW_DMA_DCHPRIn_CHPRI(baseAddr
, HW_DMA_DCHPRIn_CHANNEL(channel
), priority
);
418 * @brief Sets the channel arbitration algorithm.
420 * @param baseAddr Register base address for eDMA module.
421 * @param channelArbitration Round-Robin way for fixed priority way.
423 static inline void EDMA_HAL_SetChannelArbitrationMode(
424 uint32_t baseAddr
, edma_channel_arbitration_t channelArbitration
)
426 BW_DMA_CR_ERCA(baseAddr
, channelArbitration
);
429 #if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
431 * @brief Configures the group priority.
433 * This function configures the priority for group 0 and group 1.
435 * @param baseAddr Register base address for eDMA module.
436 * @param groupPriority Group priority configuration. Note that each group get its own
439 void EDMA_HAL_SetGroupPriority(uint32_t baseAddr
, edma_group_priority_t groupPriority
);
442 * @brief Sets the eDMA group arbitration algorithm.
444 * @param baseAddr Register base address for eDMA module.
445 * @param groupArbitration Group arbitration way. Fixed-Priority way or Round-Robin way.
447 static inline void EDMA_HAL_SetGroupArbitrationMode(
448 uint32_t baseAddr
, edma_group_arbitration_t groupArbitration
)
450 BW_DMA_CR_ERGA(baseAddr
, groupArbitration
);
456 * @name eDMA HAL driver configuration and operation.
460 * @brief Enables/Disables the minor loop mapping.
462 * This function enables/disables the minor loop mapping feature.
463 * If enabled, the NBYTES is redefined to include the individual enable fields and the NBYTES field. The
464 * individual enable fields allow the minor loop offset to be applied to the source address, the
465 * destination address, or both. The NBYTES field is reduced when either offset is enabled.
467 * @param baseAddr Register base address for eDMA module.
468 * @param enable Enables (true) or Disable (false) minor loop mapping.
470 static inline void EDMA_HAL_SetMinorLoopMappingCmd(uint32_t baseAddr
, bool enable
)
472 BW_DMA_CR_EMLM(baseAddr
, enable
);
476 * @brief Enables or disables the continuous transfer mode.
478 * This function enables or disables the continuous transfer. If set, a minor loop channel link
479 * does not go through the channel arbitration before being activated again. Upon minor loop
480 * completion, the channel activates again if that channel has a minor loop channel link enabled and
481 * the link channel is itself.
483 * @param baseAddr Register base address for eDMA module.
484 * @param continuous Enables (true) or Disable (false) continuous transfer mode.
486 static inline void EDMA_HAL_SetContinuousLinkCmd(uint32_t baseAddr
, bool continuous
)
488 BW_DMA_CR_CLM(baseAddr
, continuous
);
492 * @brief Gets the error status of the eDMA module.
494 * @param baseAddr Register base address for eDMA module.
495 * @return Detailed information of the error type in the eDMA module.
497 static inline uint32_t EDMA_HAL_GetErrorStatus(uint32_t baseAddr
)
499 return HW_DMA_ES_RD(baseAddr
);
503 * @brief Enables/Disables the error interrupt for channels.
505 * @param baseAddr Register base address for eDMA module.
506 * @param enable Enable(true) or Disable (false) error interrupt.
507 * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt
508 * will be enabled/disabled.
510 void EDMA_HAL_SetErrorIntCmd(uint32_t baseAddr
, bool enable
, edma_channel_indicator_t channel
);
513 * @brief Checks whether the eDMA channel error interrupt is enabled or disabled.
515 * @param baseAddr Register base address for eDMA module.
516 * @param channel eDMA channel number.
517 * @return Error interrupt is enabled (true) or disabled (false).
519 bool EDMA_HAL_GetErrorIntCmd(uint32_t baseAddr
, uint32_t channel
);
522 * @brief Gets the eDMA error interrupt status.
524 * @param baseAddr Register base address for eDMA module.
525 * @param channel eDMA channel number.
526 * @return 32 bit variable indicating error channels. If error happens on eDMA channel n, the bit n
527 * of this variable is '1'. If not, the bit n of this variable is '0'.
529 static inline uint32_t EDMA_HAL_GetErrorIntStatusFlag(uint32_t baseAddr
)
531 return HW_DMA_ERR_RD(baseAddr
);
535 * @brief Clears the error interrupt status for the eDMA channel or channels.
537 * @param baseAddr Register base address for eDMA module.
538 * @param enable Enable(true) or Disable (false) error interrupt.
539 * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt
540 * status will be cleared.
542 static inline void EDMA_HAL_ClearErrorIntStatusFlag(
543 uint32_t baseAddr
, edma_channel_indicator_t channel
)
545 HW_DMA_CERR_WR(baseAddr
, channel
);
549 * @brief Enables/Disables the DMA request for the channel or all channels.
551 * @param baseAddr Register base address for eDMA module.
552 * @param enable Enable(true) or Disable (false) DMA request.
553 * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels DMA request
554 * are enabled/disabled.
556 void EDMA_HAL_SetDmaRequestCmd(uint32_t baseAddr
, edma_channel_indicator_t channel
,bool enable
);
559 * @brief Checks whether the eDMA channel DMA request is enabled or disabled.
561 * @param baseAddr Register base address for eDMA module.
562 * @param channel eDMA channel number.
563 * @return DMA request is enabled (true) or disabled (false).
565 static inline bool EDMA_HAL_GetDmaRequestCmd(uint32_t baseAddr
, uint32_t channel
)
567 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
569 return ((HW_DMA_ERQ_RD(baseAddr
) >> channel
) & 1U);
573 * @brief Gets the eDMA channel DMA request status.
575 * @param baseAddr Register base address for eDMA module.
576 * @param channel eDMA channel number.
577 * @return Hardware request is triggered in this eDMA channel (true) or not be triggered in this
580 static inline bool EDMA_HAL_GetDmaRequestStatusFlag(uint32_t baseAddr
, uint32_t channel
)
582 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
583 return (((uint32_t)HW_DMA_HRS_RD(baseAddr
) >> channel
) & 1U);
587 * @brief Clears the done status for a channel or all channels.
589 * @param baseAddr Register base address for eDMA module.
590 * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' done status will
593 static inline void EDMA_HAL_ClearDoneStatusFlag(uint32_t baseAddr
, edma_channel_indicator_t channel
)
595 HW_DMA_CDNE_WR(baseAddr
, channel
);
599 * @brief Triggers the eDMA channel.
601 * @param baseAddr Register base address for eDMA module.
602 * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels are tirggere.
604 static inline void EDMA_HAL_TriggerChannelStart(uint32_t baseAddr
, edma_channel_indicator_t channel
)
606 HW_DMA_SSRT_WR(baseAddr
, channel
);
610 * @brief Gets the eDMA channel interrupt request status.
612 * @param baseAddr Register base address for eDMA module.
613 * @param channel eDMA channel number.
614 * @return Interrupt request happens in this eDMA channel (true) or not happen in this
617 static inline bool EDMA_HAL_GetIntStatusFlag(uint32_t baseAddr
, uint32_t channel
)
619 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
621 return (((uint32_t)HW_DMA_INT_RD(baseAddr
) >> channel
) & 1U);
625 * @brief Gets the eDMA all channel's interrupt request status.
627 * @param baseAddr Register base address for eDMA module.
628 * @param channel eDMA channel number.
629 * @return Interrupt status flag of all channels.
631 static inline uint32_t EDMA_HAL_GetAllIntStatusFlag(uint32_t baseAddr
)
633 return (uint32_t)HW_DMA_INT_RD(baseAddr
);
637 * @brief Clears the interrupt status for the eDMA channel or all channels.
639 * @param baseAddr Register base address for eDMA module.
640 * @param enable Enable(true) or Disable (false) error interrupt.
641 * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' interrupt
642 * status will be cleared.
644 static inline void EDMA_HAL_ClearIntStatusFlag(
645 uint32_t baseAddr
, edma_channel_indicator_t channel
)
647 HW_DMA_CINT_WR(baseAddr
, channel
);
650 #if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
652 * @brief Enables/Disables an asynchronous request in stop mode.
654 * @param baseAddr Register base address for eDMA module.
655 * @param channel eDMA channel number.
656 * @param enable Enable (true) or Disable (false) async DMA request.
658 void EDMA_HAL_SetAsyncRequestInStopModeCmd(uint32_t baseAddr
, uint32_t channel
, bool enable
);
664 * @name eDMA HAL driver hardware TCD configuration functions.
669 * @brief Clears all registers to 0 for the hardware TCD.
671 * @param baseAddr Register base address for eDMA module.
672 * @param channel eDMA channel number.
674 void EDMA_HAL_HTCDClearReg(uint32_t baseAddr
, uint32_t channel
);
677 * @brief Configures the source address for the hardware TCD.
679 * @param baseAddr Register base address for eDMA module.
680 * @param channel eDMA channel number.
681 * @param address The pointer to the source memory address.
683 static inline void EDMA_HAL_HTCDSetSrcAddr(uint32_t baseAddr
, uint32_t channel
, uint32_t address
)
685 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
686 BW_DMA_TCDn_SADDR_SADDR(baseAddr
, channel
, address
);
690 * @brief Configures the source address signed offset for the hardware TCD.
692 * Sign-extended offset applied to the current source address to form the next-state value as each
693 * source read is complete.
695 * @param baseAddr Register base address for eDMA module.
696 * @param channel eDMA channel number.
697 * @param offset signed-offset for source address.
699 static inline void EDMA_HAL_HTCDSetSrcOffset(uint32_t baseAddr
, uint32_t channel
, int16_t offset
)
701 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
702 BW_DMA_TCDn_SOFF_SOFF(baseAddr
, channel
, offset
);
706 * @brief Configures the transfer attribute for the eDMA channel.
708 * @param baseAddr Register base address for eDMA module.
709 * @param channel eDMA channel number.
710 * @param srcModulo enumeration type for an allowed source modulo. The value defines a specific address range
711 * specified as the value after the SADDR + SOFF calculation is performed on the original register
712 * value. Setting this field provides the ability to implement a circular data. For data queues
713 * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD
714 * field should be set to the appropriate value for the queue, freezing the desired number of upper
715 * address bits. The value programmed into this field specifies the number of the lower address bits
716 * allowed to change. For a circular queue application, the SOFF is typically set to the transfer
717 * size to implement post-increment addressing with SMOD function restricting the addresses to a
718 * 0-modulo-size range.
719 * @param destModulo Enum type for an allowed destination modulo.
720 * @param srcTransferSize Enum type for source transfer size.
721 * @param destTransferSize Enum type for destination transfer size.
723 void EDMA_HAL_HTCDSetAttribute(
724 uint32_t baseAddr
, uint32_t channel
,
725 edma_modulo_t srcModulo
, edma_modulo_t destModulo
,
726 edma_transfer_size_t srcTransferSize
, edma_transfer_size_t destTransferSize
);
729 * @brief Configures the nbytes for the eDMA channel.
731 * Note here that user need firstly configure the minor loop mapping feature and then call this
734 * @param baseAddr Register base address for eDMA module.
735 * @param channel eDMA channel number.
736 * @param nbytes Number of bytes to be transferred in each service request of the channel
738 void EDMA_HAL_HTCDSetNbytes(uint32_t baseAddr
, uint32_t channel
, uint32_t nbytes
);
741 * @brief Gets the nbytes configuration data for the hardware TCD.
743 * This function decides whether the minor loop mapping is enabled or whether the source/dest
744 * minor loop mapping is enabled. Then, the nbytes are returned accordingly.
746 * @param baseAddr Register base address for eDMA module.
747 * @param channel eDMA channel number.
748 * @return nbytes configuration according to minor loop setting.
750 uint32_t EDMA_HAL_HTCDGetNbytes(uint32_t baseAddr
, uint32_t channel
);
753 * @brief Configures the minor loop offset for the hardware TCD.
755 * Configures both the enable bits and the offset value. If neither source nor destination offset is enabled,
756 * offset is not configured. Note here if source or destination offset is required, the eDMA module
757 * EMLM bit will be set in this function. User need to know this side effect.
759 * @param baseAddr Register base address for eDMA module.
760 * @param channel eDMA channel number.
761 * @param config Configuration data structure for the minor loop offset
763 void EDMA_HAL_HTCDSetMinorLoopOffset(
764 uint32_t baseAddr
, uint32_t channel
, edma_minorloop_offset_config_t
*config
);
767 * @brief Configures the last source address adjustment for the hardware TCD.
769 * Adjustment value added to the source address at the completion of the major iteration count. This
770 * value can be applied to restore the source address to the initial value, or adjust the address to
771 * reference the next data structure.
773 * @param baseAddr Register base address for eDMA module.
774 * @param channel eDMA channel number.
775 * @param size adjustment value
777 static inline void EDMA_HAL_HTCDSetSrcLastAdjust(uint32_t baseAddr
, uint32_t channel
, int32_t size
)
779 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
780 BW_DMA_TCDn_SLAST_SLAST(baseAddr
, channel
, size
);
784 * @brief Configures the destination address for the hardware TCD.
786 * @param baseAddr Register base address for eDMA module.
787 * @param channel eDMA channel number.
788 * @param address The pointer to the destination address.
790 static inline void EDMA_HAL_HTCDSetDestAddr(uint32_t baseAddr
, uint32_t channel
, uint32_t address
)
792 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
793 BW_DMA_TCDn_DADDR_DADDR(baseAddr
, channel
, address
);
797 * @brief Configures the destination address signed offset for the hardware TCD.
799 * Sign-extended offset applied to the current source address to form the next-state value as each
800 * destination write is complete.
802 * @param baseAddr Register base address for eDMA module.
803 * @param channel eDMA channel number.
804 * @param offset signed-offset
806 static inline void EDMA_HAL_HTCDSetDestOffset(uint32_t baseAddr
, uint32_t channel
, int16_t offset
)
808 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
809 BW_DMA_TCDn_DOFF_DOFF(baseAddr
, channel
, offset
);
813 * @brief Configures the last source address adjustment.
815 * This function adds an adjustment value added to the source address at the completion of the major
816 * iteration count. This value can be applied to restore the source address to the initial value, or
817 * adjust the address to reference the next data structure.
819 * @param baseAddr Register base address for eDMA module.
820 * @param channel eDMA channel number.
821 * @param adjust adjustment value
823 static inline void EDMA_HAL_HTCDSetDestLastAdjust(
824 uint32_t baseAddr
, uint32_t channel
, uint32_t adjust
)
826 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
827 BW_DMA_TCDn_DLASTSGA_DLASTSGA(baseAddr
, channel
, adjust
);
831 * @brief Configures the memory address for the next transfer TCD for the hardware TCD.
834 * This function enables the scatter/gather feature for the hardware TCD and configures the next
835 * TCD's address. This address points to the beginning of a 0-modulo-32 byte region containing
836 * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
837 * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
838 * a configuration error is reported.
840 * @param baseAddr Register base address for eDMA module.
841 * @param channel eDMA channel number.
842 * @param stcd The pointer to the TCD to be linked to this hardware TCD.
844 void EDMA_HAL_HTCDSetScatterGatherLink(
845 uint32_t baseAddr
, uint32_t channel
, edma_software_tcd_t
*stcd
);
848 * @brief Configures the bandwidth for the hardware TCD.
850 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
851 * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
852 * This field forces the eDMA to stall after the completion of each read/write access to control the
853 * bus request bandwidth seen by the crossbar switch.
855 * @param baseAddr Register base address for eDMA module.
856 * @param channel eDMA channel number.
857 * @param bandwidth enum type for bandwidth control
859 static inline void EDMA_HAL_HTCDSetBandwidth(
860 uint32_t baseAddr
, uint32_t channel
, edma_bandwidth_config_t bandwidth
)
862 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
863 BW_DMA_TCDn_CSR_BWC(baseAddr
, channel
, bandwidth
);
867 * @brief Configures the major channel link the hardware TCD.
869 * If the major link is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
870 * channel service request at the channel defined by these six bits by setting that channel start
873 * @param baseAddr Register base address for eDMA module.
874 * @param channel eDMA channel number.
875 * @param majorChannel channel number for major link
876 * @param enable Enables (true) or Disables (false) channel major link.
878 static inline void EDMA_HAL_HTCDSetChannelMajorLink(
879 uint32_t baseAddr
, uint32_t channel
, uint32_t majorChannel
, bool enable
)
881 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
882 BW_DMA_TCDn_CSR_MAJORLINKCH(baseAddr
, channel
, majorChannel
);
883 BW_DMA_TCDn_CSR_MAJORELINK(baseAddr
, channel
, enable
);
887 * @brief Gets the major link channel for the hardware TCD.
889 * @param baseAddr Register base address for eDMA module.
890 * @param channel eDMA channel number.
891 * @return major link channel number
893 static inline uint32_t EDMA_HAL_HTCDGetMajorLinkChannel(uint32_t baseAddr
, uint32_t channel
)
895 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
896 return BR_DMA_TCDn_CSR_MAJORLINKCH(baseAddr
, channel
);
900 * @brief Enables/Disables the scatter/gather feature for the hardware TCD.
902 * @param baseAddr Register base address for eDMA module.
903 * @param channel eDMA channel number.
904 * @param enable Enables (true) /Disables (false) scatter/gather feature.
906 static inline void EDMA_HAL_HTCDSetScatterGatherCmd(
907 uint32_t baseAddr
, uint32_t channel
, bool enable
)
909 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
910 BW_DMA_TCDn_CSR_ESG(baseAddr
, channel
, enable
);
914 * @brief Checks whether the scatter/gather feature is enabled for the hardware TCD.
916 * @param baseAddr Register base address for eDMA module.
917 * @param channel eDMA channel number.
918 * @return True stand for enabled. False stands for disabled.
920 static inline bool EDMA_HAL_HTCDGetScatterGatherCmd(uint32_t baseAddr
, uint32_t channel
)
922 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
923 return BR_DMA_TCDn_CSR_ESG(baseAddr
, channel
);
928 * @brief Disables/Enables the DMA request after the major loop completes for the hardware TCD.
930 * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
931 * current major iteration count reaches zero.
933 * @param baseAddr Register base address for eDMA module.
934 * @param channel eDMA channel number.
935 * @param disable Disable (true)/Enable (true) DMA request after TCD complete.
937 static inline void EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd(
938 uint32_t baseAddr
, uint32_t channel
, bool disable
)
940 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
941 BW_DMA_TCDn_CSR_DREQ(baseAddr
, channel
, disable
);
945 * @brief Enables/Disables the half complete interrupt for the hardware TCD.
947 * If set, the channel generates an interrupt request by setting the appropriate bit in the
948 * interrupt register when the current major iteration count reaches the halfway point. Specifically,
949 * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
950 * interrupt request is provided to support the double-buffered schemes or other types of data movement
951 * where the processor needs an early indication of the transfer's process.
953 * @param baseAddr Register base address for eDMA module.
954 * @param channel eDMA channel number.
955 * @param enable Enable (true) /Disable (false) half complete interrupt.
957 static inline void EDMA_HAL_HTCDSetHalfCompleteIntCmd(
958 uint32_t baseAddr
, uint32_t channel
, bool enable
)
960 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
961 BW_DMA_TCDn_CSR_INTHALF(baseAddr
, channel
, enable
);
965 * @brief Enables/Disables the interrupt after the major loop completes for the hardware TCD.
967 * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
968 * interrupt register when the current major iteration count reaches zero.
970 * @param baseAddr Register base address for eDMA module.
971 * @param channel eDMA channel number.
972 * @param enable Enable (true) /Disable (false) interrupt after TCD done.
974 static inline void EDMA_HAL_HTCDSetIntCmd(
975 uint32_t baseAddr
, uint32_t channel
, bool enable
)
977 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
978 BW_DMA_TCDn_CSR_INTMAJOR(baseAddr
, channel
, enable
);
982 * @brief Triggers the start bits for the hardware TCD.
984 * The eDMA hardware automatically clears this flag after the channel begins execution.
986 * @param baseAddr Register base address for eDMA module.
987 * @param channel eDMA channel number.
989 static inline void EDMA_HAL_HTCDTriggerChannelStart(uint32_t baseAddr
, uint32_t channel
)
991 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
992 BW_DMA_TCDn_CSR_START(baseAddr
, channel
, true);
996 * @brief Checks whether the channel is running for the hardware TCD.
998 * @param baseAddr Register base address for eDMA module.
999 * @param channel eDMA channel number.
1000 * @return True stands for running. False stands for not.
1002 static inline bool EDMA_HAL_HTCDGetChannelActiveStatus(uint32_t baseAddr
, uint32_t channel
)
1004 assert(channel
< FSL_FEATURE_EDMA_MODULE_CHANNEL
);
1005 return BR_DMA_TCDn_CSR_ACTIVE(baseAddr
, channel
);
1009 * @brief Sets the channel minor link for the hardware TCD.
1011 * @param baseAddr Register base address for eDMA module.
1012 * @param channel eDMA channel number.
1013 * @param linkChannel Channel to be linked on minor loop complete.
1014 * @param enable Enable (true)/Disable (false) channel minor link.
1016 void EDMA_HAL_HTCDSetChannelMinorLink(
1017 uint32_t baseAddr
, uint32_t channel
, uint32_t linkChannel
, bool enable
);
1020 * @brief Sets the major iteration count according to minor loop channel link setting.
1022 * Note here that user need to first set the minor loop channel link and then call this function.
1023 * The execute flow inside this function is dependent on the minor loop channel link setting.
1025 * @param baseAddr Register base address for eDMA module.
1026 * @param channel eDMA channel number.
1027 * @param count major loop count
1029 void EDMA_HAL_HTCDSetMajorCount(uint32_t baseAddr
, uint32_t channel
, uint32_t count
);
1032 * @brief Gets the number of beginning major counts for the hardware TCD.
1034 * @param baseAddr Register base address for eDMA module.
1035 * @param channel eDMA channel number.
1036 * @return Begin major counts.
1038 uint32_t EDMA_HAL_HTCDGetBeginMajorCount(uint32_t baseAddr
, uint32_t channel
);
1041 * @brief Gets the number of current major counts for the hardware TCD.
1043 * @param baseAddr Register base address for eDMA module.
1044 * @param channel eDMA channel number.
1045 * @return Current major counts.
1047 uint32_t EDMA_HAL_HTCDGetCurrentMajorCount(uint32_t baseAddr
, uint32_t channel
);
1050 * @brief Gets the number of bytes already transferred for the hardware TCD.
1052 * @param baseAddr Register base address for eDMA module.
1053 * @param channel eDMA channel number.
1054 * @return data bytes already transferred
1056 uint32_t EDMA_HAL_HTCDGetFinishedBytes(uint32_t baseAddr
, uint32_t channel
);
1059 * @brief Gets the number of bytes haven't transferred for the hardware TCD.
1061 * @param baseAddr Register base address for eDMA module.
1062 * @param channel eDMA channel number.
1063 * @return data bytes already transferred
1065 uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(uint32_t baseAddr
, uint32_t channel
);
1068 * @brief Gets the channel done status.
1070 * @param baseAddr Register base address for eDMA module.
1071 * @param channel eDMA channel number.
1072 * @return If channel done.
1074 static inline bool EDMA_HAL_HTCDGetDoneStatusFlag(uint32_t baseAddr
, uint32_t channel
)
1076 return BR_DMA_TCDn_CSR_DONE(baseAddr
,channel
);
1082 * @name EDMA HAL driver software TCD configuration functions.
1086 * @brief Configures the source address for the software TCD.
1088 * @param stcd The pointer to the software TCD.
1089 * @param channel eDMA channel number.
1090 * @param address The pointer to the source memory address.
1092 static inline void EDMA_HAL_STCDSetSrcAddr(edma_software_tcd_t
*stcd
, uint32_t address
)
1095 stcd
->SADDR
= DMA_SADDR_SADDR(address
);
1099 * @brief Configures the source address signed offset for the software TCD.
1101 * Sign-extended offset applied to the current source address to form the next-state value as each
1102 * source read is complete.
1104 * @param stcd The pointer to the software TCD.
1105 * @param offset signed-offset for source address.
1107 static inline void EDMA_HAL_STCDSetSrcOffset(edma_software_tcd_t
*stcd
, int16_t offset
)
1110 stcd
->SOFF
= DMA_SOFF_SOFF(offset
);
1114 * @brief Configures the transfer attribute for software TCD.
1116 * @param stcd The pointer to the software TCD.
1117 * @param srcModulo enum type for an allowed source modulo. The value defines a specific address range
1118 * specified as the value after the SADDR + SOFF calculation is performed on the original register
1119 * value. Setting this field provides the ability to implement a circular data. For data queues
1120 * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD
1121 * field should be set to the appropriate value for the queue, freezing the desired number of upper
1122 * address bits. The value programmed into this field specifies the number of the lower address bits
1123 * allowed to change. For a circular queue application, the SOFF is typically set to the transfer
1124 * size to implement post-increment addressing with SMOD function restricting the addresses to a
1125 * 0-modulo-size range.
1126 * @param destModulo Enum type for an allowed destination modulo.
1127 * @param srcTransferSize Enum type for source transfer size.
1128 * @param destTransferSize Enum type for destinatio transfer size.
1130 void EDMA_HAL_STCDSetAttribute(
1131 edma_software_tcd_t
*stcd
,
1132 edma_modulo_t srcModulo
, edma_modulo_t destModulo
,
1133 edma_transfer_size_t srcTransferSize
, edma_transfer_size_t destTransferSize
);
1136 * @brief Configures the nbytes for software TCD.
1138 * Note here that user need firstly configure the minor loop mapping feature and then call this
1141 * @param baseAddr Register base address for eDMA module.
1142 * @param stcd The pointer to the software TCD.
1143 * @param nbytes Number of bytes to be transferred in each service request of the channel
1145 void EDMA_HAL_STCDSetNbytes(uint32_t baseAddr
, edma_software_tcd_t
*stcd
, uint32_t nbytes
);
1148 * @brief Configures the minorloop offset for the software TCD.
1150 * Configures both the enable bits and the offset value. If neither source nor dest offset is enabled,
1151 * offset is not configured. Note here if source or destination offset is requred, the eDMA module
1152 * EMLM bit will be set in this function. User need to know this side effect.
1154 * @param baseAddr Register base address for eDMA module.
1155 * @param stcd The pointer to the software TCD.
1156 * @param config Configuration data structure for the minorloop offset
1158 void EDMA_HAL_STCDSetMinorLoopOffset(
1159 uint32_t baseAddr
, edma_software_tcd_t
*stcd
, edma_minorloop_offset_config_t
*config
);
1162 * @brief Configures the last source address adjustment for the software TCD.
1164 * Adjustment value added to the source address at the completion of the major iteration count. This
1165 * value can be applied to restore the source address to the initial value, or adjust the address to
1166 * reference the next data structure.
1168 * @param stcd The pointer to the software TCD.
1169 * @param size adjustment value
1171 static inline void EDMA_HAL_STCDSetSrcLastAdjust(edma_software_tcd_t
*stcd
, int32_t size
)
1174 stcd
->SLAST
= (stcd
->SLAST
& ~DMA_SLAST_SLAST_MASK
) | DMA_SLAST_SLAST(size
);
1178 * @brief Configures the destination address for the software TCD.
1180 * @param stcd The pointer to the software TCD.
1181 * @param address The pointer to the destination addresss.
1183 static inline void EDMA_HAL_STCDSetDestAddr(edma_software_tcd_t
*stcd
, uint32_t address
)
1186 stcd
->DADDR
= DMA_DADDR_DADDR(address
);
1190 * @brief Configures the destination address signed offset for the software TCD.
1192 * Sign-extended offset applied to the current source address to form the next-state value as each
1193 * destination write is complete.
1195 * @param stcd The pointer to the software TCD.
1196 * @param offset signed-offset
1198 static inline void EDMA_HAL_STCDSetDestOffset(edma_software_tcd_t
*stcd
, int16_t offset
)
1201 stcd
->DOFF
= DMA_DOFF_DOFF(offset
);
1205 * @brief Configures the last source address adjustment.
1207 * This function add an adjustment value added to the source address at the completion of the major
1208 * iteration count. This value can be applied to restore the source address to the initial value, or
1209 * adjust the address to reference the next data structure.
1211 * @param stcd The pointer to the software TCD.
1212 * @param adjust adjustment value
1214 static inline void EDMA_HAL_STCDSetDestLastAdjust(
1215 edma_software_tcd_t
*stcd
, uint32_t adjust
)
1218 stcd
->DLAST_SGA
= DMA_DLAST_SGA_DLASTSGA(adjust
);
1222 * @brief Configures the memory address for the next transfer TCD for the software TCD.
1225 * This function enable the scatter/gather feature for the software TCD and configure the next
1226 * TCD's address.This address points to the beginning of a 0-modulo-32 byte region containing
1227 * the next transfer TCD to be loaded into this channel. The channel reload is performed as the
1228 * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise,
1229 * a configuration error is reported.
1231 * @param stcd The pointer to the software TCD.
1232 * @param nextStcd The pointer to the TCD to be linked to this software TCD.
1234 void EDMA_HAL_STCDSetScatterGatherLink(
1235 edma_software_tcd_t
*stcd
, edma_software_tcd_t
*nextStcd
);
1238 * @brief Configures the bandwidth for the software TCD.
1240 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
1241 * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
1242 * This field forces the eDMA to stall after the completion of each read/write access to control the
1243 * bus request bandwidth seen by the crossbar switch.
1245 * @param stcd The pointer to the software TCD.
1246 * @param bandwidth enum type for bandwidth control
1248 static inline void EDMA_HAL_STCDSetBandwidth(
1249 edma_software_tcd_t
*stcd
, edma_bandwidth_config_t bandwidth
)
1252 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_BWC_MASK
) | DMA_CSR_BWC(bandwidth
);
1256 * @brief Configures the major channel link the software TCD.
1258 * If the majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
1259 * channel service request at the channel defined by these six bits by setting that channel start
1262 * @param stcd The pointer to the software TCD.
1263 * @param majorChannel channel number for major link
1264 * @param enable Enables (true) or Disables (false) channel major link.
1266 static inline void EDMA_HAL_STCDSetChannelMajorLink(
1267 edma_software_tcd_t
*stcd
, uint32_t majorChannel
, bool enable
)
1270 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_MAJORLINKCH_MASK
) | DMA_CSR_MAJORLINKCH(majorChannel
);
1271 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_MAJORELINK_MASK
) |
1272 ((uint32_t)enable
<< DMA_CSR_MAJORELINK_SHIFT
);
1277 * @brief Enables/Disables the scatter/gather feature for the software TCD.
1279 * @param stcd The pointer to the software TCD.
1280 * @param enable Enables (true) /Disables (false) scatter/gather feature.
1282 static inline void EDMA_HAL_STCDSetScatterGatherCmd(
1283 edma_software_tcd_t
*stcd
, bool enable
)
1286 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_ESG_MASK
) | ((uint32_t)enable
<< DMA_CSR_ESG_SHIFT
);
1291 * @brief Disables/Enables the DMA request after the major loop completes for the software TCD.
1293 * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
1294 * current major iteration count reaches zero.
1296 * @param stcd The pointer to the software TCD.
1297 * @param disable Disable (true)/Enable (true) dma request after TCD complete.
1299 static inline void EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd(
1300 edma_software_tcd_t
*stcd
, bool disable
)
1303 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_DREQ_MASK
) | ((uint32_t)disable
<< DMA_CSR_DREQ_SHIFT
);
1307 * @brief Enables/Disables the half complete interrupt for the software TCD.
1309 * If set, the channel generates an interrupt request by setting the appropriate bit in the
1310 * interrupt register when the current major iteration count reaches the halfway point. Specifically,
1311 * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
1312 * interrupt request is provided to support the double-buffered schemes or other types of data movement
1313 * where the processor needs an early indication of the transfer's process.
1315 * @param stcd The pointer to the software TCD.
1316 * @param enable Enable (true) /Disable (false) half complete interrupt.
1318 static inline void EDMA_HAL_STCDSetHalfCompleteIntCmd(
1319 edma_software_tcd_t
*stcd
, bool enable
)
1322 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_INTHALF_MASK
) | ((uint32_t)enable
<< DMA_CSR_INTHALF_SHIFT
);
1326 * @brief Enables/Disables the interrupt after the major loop completes for the software TCD.
1328 * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
1329 * interrupt register when the current major iteration count reaches zero.
1331 * @param stcd The pointer to the software TCD.
1332 * @param enable Enable (true) /Disable (false) interrupt after TCD done.
1334 static inline void EDMA_HAL_STCDSetIntCmd(edma_software_tcd_t
*stcd
, bool enable
)
1337 stcd
->CSR
= (stcd
->CSR
& ~DMA_CSR_INTMAJOR_MASK
) | ((uint32_t)enable
<< DMA_CSR_INTMAJOR_SHIFT
);
1341 * @brief Triggers the start bits for the software TCD.
1343 * The eDMA hardware automatically clears this flag after the channel begins execution.
1345 * @param stcd The pointer to the software TCD.
1347 static inline void EDMA_HAL_STCDTriggerChannelStart(edma_software_tcd_t
*stcd
)
1350 stcd
->CSR
|= DMA_CSR_START_MASK
;
1354 * @brief Set Channel minor link for software TCD.
1356 * @param stcd The pointer to the software TCD.
1357 * @param linkChannel Channel to be linked on minor loop complete.
1358 * @param enable Enable (true)/Disable (false) channel minor link.
1360 void EDMA_HAL_STCDSetChannelMinorLink(
1361 edma_software_tcd_t
*stcd
, uint32_t linkChannel
, bool enable
);
1364 * @brief Sets the major iteration count according to minor loop channel link setting.
1366 * Note here that user need to first set the minor loop channel link and then call this function.
1367 * The execute flow inside this function is dependent on the minor loop channel link setting.
1369 * @param stcd The pointer to the software TCD.
1370 * @param count major loop count
1372 void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t
*stcd
, uint32_t count
);
1375 * @brief Copy the software TCD configuration to the hardware TCD.
1377 * @param baseAddr Register base address for eDMA module.
1378 * @param channel eDMA channel number.
1379 * @param stcd The pointer to the software TCD.
1381 void EDMA_HAL_PushSTCDToHTCD(uint32_t baseAddr
, uint32_t channel
, edma_software_tcd_t
*stcd
);
1384 * @brief Set the basic transfer for software TCD.
1386 * This function is used to setup the basic transfer for software TCD. The minor loop setting is not
1387 * involved here cause minor loop's configuration will lay a impact on the global eDMA setting. And
1388 * the source minor loop offset is relevant to the dest minor loop offset. For these reasons, minor
1389 * loop offset configuration is treated as an advanced configuration. User can call the
1390 * EDMA_HAL_STCDSetMinorLoopOffset() to configure the minor loop offset feature.
1392 * @param baseAddr Register base address for eDMA module.
1393 * @param stcd The pointer to the software TCD.
1394 * @param config The pointer to the transfer configuration structure.
1395 * @param enableInt Enables (true) or Disables (false) interrupt on TCD complete.
1396 * @param disableDmaRequest Disables (true) or Enable (false) dma request on TCD complete.
1398 edma_status_t
EDMA_HAL_STCDSetBasicTransfer(
1399 uint32_t baseAddr
, edma_software_tcd_t
*stcd
, edma_transfer_config_t
*config
,
1400 bool enableInt
, bool disableDmaRequest
);
1406 #if defined(__cplusplus)
1412 #endif /* __EDMA_HAL_H__ */
1414 /*******************************************************************************
1416 ******************************************************************************/