tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c

   1 /*
   2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without modification,
   6  * are permitted provided that the following conditions are met:
   7  *
   8  * o Redistributions of source code must retain the above copyright notice, this list
   9  *   of conditions and the following disclaimer.
  10  *
  11  * o Redistributions in binary form must reproduce the above copyright notice, this
  12  *   list of conditions and the following disclaimer in the documentation and/or
  13  *   other materials provided with the distribution.
  14  *
  15  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  16  *   contributors may be used to endorse or promote products derived from this
  17  *   software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 #include "fsl_ftm_hal.h"
  31
  32 /*******************************************************************************
  33  * Definitions
  34  ******************************************************************************/
  35 void FTM_HAL_Init(uint32_t ftmBaseAddr)
  36 {
  37
  38 }
  39
  40 void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel)
  41 {
  42     FTM_HAL_SetDualEdgeCaptureCmd(ftmBaseAddr, channel, false);
  43     FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, config->edgeMode ? 1 : 2);
  44     switch(config->mode)
  45     {
  46         case kFtmEdgeAlignedPWM:
  47             FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
  48             FTM_HAL_SetCpwms(ftmBaseAddr, 0);
  49             FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 2);
  50             break;
  51         case kFtmCenterAlignedPWM:
  52             FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
  53             FTM_HAL_SetCpwms(ftmBaseAddr, 1);
  54             break;
  55         case kFtmCombinedPWM:
  56             FTM_HAL_SetCpwms(ftmBaseAddr, 0);
  57             FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, true);
  58             break;
  59         default:
  60             assert(0);
  61             break;
  62     }
  63 }
  64
  65 void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel)
  66 {
  67
  68     FTM_HAL_SetChnCountVal(ftmBaseAddr, channel, 0);
  69     FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, 0);
  70     FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 0);
  71     FTM_HAL_SetCpwms(ftmBaseAddr, 0);
  72     FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
  73 }
  74
  75 void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance)
  76 {
  77     uint8_t chan = FSL_FEATURE_FTM_CHANNEL_COUNTn(instance);
  78
  79     HW_FTM_SC_WR(ftmBaseAddr, 0);
  80     HW_FTM_CNT_WR(ftmBaseAddr, 0);
  81     HW_FTM_MOD_WR(ftmBaseAddr, 0);
  82
  83     for(int i = 0; i < chan; i++)
  84     {
  85         HW_FTM_CnSC_WR(ftmBaseAddr, i, 0);
  86         HW_FTM_CnV_WR(ftmBaseAddr, i, 0);
  87     }
  88     HW_FTM_CNTIN_WR(ftmBaseAddr, 0);
  89     HW_FTM_STATUS_WR(ftmBaseAddr, 0);
  90     HW_FTM_MODE_WR(ftmBaseAddr, 0x00000004);
  91     HW_FTM_SYNC_WR(ftmBaseAddr, 0);
  92     HW_FTM_OUTINIT_WR(ftmBaseAddr, 0);
  93     HW_FTM_OUTMASK_WR(ftmBaseAddr, 0);
  94     HW_FTM_COMBINE_WR(ftmBaseAddr, 0);
  95     HW_FTM_DEADTIME_WR(ftmBaseAddr, 0);
  96     HW_FTM_EXTTRIG_WR(ftmBaseAddr, 0);
  97     HW_FTM_POL_WR(ftmBaseAddr, 0);
  98     HW_FTM_FMS_WR(ftmBaseAddr, 0);
  99     HW_FTM_FILTER_WR(ftmBaseAddr, 0);
 100     HW_FTM_FLTCTRL_WR(ftmBaseAddr, 0);
 101     /*HW_FTM_QDCTRL_WR(instance, 0);*/
 102     HW_FTM_CONF_WR(ftmBaseAddr, 0);
 103     HW_FTM_FLTPOL_WR(ftmBaseAddr, 0);
 104     HW_FTM_SYNCONF_WR(ftmBaseAddr, 0);
 105     HW_FTM_INVCTRL_WR(ftmBaseAddr, 0);
 106     HW_FTM_SWOCTRL_WR(ftmBaseAddr, 0);
 107     HW_FTM_PWMLOAD_WR(ftmBaseAddr, 0);
 108 }
 109
 110 void FTM_HAL_SetHardwareTriggerCmd(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable)
 111 {
 112     switch(trigger_num)
 113     {
 114         case 0:
 115             BW_FTM_SYNC_TRIG0(ftmBaseAddr, enable ? 1 : 0);
 116             break;
 117         case 1:
 118             BW_FTM_SYNC_TRIG1(ftmBaseAddr, enable ? 1 : 0);
 119             break;
 120         case 2:
 121             BW_FTM_SYNC_TRIG2(ftmBaseAddr, enable ? 1 : 0);
 122             break;
 123         default:
 124             assert(0);
 125             break;
 126     }
 127 }
 128
 129 void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
 130 {
 131     assert(channel < HW_CHAN6);
 132
 133     uint8_t bit = val ? 1 : 0;
 134     uint32_t value = (channel > 1U) ? (uint8_t)(bit << (channel - 2U)) : (uint8_t)(bit << (channel + 4U));
 135
 136     val ? HW_FTM_EXTTRIG_SET(ftmBaseAddr, value) : HW_FTM_EXTTRIG_CLR(ftmBaseAddr, value);
 137 }
 138
 139 void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val)
 140 {
 141     assert(channel < HW_CHAN4);
 142
 143     switch(channel)
 144     {
 145         case HW_CHAN0:
 146             BW_FTM_FILTER_CH0FVAL(ftmBaseAddr, val);
 147             break;
 148         case HW_CHAN1:
 149             BW_FTM_FILTER_CH1FVAL(ftmBaseAddr, val);
 150             break;
 151         case HW_CHAN2:
 152             BW_FTM_FILTER_CH2FVAL(ftmBaseAddr, val);
 153             break;
 154         case HW_CHAN3:
 155             BW_FTM_FILTER_CH3FVAL(ftmBaseAddr, val);
 156             break;
 157         default:
 158             assert(0);
 159             break;
 160     }
 161 }
 162
 163 uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel)
 164 {
 165     if((channel == HW_CHAN0) || (channel == HW_CHAN1))
 166     {
 167         return 0;
 168     }
 169     else if((channel == HW_CHAN2) || (channel == HW_CHAN3))
 170     {
 171         return 1;
 172     }
 173     else if((channel == HW_CHAN4) || (channel == HW_CHAN5))
 174     {
 175         return 2;
 176     }
 177     else
 178     {
 179         return 3;
 180     }
 181 }
 182
 183 /*******************************************************************************
 184  * EOF
 185  ******************************************************************************/
 186