tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_LPUART_FEATURES_H__)
  48 #define __FSL_LPUART_FEATURES_H__
  49
  50 #if defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
  51     defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
  52     defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \
  53     defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
  54     defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F128VLH10) || \
  55     defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
  56     defined(CPU_MKV31F512VLL12)
  57     /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
  58     #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
  59     /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
  60     #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
  61     /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
  62     #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
  63     /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
  64     #define FSL_FEATURE_LPUART_HAS_FIFO (0)
  65     /* @brief Hardware flow control (RTS, CTS) is supported. */
  66     #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
  67     /* @brief Infrared (modulation) is supported. */
  68     #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
  69     /* @brief 2 bits long stop bit is available. */
  70     #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
  71     /* @brief Maximal data width without parity bit. */
  72     #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
  73     /* @brief Baud rate fine adjustment is available. */
  74     #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
  75     /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
  76     #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
  77     /* @brief Baud rate oversampling is available. */
  78     #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
  79     /* @brief Baud rate oversampling is available. */
  80     #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
  81     /* @brief Peripheral type. */
  82     #define FSL_FEATURE_LPUART_IS_SCI (1)
  83     /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
  84     #define FSL_FEATURE_LPUART_FIFO_SIZE (0)
  85     /* @brief Maximal data width without parity bit. */
  86     #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
  87     /* @brief Maximal data width with parity bit. */
  88     #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
  89     /* @brief Supports two match addresses to filter incoming frames. */
  90     #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
  91     /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
  92     #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
  93     /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
  94     #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
  95     /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
  96     #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
  97     /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
  98     #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
  99     /* @brief Has improved smart card (ISO7816 protocol) support. */
 100     #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
 101     /* @brief Has local operation network (CEA709.1-B protocol) support. */
 102     #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
 103     /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
 104     #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
 105 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
 106     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
 107     /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
 108     #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
 109     /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
 110     #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
 111     /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
 112     #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
 113     /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
 114     #define FSL_FEATURE_LPUART_HAS_FIFO (0)
 115     /* @brief Hardware flow control (RTS, CTS) is supported. */
 116     #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
 117     /* @brief Infrared (modulation) is supported. */
 118     #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
 119     /* @brief 2 bits long stop bit is available. */
 120     #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
 121     /* @brief Maximal data width without parity bit. */
 122     #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
 123     /* @brief Baud rate fine adjustment is available. */
 124     #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
 125     /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
 126     #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
 127     /* @brief Baud rate oversampling is available. */
 128     #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
 129     /* @brief Baud rate oversampling is available. */
 130     #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
 131     /* @brief Peripheral type. */
 132     #define FSL_FEATURE_LPUART_IS_SCI (1)
 133     /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
 134     #define FSL_FEATURE_LPUART_FIFO_SIZE (0)
 135     /* @brief Maximal data width without parity bit. */
 136     #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
 137     /* @brief Maximal data width with parity bit. */
 138     #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
 139     /* @brief Supports two match addresses to filter incoming frames. */
 140     #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
 141     /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
 142     #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0)
 143     /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
 144     #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
 145     /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
 146     #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
 147     /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
 148     #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
 149     /* @brief Has improved smart card (ISO7816 protocol) support. */
 150     #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
 151     /* @brief Has local operation network (CEA709.1-B protocol) support. */
 152     #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
 153     /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
 154     #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
 155 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
 156     defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
 157     defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
 158     defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
 159     defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
 160     defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
 161     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
 162     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
 163     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
 164     /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
 165     #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
 166     /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
 167     #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
 168     /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
 169     #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
 170     /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
 171     #define FSL_FEATURE_LPUART_HAS_FIFO (0)
 172     /* @brief Hardware flow control (RTS, CTS) is supported. */
 173     #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
 174     /* @brief Infrared (modulation) is supported. */
 175     #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
 176     /* @brief 2 bits long stop bit is available. */
 177     #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
 178     /* @brief Maximal data width without parity bit. */
 179     #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
 180     /* @brief Baud rate fine adjustment is available. */
 181     #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
 182     /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
 183     #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
 184     /* @brief Baud rate oversampling is available. */
 185     #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
 186     /* @brief Baud rate oversampling is available. */
 187     #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
 188     /* @brief Peripheral type. */
 189     #define FSL_FEATURE_LPUART_IS_SCI (1)
 190     /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
 191     #define FSL_FEATURE_LPUART_FIFO_SIZE (0)
 192     /* @brief Maximal data width without parity bit. */
 193     #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
 194     /* @brief Maximal data width with parity bit. */
 195     #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
 196     /* @brief Supports two match addresses to filter incoming frames. */
 197     #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
 198     /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
 199     #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
 200     /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
 201     #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
 202     /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
 203     #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
 204     /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
 205     #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
 206     /* @brief Has improved smart card (ISO7816 protocol) support. */
 207     #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
 208     /* @brief Has local operation network (CEA709.1-B protocol) support. */
 209     #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
 210     /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
 211     #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
 212 #else
 213     #define MBED_NO_LPUART
 214 #endif
 215
 216 #endif /* __FSL_LPUART_FEATURES_H__ */
 217
 218 /*******************************************************************************
 219  * EOF
 220  ******************************************************************************/