tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h

   1 /*
   2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without modification,
   6  * are permitted provided that the following conditions are met:
   7  *
   8  * o Redistributions of source code must retain the above copyright notice, this list
   9  *   of conditions and the following disclaimer.
  10  *
  11  * o Redistributions in binary form must reproduce the above copyright notice, this
  12  *   list of conditions and the following disclaimer in the documentation and/or
  13  *   other materials provided with the distribution.
  14  *
  15  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  16  *   contributors may be used to endorse or promote products derived from this
  17  *   software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 #ifndef __FSL_PORT_HAL_H__
  31 #define __FSL_PORT_HAL_H__
  32
  33 #include <assert.h>
  34 #include <stdint.h>
  35 #include <stdbool.h>
  36 #include "fsl_port_features.h"
  37 #include "fsl_device_registers.h"
  38
  39 /*!
  40  * @addtogroup port_hal
  41  * @{
  42  */
  43
  44 /*******************************************************************************
  45  * Definitions
  46  ******************************************************************************/
  47 /*! @brief Internal resistor pull feature selection*/
  48 typedef enum _port_pull {
  49     kPortPullDown = 0U,  /*!< internal pull-down resistor is enabled.*/
  50     kPortPullUp   = 1U   /*!< internal pull-up resistor is enabled.*/
  51 } port_pull_t;
  52
  53 /*! @brief Slew rate selection*/
  54 typedef enum _port_slew_rate {
  55     kPortFastSlewRate = 0U,  /*!< fast slew rate is configured.*/
  56     kPortSlowSlewRate = 1U   /*!< slow slew rate is configured.*/
  57 } port_slew_rate_t;
  58
  59 /*! @brief Configures the drive strength.*/
  60 typedef enum _port_drive_strength {
  61     kPortLowDriveStrength  = 0U, /*!< low drive strength is configured.*/
  62     kPortHighDriveStrength = 1U  /*!< high drive strength is configured.*/
  63 } port_drive_strength_t;
  64
  65 /*! @brief Pin mux selection*/
  66 typedef enum _port_mux {
  67     kPortPinDisabled = 0U,   /*!< corresponding pin is disabled as analog.*/
  68     kPortMuxAsGpio   = 1U,   /*!< corresponding pin is configured as GPIO.*/
  69     kPortMuxAlt2     = 2U,   /*!< chip-specific*/
  70     kPortMuxAlt3     = 3U,   /*!< chip-specific*/
  71     kPortMuxAlt4     = 4U,   /*!< chip-specific*/
  72     kPortMuxAlt5     = 5U,   /*!< chip-specific*/
  73     kPortMuxAlt6     = 6U,   /*!< chip-specific*/
  74     kPortMuxAlt7     = 7U    /*!< chip-specific*/
  75 } port_mux_t;
  76
  77 /*! @brief Digital filter clock source selection*/
  78 #if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
  79 typedef enum _port_digital_filter_clock_source {
  80     kPortBusClock = 0U,  /*!< Digital filters are clocked by the bus clock.*/
  81     kPortLPOClock = 1U   /*!< Digital filters are clocked by the 1 kHz LPO clock.*/
  82 } port_digital_filter_clock_source_t;
  83 #endif
  84
  85 /*! @brief Configures the interrupt generation condition.*/
  86 typedef enum _port_interrupt_config {
  87     kPortIntDisabled    = 0x0U,  /*!< Interrupt/DMA request is disabled.*/
  88     kPortDmaRisingEdge  = 0x1U,  /*!< DMA request on rising edge.*/
  89     kPortDmaFallingEdge = 0x2U,  /*!< DMA request on falling edge.*/
  90     kPortDmaEitherEdge  = 0x3U,  /*!< DMA request on either edge.*/
  91     kPortIntLogicZero   = 0x8U,  /*!< Interrupt when logic zero. */
  92     kPortIntRisingEdge  = 0x9U,  /*!< Interrupt on rising edge. */
  93     kPortIntFallingEdge = 0xAU,  /*!< Interrupt on falling edge. */
  94     kPortIntEitherEdge  = 0xBU,  /*!< Interrupt on either edge. */
  95     kPortIntLogicOne    = 0xCU   /*!< Interrupt when logic one. */
  96 } port_interrupt_config_t;
  97
  98 /*******************************************************************************
  99  * API
 100  ******************************************************************************/
 101
 102 #if defined(__cplusplus)
 103 extern "C" {
 104 #endif
 105
 106 /*!
 107  * @name Configuration
 108  * @{
 109  */
 110
 111 /*!
 112  * @brief Selects the internal resistor as pull-down or pull-up.
 113  *
 114  * Pull configuration is valid in all digital pin muxing modes.
 115  *
 116  * @param baseAddr  port base address.
 117  * @param pin       port pin number
 118  * @param pullSelect  internal resistor pull feature selection
 119  *        - kPortPullDown: internal pull-down resistor is enabled.
 120  *        - kPortPullUp  : internal pull-up resistor is enabled.
 121  */
 122 static inline void PORT_HAL_SetPullMode(uint32_t baseAddr,
 123                                         uint32_t pin,
 124                                         port_pull_t pullSelect)
 125 {
 126     assert(pin < 32U);
 127     BW_PORT_PCRn_PS(baseAddr, pin, pullSelect);
 128 }
 129
 130 /*!
 131  * @brief Enables or disables the internal pull resistor.
 132  *
 133  * @param baseAddr  port base address
 134  * @param pin       port pin number
 135  * @param isPullEnabled  internal pull resistor enable or disable
 136  *        - true : internal pull resistor is enabled.
 137  *        - false: internal pull resistor is disabled.
 138  */
 139 static inline void PORT_HAL_SetPullCmd(uint32_t baseAddr, uint32_t pin, bool isPullEnabled)
 140 {
 141     assert(pin < 32U);
 142     BW_PORT_PCRn_PE(baseAddr, pin, isPullEnabled);
 143 }
 144
 145 /*!
 146  * @brief Configures the fast/slow slew rate if the pin is used as a digital output.
 147  *
 148  * @param baseAddr  port base address
 149  * @param pin  port pin number
 150  * @param rateSelect  slew rate selection
 151  *        - kPortFastSlewRate: fast slew rate is configured.
 152  *        - kPortSlowSlewRate: slow slew rate is configured.
 153  */
 154 static inline void PORT_HAL_SetSlewRateMode(uint32_t baseAddr,
 155                                                 uint32_t pin,
 156                                                 port_slew_rate_t rateSelect)
 157 {
 158     assert(pin < 32U);
 159     BW_PORT_PCRn_SRE(baseAddr, pin, rateSelect);
 160 }
 161
 162 /*!
 163  * @brief Configures the passive filter if the pin is used as a digital input.
 164  *
 165  * If enabled, a low pass filter (10 MHz to 30 MHz bandwidth)  is enabled
 166  * on the digital input path. Disable the Passive Input Filter when supporting
 167  * high speed interfaces (> 2 MHz) on the pin.
 168  *
 169  * @param baseAddr  port base address
 170  * @param pin  port pin number
 171  * @param isPassiveFilterEnabled  passive filter configuration
 172  *        - false: passive filter is disabled.
 173  *        - true : passive filter is enabled.
 174  */
 175 static inline void PORT_HAL_SetPassiveFilterCmd(uint32_t baseAddr,
 176                                                      uint32_t pin,
 177                                                      bool isPassiveFilterEnabled)
 178 {
 179     assert(pin < 32U);
 180     BW_PORT_PCRn_PFE(baseAddr, pin, isPassiveFilterEnabled);
 181 }
 182
 183 #if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
 184 /*!
 185  * @brief Enables or disables the open drain.
 186  *
 187  * @param baseAddr  port base address
 188  * @param pin  port pin number
 189  * @param isOpenDrainEnabled  enable open drain or not
 190  *        - false: Open Drain output is disabled on the corresponding pin.
 191  *        - true : Open Drain output is disabled on the corresponding pin.
 192  */
 193 static inline void PORT_HAL_SetOpenDrainCmd(uint32_t baseAddr,
 194                                                  uint32_t pin,
 195                                                  bool isOpenDrainEnabled)
 196 {
 197     assert(pin < 32U);
 198     BW_PORT_PCRn_ODE(baseAddr, pin, isOpenDrainEnabled);
 199 }
 200 #endif /*FSL_FEATURE_PORT_HAS_OPEN_DRAIN*/
 201
 202 /*!
 203  * @brief Configures the drive strength if the pin is used as a digital output.
 204  *
 205  * @param baseAddr  port base address
 206  * @param pin  port pin number
 207  * @param driveSelect  drive strength selection
 208  *        - kLowDriveStrength : low drive strength is configured.
 209  *        - kHighDriveStrength: high drive strength is configured.
 210  */
 211 static inline void PORT_HAL_SetDriveStrengthMode(uint32_t baseAddr,
 212                                                      uint32_t pin,
 213                                                      port_drive_strength_t driveSelect)
 214 {
 215     assert(pin < 32U);
 216     BW_PORT_PCRn_DSE(baseAddr, pin, driveSelect);
 217 }
 218
 219 /*!
 220  * @brief Configures the pin muxing.
 221  *
 222  * @param baseAddr  port base address
 223  * @param pin  port pin number
 224  * @param mux  pin muxing slot selection
 225  *        - kPinDisabled: Pin disabled.
 226  *        - kMuxAsGpio  : Set as GPIO.
 227  *        - others      : chip-specific.
 228  */
 229 static inline void PORT_HAL_SetMuxMode(uint32_t baseAddr, uint32_t pin, port_mux_t mux)
 230 {
 231     assert(pin < 32U);
 232     BW_PORT_PCRn_MUX(baseAddr, pin, mux);
 233 }
 234
 235 #if FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
 236 /*!
 237  * @brief Locks or unlocks the pin control register bits[15:0].
 238  *
 239  * @param baseAddr  port base address
 240  * @param pin  port pin number
 241  * @param isPinLockEnabled  lock pin control register or not
 242  *        - false: pin control register bit[15:0] are not locked.
 243  *        - true : pin control register bit[15:0] are locked, cannot be updated till system reset.
 244  */
 245 static inline void PORT_HAL_SetPinCtrlLockCmd(uint32_t baseAddr,
 246                                                        uint32_t pin,
 247                                                        bool isPinLockEnabled)
 248 {
 249     assert(pin < 32U);
 250     BW_PORT_PCRn_LK(baseAddr, pin, isPinLockEnabled);
 251 }
 252 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK*/
 253
 254 #if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
 255 /*!
 256  * @brief Enables or disables the digital filter in one single port.
 257  *        Each bit of the 32-bit register represents one pin.
 258  *
 259  * @param baseAddr  port base address
 260  * @param pin  port pin number
 261  * @param isDigitalFilterEnabled  digital filter enable/disable
 262  *        - false: digital filter is disabled on the corresponding pin.
 263  *        - true : digital filter is enabled on the corresponding pin.
 264  */
 265 static inline void PORT_HAL_SetDigitalFilterCmd(uint32_t baseAddr,
 266                                                      uint32_t pin,
 267                                                      bool isDigitalFilterEnabled)
 268 {
 269     assert(pin < 32U);
 270     HW_PORT_DFER_SET(baseAddr, (uint32_t)isDigitalFilterEnabled << pin);
 271 }
 272
 273 /*!
 274  * @brief Configures the clock source for the digital input filters. Changing the filter clock source should
 275  *        only be done after disabling all enabled filters. Every pin in one port uses the same
 276  *        clock source.
 277  *
 278  * @param baseAddr  port base address
 279  * @param clockSource  chose which clock source to use for current port
 280  *        - kBusClock: digital filters are clocked by the bus clock.
 281  *        - kLPOClock: digital filters are clocked by the 1 kHz LPO clock.
 282  */
 283 static inline void PORT_HAL_SetDigitalFilterClock(uint32_t baseAddr,
 284                                                     port_digital_filter_clock_source_t clockSource)
 285 {
 286     HW_PORT_DFCR_WR(baseAddr, clockSource);
 287 }
 288
 289 /*!
 290  * @brief Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs
 291  *        for enabled digital filters. Glitches that are longer than this register setting
 292  *        (in clock cycles)  pass through the digital filter, while glitches that are equal
 293  *        to or less than this register setting (in clock cycles)  are filtered. Changing the
 294  *        filter length should only be done after disabling all enabled filters.
 295  *
 296  * @param baseAddr  port base address
 297  * @param width  configure digital filter width (should be less than 5 bits).
 298  */
 299 static inline void PORT_HAL_SetDigitalFilterWidth(uint32_t baseAddr, uint8_t width)
 300 {
 301     HW_PORT_DFWR_WR(baseAddr, width);
 302 }
 303 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER*/
 304
 305 /*!
 306  * @brief Configures the low half of the pin control register for the same settings.
 307  *        This function operates pin 0 -15 of one specific port.
 308  *
 309  * @param baseAddr  port base address
 310  * @param lowPinSelect  update corresponding pin control register or not. For a specific bit:
 311  *        - 0: corresponding low half of pin control register won't be updated according to configuration.
 312  *        - 1: corresponding low half of pin control register will be updated according to configuration.
 313  * @param config  value  is written to a low half port control register bits[15:0].
 314  */
 315 void PORT_HAL_SetLowGlobalPinCtrl(uint32_t baseAddr, uint16_t lowPinSelect, uint16_t config);
 316
 317 /*!
 318  * @brief Configures the high half of pin control register for the same settings.
 319  *        This function operates pin 16 -31 of one specific port.
 320  *
 321  * @param baseAddr  port base address
 322  * @param highPinSelect  update corresponding pin control register or not. For a specific bit:
 323  *        - 0: corresponding high half of pin control register won't be updated according to configuration.
 324  *        - 1: corresponding high half of pin control register will be updated according to configuration.
 325  * @param config  value is  written to a high half port control register bits[15:0].
 326  */
 327 void PORT_HAL_SetHighGlobalPinCtrl(uint32_t baseAddr, uint16_t highPinSelect, uint16_t config);
 328
 329 /*@}*/
 330
 331 /*!
 332  * @name Interrupt
 333  * @{
 334  */
 335
 336 /*!
 337  * @brief Configures the port pin interrupt/DMA request.
 338  *
 339  * @param baseAddr  port base address.
 340  * @param pin  port pin number
 341  * @param intConfig  interrupt configuration
 342  *        - kIntDisabled   : Interrupt/DMA request disabled.
 343  *        - kDmaRisingEdge : DMA request on rising edge.
 344  *        - kDmaFallingEdge: DMA request on falling edge.
 345  *        - kDmaEitherEdge : DMA request on either edge.
 346  *        - KIntLogicZero  : Interrupt when logic zero.
 347  *        - KIntRisingEdge : Interrupt on rising edge.
 348  *        - KIntFallingEdge: Interrupt on falling edge.
 349  *        - KIntEitherEdge : Interrupt on either edge.
 350  *        - KIntLogicOne   : Interrupt when logic one.
 351  */
 352 static inline void PORT_HAL_SetPinIntMode(uint32_t baseAddr,
 353                                           uint32_t pin,
 354                                           port_interrupt_config_t intConfig)
 355 {
 356     assert(pin < 32U);
 357     BW_PORT_PCRn_IRQC(baseAddr, pin, intConfig);
 358 }
 359
 360 /*!
 361  * @brief Gets the current port pin interrupt/DMA request configuration.
 362  *
 363  * @param baseAddr  port base address
 364  * @param pin  port pin number
 365  * @return  interrupt configuration
 366  *        - kIntDisabled   : Interrupt/DMA request disabled.
 367  *        - kDmaRisingEdge : DMA request on rising edge.
 368  *        - kDmaFallingEdge: DMA request on falling edge.
 369  *        - kDmaEitherEdge : DMA request on either edge.
 370  *        - KIntLogicZero  : Interrupt when logic zero.
 371  *        - KIntRisingEdge : Interrupt on rising edge.
 372  *        - KIntFallingEdge: Interrupt on falling edge.
 373  *        - KIntEitherEdge : Interrupt on either edge.
 374  *        - KIntLogicOne   : Interrupt when logic one.
 375  */
 376 static inline port_interrupt_config_t PORT_HAL_GetPinIntMode(uint32_t baseAddr, uint32_t pin)
 377 {
 378     assert(pin < 32U);
 379     return (port_interrupt_config_t)BR_PORT_PCRn_IRQC(baseAddr, pin);
 380 }
 381
 382 /*!
 383  * @brief Reads the individual pin-interrupt status flag.
 384  *
 385  * If a pin is configured to generate the DMA request,  the corresponding flag
 386  * is cleared automatically at the completion of the requested DMA transfer.
 387  * Otherwise, the flag remains set until a logic one is written to that flag.
 388  * If configured for a level sensitive interrupt that remains asserted, the flag
 389  * is set again immediately.
 390  *
 391  * @param baseAddr  port base address
 392  * @param pin  port pin number
 393  * @return current pin interrupt status flag
 394  *         - 0: interrupt is not detected.
 395  *         - 1: interrupt is detected.
 396  */
 397 static inline bool PORT_HAL_IsPinIntPending(uint32_t baseAddr, uint32_t pin)
 398 {
 399     assert(pin < 32U);
 400     return BR_PORT_PCRn_ISF(baseAddr, pin);
 401 }
 402
 403 /*!
 404  * @brief Clears the individual pin-interrupt status flag.
 405  *
 406  * @param baseAddr  port base address
 407  * @param pin  port pin number
 408  */
 409 static inline void PORT_HAL_ClearPinIntFlag(uint32_t baseAddr, uint32_t pin)
 410 {
 411     assert(pin < 32U);
 412     BW_PORT_PCRn_ISF(baseAddr, pin, 1U);
 413 }
 414
 415 /*!
 416  * @brief Reads the entire port interrupt status flag.
 417  *
 418  * @param baseAddr  port base address
 419  * @return all 32 pin interrupt status flags. For specific bit:
 420  *         - 0: interrupt is not detected.
 421  *         - 1: interrupt is detected.
 422  */
 423 static inline uint32_t PORT_HAL_GetPortIntFlag(uint32_t baseAddr)
 424 {
 425     return HW_PORT_ISFR_RD(baseAddr);
 426 }
 427
 428 /*!
 429  * @brief Clears the entire port interrupt status flag.
 430  *
 431  * @param baseAddr  port base address
 432  */
 433 static inline void PORT_HAL_ClearPortIntFlag(uint32_t baseAddr)
 434 {
 435     HW_PORT_ISFR_WR(baseAddr, ~0U);
 436 }
 437
 438 /*@}*/
 439
 440 #if defined(__cplusplus)
 441 }
 442 #endif
 443
 444 /*! @}*/
 445
 446 #endif /* __FSL_PORT_HAL_H__*/
 447 /*******************************************************************************
 448  * EOF
 449  ******************************************************************************/
 450