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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / hal / TARGET_Freescale / TARGET_KPSDK_MCUS / TARGET_KPSDK_CODE / hal / sim / fsl_sim_hal.h
1 /*
2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #if !defined(__FSL_SIM_HAL_H__)
32 #define __FSL_SIM_HAL_H__
33
34 #include <stdint.h>
35 #include <stdbool.h>
36 #include <assert.h>
37 #include "fsl_device_registers.h"
38 #include "fsl_sim_features.h"
39
40 /*! @addtogroup sim_hal*/
41 /*! @{*/
42
43 /*! @file*/
44
45 /*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48 typedef enum _clock_names {
49
50 /* default clocks*/
51 kCoreClock, /**/
52 kSystemClock, /**/
53 kPlatformClock, /**/
54 kBusClock, /**/
55 kFlexBusClock, /**/
56 kFlashClock, /**/
57
58 /* other internal clocks used by peripherals*/
59 /* osc clock*/
60 kOsc32kClock,
61 kOsc0ErClock,
62 kOsc1ErClock,
63
64 /* irc 48Mhz clock */
65 kIrc48mClock,
66
67 /* rtc clock*/
68 kRtc32kClock,
69 kRtc1hzClock,
70
71 /* lpo clcok*/
72 kLpoClock,
73
74 /* mcg clocks*/
75 kMcgFfClock,
76 kMcgFllClock,
77 kMcgPll0Clock,
78 kMcgPll1Clock,
79 kMcgOutClock,
80 kMcgIrClock,
81
82 /* constant clocks (provided in other header files?)*/
83 kSDHC0_CLKIN,
84 kENET_1588_CLKIN,
85 kEXTAL_Clock,
86 kEXTAL1_Clock,
87 kUSB_CLKIN,
88
89 /* reserved value*/
90 kReserved,
91
92 kClockNameCount
93 } clock_names_t;
94
95 /*! @brief Clock source and sel names */
96 typedef enum _clock_source_names {
97 kClockNfcSrc, /* NFCSRC*/
98 kClockEsdhcSrc, /* ESDHCSRC K70*/
99 kClockSdhcSrc, /* SDHCSRC K64*/
100 kClockLcdcSrc, /* LCDCSRC*/
101 kClockTimeSrc, /* TIMESRC*/
102 kClockRmiiSrc, /* RMIISRC*/
103 kClockUsbfSrc, /* USBFSRC K70*/
104 kClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/
105 kClockUsbhSrc, /* USBHSRC*/
106 kClockUart0Src, /* UART0SRC*/
107 kClockLpuartSrc, /* LPUARTSRC K22, KV31 */
108 kClockTpmSrc, /* TPMSRC*/
109 kClockOsc32kSel, /* OSC32KSEL*/
110 kClockUsbfSel, /* USBF_CLKSEL*/
111 kClockPllfllSel, /* PLLFLLSEL*/
112 kClockNfcSel, /* NFC_CLKSEL*/
113 kClockLcdcSel, /* LCDC_CLKSEL*/
114 kClockTraceSel, /* TRACE_CLKSEL*/
115 kClockClkoutSel, /* CLKOUTSEL*/
116 kClockRtcClkoutSel, /* RTCCLKOUTSEL */
117 kClockSourceMax
118 } clock_source_names_t;
119
120 /*! @brief Clock Divider names*/
121 typedef enum _clock_divider_names {
122 kClockDividerOutdiv1, /* OUTDIV1*/
123 kClockDividerOutdiv2, /* OUTDIV2*/
124 kClockDividerOutdiv3, /* OUTDIV3*/
125 kClockDividerOutdiv4, /* OUTDIV4*/
126 kClockDividerUsbFrac, /* (USBFRAC + 1) / (USBDIV + 1)*/
127 kClockDividerUsbDiv,
128 kClockDividerUsbfsFrac, /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/
129 kClockDividerUsbfsDiv,
130 kClockDividerUsbhsFrac, /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/
131 kClockDividerUsbhsDiv,
132 kClockDividerLcdcFrac, /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/
133 kClockDividerLcdcDiv,
134 kClockDividerNfcFrac, /* (NFCFRAC + 1) / (NFCDIV + 1)*/
135 kClockDividerNfcDiv,
136 kClockDividerSpecial1, /* special divider 1*/
137 kClockDividerMax
138 } clock_divider_names_t;
139
140 /*! @brief SIM USB voltage regulator in standby mode setting during stop modes */
141 typedef enum _sim_usbsstby_stop
142 {
143 kSimUsbsstbyNoRegulator, /* regulator not in standby during Stop modes */
144 kSimUsbsstbyWithRegulator /* regulator in standby during Stop modes */
145 } sim_usbsstby_stop_t;
146
147 /*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */
148 typedef enum _sim_usbvstby_stop
149 {
150 kSimUsbvstbyNoRegulator, /* regulator not in standby during VLPR and VLPW modes */
151 kSimUsbvstbyWithRegulator /* regulator in standby during VLPR and VLPW modes */
152 } sim_usbvstby_stop_t;
153
154 /*! @brief SIM CMT/UART pad drive strength */
155 typedef enum _sim_cmtuartpad_strengh
156 {
157 kSimCmtuartSinglePad, /* Single-pad drive strength for CMT IRO or UART0_TXD */
158 kSimCmtuartDualPad /* Dual-pad drive strength for CMT IRO or UART0_TXD */
159 } sim_cmtuartpad_strengh_t;
160
161 /*! @brief SIM PTD7 pad drive strength */
162 typedef enum _sim_ptd7pad_strengh
163 {
164 kSimPtd7padSinglePad, /* Single-pad drive strength for PTD7 */
165 kSimPtd7padDualPad /* Dual-pad drive strength for PTD7 */
166 } sim_ptd7pad_strengh_t;
167
168 /*! @brief SIM FlexBus security level */
169 typedef enum _sim_flexbus_security_level
170 {
171 kSimFbslLevel0, /* All off-chip accesses (op code and data) via the FlexBus */
172 /* and DDR controller are disallowed */
173 kSimFbslLevel1, /* Undefined */
174 kSimFbslLevel2, /* Off-chip op code accesses are disallowed. Data accesses */
175 /* are allowed */
176 kSimFbslLevel3 /* Off-chip op code accesses and data accesses are allowed */
177 } sim_flexbus_security_level_t;
178
179 /*! @brief SIM ADCx pre-trigger select */
180 typedef enum _sim_pretrgsel
181 {
182 kSimAdcPretrgselA, /* Pre-trigger A selected for ADCx */
183 kSimAdcPretrgselB /* Pre-trigger B selected for ADCx */
184 } sim_pretrgsel_t;
185
186 /*! @brief SIM ADCx trigger select */
187 typedef enum _sim_trgsel
188 {
189 kSimAdcTrgselExt, /* External trigger */
190 kSimAdcTrgSelHighSpeedComp0, /* High speed comparator 0 asynchronous interrupt */
191 kSimAdcTrgSelHighSpeedComp1, /* High speed comparator 1 asynchronous interrupt */
192 kSimAdcTrgSelHighSpeedComp2, /* High speed comparator 2 asynchronous interrupt */
193 kSimAdcTrgSelPit0, /* PIT trigger 0 */
194 kSimAdcTrgSelPit1, /* PIT trigger 1 */
195 kSimAdcTrgSelPit2, /* PIT trigger 2 */
196 kSimAdcTrgSelPit3, /* PIT trigger 3 */
197 kSimAdcTrgSelFtm0, /* FTM0 trigger */
198 kSimAdcTrgSelFtm1, /* FTM1 trigger */
199 kSimAdcTrgSelFtm2, /* FTM2 trigger */
200 kSimAdcTrgSelFtm3, /* FTM3 trigger */
201 kSimAdcTrgSelRtcAlarm, /* RTC alarm */
202 kSimAdcTrgSelRtcSec, /* RTC seconds */
203 kSimAdcTrgSelLptimer, /* Low-power timer trigger */
204 kSimAdcTrgSelHigSpeedComp3 /* High speed comparator 3 asynchronous interrupt */
205 } sim_trgsel_t;
206
207 /*! @brief SIM receive data source select */
208 typedef enum _sim_uart_rxsrc
209 {
210 kSimUartRxsrcPin, /* UARTx_RX Pin */
211 kSimUartRxsrcCmp0, /* CMP0 */
212 kSimUartRxsrcCmp1, /* CMP1 */
213 kSimUartRxsrcReserved /* Reserved */
214 } sim_uart_rxsrc_t;
215
216 /*! @brief SIM transmit data source select */
217 typedef enum _sim_uart_txsrc
218 {
219 kSimUartTxsrcPin, /* UARTx_TX Pin */
220 kSimUartTxsrcCmp0, /* UARTx_TX pin modulated with FTM1 channel 0 output */
221 kSimUartTxsrcCmp1, /* UARTx_TX pin modulated with FTM2 channel 0 output */
222 kSimUartTxsrcReserved /* Reserved */
223 } sim_uart_txsrc_t;
224
225 /*! @brief SIM FlexTimer x trigger y select */
226 typedef enum _sim_ftm_trg_src
227 {
228 kSimFtmTrgSrc0, /* FlexTimer x trigger y select 0 */
229 kSimFtmTrgSrc1 /* FlexTimer x trigger y select 1 */
230 } sim_ftm_trg_src_t;
231
232 /*! @brief SIM FlexTimer external clock select */
233 typedef enum _sim_ftm_clk_sel
234 {
235 kSimFtmClkSel0, /* FTM CLKIN0 pin. */
236 kSimFtmClkSel1 /* FTM CLKIN1 pin. */
237 } sim_ftm_clk_sel_t;
238
239 /*! @brief SIM FlexTimer x channel y input capture source select */
240 typedef enum _sim_ftm_ch_src
241 {
242 kSimFtmChSrc0, /* See RM for details of each selection for each channel */
243 kSimFtmChSrc1, /* See RM for details of each selection for each channel */
244 kSimFtmChSrc2, /* See RM for details of each selection for each channel */
245 kSimFtmChSrc3 /* See RM for details of each selection for each channel */
246 } sim_ftm_ch_src_t;
247
248 /*! @brief SIM FlexTimer x Fault y select */
249 typedef enum _sim_ftm_flt_sel
250 {
251 kSimFtmFltSel0, /* FlexTimer x fault y select 0 */
252 kSimFtmFltSel1 /* FlexTimer x fault y select 1 */
253 } sim_ftm_flt_sel_t;
254
255 /*! @brief SIM Timer/PWM external clock select */
256 typedef enum _sim_tpm_clk_sel
257 {
258 kSimTpmClkSel0, /* Timer/PWM TPM_CLKIN0 pin. */
259 kSimTpmClkSel1 /* Timer/PWM TPM_CLKIN1 pin. */
260 } sim_tpm_clk_sel_t;
261
262 /*! @brief SIM Timer/PWM x channel y input capture source select */
263 typedef enum _sim_tpm_ch_src
264 {
265 kSimTpmChSrc0, /* TPMx_CH0 signal */
266 kSimTpmChSrc1 /* CMP0 output */
267 } sim_tpm_ch_src_t;
268
269 /*! @brief SIM HAL API return status*/
270 typedef enum _sim_hal_status {
271 kSimHalSuccess,
272 kSimHalFail,
273 kSimHalNoSuchModule,
274 kSimHalNoSuchClockSrc,
275 kSimHalNoSuchDivider
276 } sim_hal_status_t;
277
278 /*! @brief Clock name configuration table structure*/
279 typedef struct ClockNameConfig {
280 bool useOtherRefClock; /*!< if it uses the other ref clock*/
281 clock_names_t otherRefClockName; /*!< other ref clock name*/
282 clock_divider_names_t dividerName; /*!< clock divider name*/
283 } clock_name_config_t;
284
285 /*! @brief clock name configuration table for specified CPU defined in fsl_clock_module_names_Kxxx.h*/
286 extern const clock_name_config_t kClockNameConfigTable[];
287
288
289 /*******************************************************************************
290 * API
291 ******************************************************************************/
292
293 #if defined(__cplusplus)
294 extern "C" {
295 #endif /* __cplusplus*/
296
297 /*! @name clock-related feature APIs*/
298 /*@{*/
299
300 /*!
301 * @brief Sets the clock source setting.
302 *
303 * This function sets the settings for a specified clock source. Each clock
304 * source has its own clock selection settings. See the chip reference manual for
305 * clock source detailed settings and the clock_source_names_t
306 * for clock sources.
307 *
308 * @param baseAddr Base address for current SIM instance.
309 * @param clockSource Clock source name defined in sim_clock_source_names_t
310 * @param setting Setting value
311 * @return status If the clock source doesn't exist, it returns an error.
312 */
313 sim_hal_status_t CLOCK_HAL_SetSource(uint32_t baseAddr, clock_source_names_t clockSource, uint8_t setting);
314
315 /*!
316 * @brief Gets the clock source setting.
317 *
318 * This function gets the settings for a specified clock source. Each clock
319 * source has its own clock selection settings. See the reference manual for
320 * clock source detailed settings and the clock_source_names_t
321 * for clock sources.
322 *
323 * @param baseAddr Base address for current SIM instance.
324 * @param clockSource Clock source name
325 * @param setting Current setting pointer for the clock source
326 * @return status If the clock source doesn't exist, it returns an error.
327 */
328 sim_hal_status_t CLOCK_HAL_GetSource(uint32_t baseAddr, clock_source_names_t clockSource,
329 uint8_t *setting);
330
331 /*!
332 * @brief Sets the clock divider setting.
333 *
334 * This function sets the setting for a specified clock divider. See the
335 * reference manual for a supported clock divider and value range and the
336 * clock_divider_names_t for dividers.
337 *
338 * @param baseAddr Base address for current SIM instance.
339 * @param clockDivider Clock divider name
340 * @param setting Divider setting
341 * @return status If the clock divider doesn't exist, it returns an error.
342 */
343 sim_hal_status_t CLOCK_HAL_SetDivider(uint32_t baseAddr, clock_divider_names_t clockDivider,
344 uint32_t setting);
345
346 /*!
347 * @brief Sets the clock out dividers setting.
348 *
349 * This function sets the setting for all clock out dividers at the same time.
350 * See the reference manual for a supported clock divider and value range and the
351 * clock_divider_names_t for clock out dividers.
352 *
353 * @param baseAddr Base address for current SIM instance.
354 * @param outdiv1 Outdivider1 setting
355 * @param outdiv2 Outdivider2 setting
356 * @param outdiv3 Outdivider3 setting
357 * @param outdiv4 Outdivider4 setting
358 */
359 void CLOCK_HAL_SetOutDividers(uint32_t baseAddr, uint32_t outdiv1, uint32_t outdiv2,
360 uint32_t outdiv3, uint32_t outdiv4);
361
362 /*!
363 * @brief Gets the clock divider setting.
364 *
365 * This function gets the setting for a specified clock divider. See the
366 * reference manual for a supported clock divider and value range and the
367 * clock_divider_names_t for dividers.
368 *
369 * @param baseAddr Base address for current SIM instance.
370 * @param clockDivider Clock divider name
371 * @param setting Divider value pointer
372 * @return status If the clock divider doesn't exist, it returns an error.
373 */
374 sim_hal_status_t CLOCK_HAL_GetDivider(uint32_t baseAddr, clock_divider_names_t clockDivider,
375 uint32_t *setting);
376
377 /*@}*/
378
379 /*! @name individual field access APIs*/
380 /*@{*/
381
382 #if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE
383 /*!
384 * @brief Gets RAM size.
385 *
386 * This function gets the RAM size. The field specifies the amount of system RAM
387 * available on the device.
388 *
389 * @param baseAddr Base address for current SIM instance.
390 * @return size RAM size on the device
391 */
392 static inline uint32_t SIM_HAL_GetRamSize(uint32_t baseAddr)
393 {
394 return BR_SIM_SOPT1_RAMSIZE(baseAddr);
395 }
396 #endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */
397
398 #if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR
399 /*!
400 * @brief Sets the USB voltage regulator enabled setting.
401 *
402 * This function controls whether the USB voltage regulator is enabled. This bit
403 * can only be written when the SOPT1CFG[URWE] bit is set.
404 *
405 * @param baseAddr Base address for current SIM instance.
406 * @param enable USB voltage regulator enable setting
407 * - true: USB voltage regulator is enabled.
408 * - false: USB voltage regulator is disabled.
409 */
410 static inline void SIM_HAL_SetUsbVoltRegulatorCmd(uint32_t baseAddr, bool enable)
411 {
412 BW_SIM_SOPT1_USBREGEN(baseAddr, enable ? 1 : 0);
413 }
414
415 /*!
416 * @brief Gets the USB voltage regulator enabled setting.
417 *
418 * This function gets the USB voltage regulator enabled setting.
419 *
420 * @param baseAddr Base address for current SIM instance.
421 * @return enabled True if the USB voltage regulator is enabled.
422 */
423 static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(uint32_t baseAddr)
424 {
425 return BR_SIM_SOPT1_USBREGEN(baseAddr);
426 }
427
428 /*!
429 * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS.
430 *
431 * This function controls whether the USB voltage regulator is placed in a standby
432 * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the
433 * SOPT1CFG[USSWE] bit is set.
434 *
435 * @param baseAddr Base address for current SIM instance.
436 * @param setting USB voltage regulator in standby mode setting
437 * - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and
438 * VLLS modes.
439 * - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
440 * modes.
441 */
442 static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(uint32_t baseAddr,
443 sim_usbsstby_stop_t setting)
444 {
445 BW_SIM_SOPT1_USBSSTBY(baseAddr, setting);
446 }
447
448 /*!
449 * @brief Gets the USB voltage regulator in a standby mode setting.
450 *
451 * This function gets the USB voltage regulator in a standby mode setting.
452 *
453 * @param baseAddr Base address for current SIM instance.
454 * @return setting USB voltage regulator in a standby mode setting
455 */
456 static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(uint32_t baseAddr)
457 {
458 return (sim_usbsstby_stop_t)BR_SIM_SOPT1_USBSSTBY(baseAddr);
459 }
460
461 /*!
462 * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
463 *
464 * This function controls whether the USB voltage regulator is placed in a standby
465 * mode during the VLPR and the VLPW modes. This bit can only be written when the
466 * SOPT1CFG[UVSWE] bit is set.
467 *
468 * @param baseAddr Base address for current SIM instance.
469 * @param setting USB voltage regulator in standby mode setting
470 * - 0: USB voltage regulator not in standby during VLPR and VLPW modes.
471 * - 1: USB voltage regulator in standby during VLPR and VLPW modes.
472 */
473 static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(uint32_t baseAddr,
474 sim_usbvstby_stop_t setting)
475 {
476 BW_SIM_SOPT1_USBVSTBY(baseAddr, setting);
477 }
478
479 /*!
480 * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
481 *
482 * This function gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
483 *
484 * @param baseAddr Base address for current SIM instance.
485 * @return setting USB voltage regulator in a standby mode during the VLPR or the VLPW
486 */
487 static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(uint32_t baseAddr)
488 {
489 return (sim_usbvstby_stop_t)BR_SIM_SOPT1_USBVSTBY(baseAddr);
490 }
491
492 /*!
493 * @brief Sets the USB voltage regulator stop standby write enable setting.
494 *
495 * This function controls whether the USB voltage regulator stop standby write
496 * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
497 * register bit clears after a write to SOPT1[USBSSTBY].
498 *
499 * @param baseAddr Base address for current SIM instance.
500 * @param enable USB voltage regulator stop standby write enable setting
501 * - true: SOPT1[USBSSTBY] can be written.
502 * - false: SOPT1[USBSSTBY] cannot be written.
503 */
504 static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(uint32_t baseAddr, bool enable)
505 {
506 BW_SIM_SOPT1CFG_USSWE(baseAddr, enable ? 1 : 0);
507 }
508
509 /*!
510 * @brief Gets the USB voltage regulator stop standby write enable setting.
511 *
512 * This function gets the USB voltage regulator stop standby write enable setting.
513 *
514 * @param baseAddr Base address for current SIM instance.
515 * @return enabled True if the USB voltage regulator stop standby write is enabled.
516 */
517 static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(uint32_t baseAddr)
518 {
519 return BR_SIM_SOPT1CFG_USSWE(baseAddr);
520 }
521
522 /*!
523 * @brief Sets the USB voltage regulator VLP standby write enable setting.
524 *
525 * This function controls whether USB voltage regulator VLP standby write
526 * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
527 * register bit clears after a write to SOPT1[USBVSTBY].
528 *
529 * @param baseAddr Base address for current SIM instance.
530 * @param enable USB voltage regulator VLP standby write enable setting
531 * - true: SOPT1[USBSSTBY] can be written.
532 * - false: SOPT1[USBSSTBY] cannot be written.
533 */
534 static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(uint32_t baseAddr, bool enable)
535 {
536 BW_SIM_SOPT1CFG_UVSWE(baseAddr, enable ? 1 : 0);
537 }
538
539 /*!
540 * @brief Gets the USB voltage regulator VLP standby write enable setting.
541 *
542 * This function gets the USB voltage regulator VLP standby write enable setting.
543 *
544 * @param baseAddr Base address for current SIM instance.
545 * @return enabled True if the USB voltage regulator VLP standby write is enabled.
546 */
547 static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(uint32_t baseAddr)
548 {
549 return BR_SIM_SOPT1CFG_UVSWE(baseAddr);
550 }
551
552 /*!
553 * @brief Sets the USB voltage regulator enable write enable setting.
554 *
555 * This function controls whether the USB voltage regulator write enable
556 * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written.
557 * This register bit clears after a write to SOPT1[USBREGEN].
558 *
559 * @param baseAddr Base address for current SIM instance.
560 * @param enable USB voltage regulator enable write enable setting
561 * - true: SOPT1[USBSSTBY] can be written.
562 * - false: SOPT1[USBSSTBY] cannot be written.
563 */
564 static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(uint32_t baseAddr, bool enable)
565 {
566 BW_SIM_SOPT1CFG_URWE(baseAddr, enable ? 1 : 0);
567 }
568
569 /*!
570 * @brief Gets the USB voltage regulator enable write enable setting.
571 *
572 * This function gets the USB voltage regulator enable write enable setting.
573 *
574 * @param baseAddr Base address for current SIM instance.
575 * @return enabled True if USB voltage regulator enable write is enabled.
576 */
577 static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(uint32_t baseAddr)
578 {
579 return BR_SIM_SOPT1CFG_URWE(baseAddr);
580 }
581 #endif
582
583 #if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD
584 /*!
585 * @brief Sets the CMT/UART pad drive strength setting.
586 *
587 * This function controls the output drive strength of the CMT IRO signal or
588 * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it.
589 *
590 * @param baseAddr Base address for current SIM instance.
591 * @param setting CMT/UART pad drive strength setting
592 * - 0: Single-pad drive strength for CMT IRO or UART0_TXD.
593 * - 1: Dual-pad drive strength for CMT IRO or UART0_TXD.
594 */
595 static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(uint32_t baseAddr,
596 sim_cmtuartpad_strengh_t setting)
597 {
598 BW_SIM_SOPT2_CMTUARTPAD(baseAddr, setting);
599 }
600
601 /*!
602 * @brief Gets the CMT/UART pad drive strength setting.
603 *
604 * This function gets the CMT/UART pad drive strength setting.
605 *
606 * @param baseAddr Base address for current SIM instance.
607 * @return setting CMT/UART pad drive strength setting
608 */
609 static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(uint32_t baseAddr)
610 {
611 return (sim_cmtuartpad_strengh_t)BR_SIM_SOPT2_CMTUARTPAD(baseAddr);
612 }
613 #endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */
614
615 #if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD
616 /*!
617 * @brief Sets the PTD7 pad drive strength setting.
618 *
619 * This function controls the output drive strength of the PTD7 pin by selecting
620 * either one or two pads to drive it.
621 *
622 * @param baseAddr Base address for current SIM instance.
623 * @param setting PTD7 pad drive strength setting
624 * - 0: Single-pad drive strength for PTD7.
625 * - 1: Double pad drive strength for PTD7.
626 */
627 static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(uint32_t baseAddr,
628 sim_ptd7pad_strengh_t setting)
629 {
630 BW_SIM_SOPT2_PTD7PAD(baseAddr, setting);
631 }
632
633 /*!
634 * @brief Gets the PTD7 pad drive strength setting.
635 *
636 * This function gets the PTD7 pad drive strength setting.
637 *
638 * @param baseAddr Base address for current SIM instance.
639 * @return setting PTD7 pad drive strength setting
640 */
641 static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(uint32_t baseAddr)
642 {
643 return (sim_ptd7pad_strengh_t)BR_SIM_SOPT2_PTD7PAD(baseAddr);
644 }
645 #endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */
646
647 #if FSL_FEATURE_SIM_OPT_HAS_FBSL
648 /*!
649 * @brief Sets the FlexBus security level setting.
650 *
651 * This function sets the FlexBus security level setting. If the security is enabled,
652 * this field affects which CPU operations can access the off-chip via the FlexBus
653 * and DDR controller interfaces. This field has no effect if the security is not enabled.
654 *
655 * @param baseAddr Base address for current SIM instance.
656 * @param setting FlexBus security level setting
657 * - 00: All off-chip accesses (op code and data) via the FlexBus and
658 * DDR controller are disallowed.
659 * - 10: Off-chip op code accesses are disallowed. Data accesses are
660 * allowed.
661 * - 11: Off-chip op code accesses and data accesses are allowed.
662 */
663 static inline void SIM_HAL_SetFlexbusSecurityLevelMode(uint32_t baseAddr,
664 sim_flexbus_security_level_t setting)
665 {
666 BW_SIM_SOPT2_FBSL(baseAddr, setting);
667 }
668
669 /*!
670 * @brief Gets the FlexBus security level setting.
671 *
672 * This function gets the FlexBus security level setting.
673 *
674 * @param baseAddr Base address for current SIM instance.
675 * @return setting FlexBus security level setting
676 */
677 static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(uint32_t baseAddr)
678 {
679 return (sim_flexbus_security_level_t)BR_SIM_SOPT2_FBSL(baseAddr);
680 }
681 #endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */
682
683 #if FSL_FEATURE_SIM_OPT_HAS_PCR
684 /*!
685 * @brief Sets the PCR setting.
686 *
687 * This function sets the PCR setting. This is the FlexBus hold cycles before
688 * FlexBus can release bus to NFC or to IDLE.
689 *
690 * @param baseAddr Base address for current SIM instance.
691 * @param setting PCR setting
692 */
693 static inline void SIM_HAL_SetFlexbusHoldCycles(uint32_t baseAddr, uint32_t setting)
694 {
695 BW_SIM_SOPT6_PCR(baseAddr, setting);
696 }
697
698 /*!
699 * @brief Gets the PCR setting.
700 *
701 * This function gets the PCR setting.
702 *
703 * @param baseAddr Base address for current SIM instance.
704 * @return setting PCR setting
705 */
706 static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(uint32_t baseAddr)
707 {
708 return BR_SIM_SOPT6_PCR(baseAddr);
709 }
710 #endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */
711
712 #if FSL_FEATURE_SIM_OPT_HAS_MCC
713 /*!
714 * @brief Sets the MCC setting.
715 *
716 * This function sets the MCC setting. This is the NFC hold cycle in case the
717 * FlexBus request during NFC is granted.
718 *
719 * @param baseAddr Base address for current SIM instance.
720 * @param setting MCC setting
721 */
722 static inline void SIM_HAL_SetNandFlashControllerHoldCycles(uint32_t baseAddr, uint32_t setting)
723 {
724 BW_SIM_SOPT6_MCC(baseAddr, setting);
725 }
726
727 /*!
728 * @brief Gets the MCC setting.
729 *
730 * This function gets the MCC setting.
731 *
732 * @param baseAddr Base address for current SIM instance.
733 * @return setting MCC setting
734 */
735 static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(uint32_t baseAddr)
736 {
737 return BR_SIM_SOPT6_MCC(baseAddr);
738 }
739 #endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */
740
741 /*!
742 * @brief Sets the ADCx alternate trigger enable setting.
743 *
744 * This function enables/disables the alternative conversion triggers for ADCx.
745 *
746 * @param baseAddr Base address for current SIM instance.
747 * @param instance device instance.
748 * @param enable Enable alternative conversion triggers for ADCx
749 * - true: Select alternative conversion trigger.
750 * - false: Select PDB trigger.
751 */
752 void SIM_HAL_SetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance, bool enable);
753
754 /*!
755 * @brief Gets the ADCx alternate trigger enable setting.
756 *
757 * This function gets the ADCx alternate trigger enable setting.
758 *
759 * @param baseAddr Base address for current SIM instance.
760 * @param instance device instance.
761 * @return enabled True if ADCx alternate trigger is enabled
762 */
763 bool SIM_HAL_GetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance);
764
765 /*!
766 * @brief Sets the ADCx pre-trigger select setting.
767 *
768 * This function selects the ADCx pre-trigger source when the alternative triggers
769 * are enabled through ADCxALTTRGEN.
770 *
771 * @param baseAddr Base address for current SIM instance.
772 * @param instance device instance.
773 * @param select pre-trigger select setting for ADCx
774 * - 0: Pre-trigger A selected for ADCx.
775 * - 1: Pre-trigger B selected for ADCx.
776 */
777 void SIM_HAL_SetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance, sim_pretrgsel_t select);
778
779 /*!
780 * @brief Gets the ADCx pre-trigger select setting.
781 *
782 * This function gets the ADCx pre-trigger select setting.
783 *
784 * @param baseAddr Base address for current SIM instance.
785 * @param instance device instance.
786 * @return select ADCx pre-trigger select setting
787 */
788 sim_pretrgsel_t SIM_HAL_GetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance);
789
790 /*!
791 * @brief Sets the ADCx trigger select setting.
792 *
793 * This function selects the ADCx trigger source when alternative triggers
794 * are enabled through ADCxALTTRGEN.
795 *
796 * @param baseAddr Base address for current SIM instance.
797 * @param instance device instance.
798 * @param select trigger select setting for ADCx
799 * - 0000: External trigger
800 * - 0001: High speed comparator 0 asynchronous interrupt
801 * - 0010: High speed comparator 1 asynchronous interrupt
802 * - 0011: High speed comparator 2 asynchronous interrupt
803 * - 0100: PIT trigger 0
804 * - 0101: PIT trigger 1
805 * - 0110: PIT trigger 2
806 * - 0111: PIT trigger 3
807 * - 1000: FTM0 trigger
808 * - 1001: FTM1 trigger
809 * - 1010: FTM2 trigger
810 * - 1011: FTM3 trigger
811 * - 1100: RTC alarm
812 * - 1101: RTC seconds
813 * - 1110: Low-power timer trigger
814 * - 1111: High speed comparator 3 asynchronous interrupt
815 */
816 void SIM_HAL_SetAdcTriggerMode(uint32_t baseAddr, uint8_t instance, sim_trgsel_t select);
817
818 /*!
819 * @brief Gets the ADCx trigger select setting.
820 *
821 * This function gets the ADCx trigger select setting.
822 *
823 * @param baseAddr Base address for current SIM instance.
824 * @param instance device instance.
825 * @return select ADCx trigger select setting
826 */
827 sim_pretrgsel_t SIM_HAL_GetAdcTriggerMode(uint32_t baseAddr, uint8_t instance);
828
829 /*!
830 * @brief Sets the UARTx receive data source select setting.
831 *
832 * This function selects the source for the UARTx receive data.
833 *
834 * @param baseAddr Base address for current SIM instance.
835 * @param instance device instance.
836 * @param select the source for the UARTx receive data
837 * - 00: UARTx_RX pin.
838 * - 01: CMP0.
839 * - 10: CMP1.
840 * - 11: Reserved.
841 */
842 void SIM_HAL_SetUartRxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_rxsrc_t select);
843
844 /*!
845 * @brief Gets the UARTx receive data source select setting.
846 *
847 * This function gets the UARTx receive data source select setting.
848 *
849 * @param baseAddr Base address for current SIM instance.
850 * @param instance device instance.
851 * @return select UARTx receive data source select setting
852 */
853 sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(uint32_t baseAddr, uint8_t instance);
854
855 /*!
856 * @brief Sets the UARTx transmit data source select setting.
857 *
858 * This function selects the source for the UARTx transmit data.
859 *
860 * @param baseAddr Base address for current SIM instance.
861 * @param instance device instance.
862 * @param select the source for the UARTx transmit data
863 * - 00: UARTx_TX pin.
864 * - 01: UARTx_TX pin modulated with FTM1 channel 0 output.
865 * - 10: UARTx_TX pin modulated with FTM2 channel 0 output.
866 * - 11: Reserved.
867 */
868 void SIM_HAL_SetUartTxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_txsrc_t select);
869
870 /*!
871 * @brief Gets the UARTx transmit data source select setting.
872 *
873 * This function gets the UARTx transmit data source select setting.
874 *
875 * @param baseAddr Base address for current SIM instance.
876 * @param instance device instance.
877 * @return select UARTx transmit data source select setting
878 */
879 sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(uint32_t baseAddr, uint8_t instance);
880
881 #if FSL_FEATURE_SIM_OPT_HAS_ODE
882 /*!
883 * @brief Sets the UARTx Open Drain Enable setting.
884 *
885 * This function enables/disables the UARTx Open Drain.
886 *
887 * @param baseAddr Base address for current SIM instance.
888 * @param instance device instance.
889 * @param enable Enable/disable UARTx Open Drain
890 * - True: Enable UARTx Open Drain
891 * - False: Disable UARTx Open Drain
892 */
893 void SIM_HAL_SetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance, bool enable);
894
895 /*!
896 * @brief Gets the UARTx Open Drain Enable setting.
897 *
898 * This function gets the UARTx Open Drain Enable setting.
899 *
900 * @param baseAddr Base address for current SIM instance.
901 * @param instance device instance.
902 * @return enabled True if UARTx Open Drain is enabled.
903 */
904 bool SIM_HAL_GetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance);
905 #endif
906
907 #if FSL_FEATURE_SIM_OPT_HAS_FTM
908 /*!
909 * @brief Sets the FlexTimer x hardware trigger y source select setting.
910 *
911 * This function selects the source of FTMx hardware trigger y.
912 *
913 * @param baseAddr Base address for current SIM instance.
914 * @param instance device instance.
915 * @param trigger hardware trigger y
916 * @param select FlexTimer x hardware trigger y
917 * - 0: Pre-trigger A selected for ADCx.
918 * - 1: Pre-trigger B selected for ADCx.
919 */
920 void SIM_HAL_SetFtmTriggerSrcMode(uint32_t baseAddr,
921 uint8_t instance,
922 uint8_t trigger,
923 sim_ftm_trg_src_t select);
924
925 /*!
926 * @brief Gets the FlexTimer x hardware trigger y source select setting.
927 *
928 * This function gets the FlexTimer x hardware trigger y source select setting.
929 *
930 * @param baseAddr Base address for current SIM instance.
931 * @param instance device instance.
932 * @param trigger hardware trigger y
933 * @return select FlexTimer x hardware trigger y source select setting
934 */
935 sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t trigger);
936
937 /*!
938 * @brief Sets the FlexTimer x external clock pin select setting.
939 *
940 * This function selects the source of FTMx external clock pin select.
941 *
942 * @param baseAddr Base address for current SIM instance.
943 * @param instance device instance.
944 * @param select FTMx external clock pin select
945 * - 0: FTMx external clock driven by FTM CLKIN0 pin.
946 * - 1: FTMx external clock driven by FTM CLKIN1 pin.
947 */
948 void SIM_HAL_SetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance, sim_ftm_clk_sel_t select);
949
950 /*!
951 * @brief Gets the FlexTimer x external clock pin select setting.
952 *
953 * This function gets the FlexTimer x external clock pin select setting.
954 *
955 * @param baseAddr Base address for current SIM instance.
956 * @param instance device instance.
957 * @return select FlexTimer x external clock pin select setting
958 */
959 sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance);
960
961 /*!
962 * @brief Sets the FlexTimer x channel y input capture source select setting.
963 *
964 * This function selects the FlexTimer x channel y input capture source.
965 *
966 * @param baseAddr Base address for current SIM instance.
967 * @param instance device instance.
968 * @param channel FlexTimer channel y
969 * @param select FlexTimer x channel y input capture source
970 * See the reference manual for detailed definition for each channel and selection.
971 */
972 void SIM_HAL_SetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel, sim_ftm_ch_src_t select);
973
974 /*!
975 * @brief Gets the FlexTimer x channel y input capture source select setting.
976 *
977 * This function gets the FlexTimer x channel y input capture source select setting.
978 *
979 * @param baseAddr Base address for current SIM instance.
980 * @param instance device instance.
981 * @param channel FlexTimer channel y
982 * @return select FlexTimer x channel y input capture source select setting
983 */
984 sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel);
985
986 /*!
987 * @brief Sets the FlexTimer x fault y select setting.
988 *
989 * This function sets the FlexTimer x fault y select setting.
990 *
991 * @param baseAddr Base address for current SIM instance.
992 * @param instance device instance.
993 * @param fault fault y
994 * @param select FlexTimer x fault y select setting
995 * - 0: FlexTimer x fault y select 0.
996 * - 1: FlexTimer x fault y select 1.
997 */
998 void SIM_HAL_SetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select);
999
1000 /*!
1001 * @brief Gets the FlexTimer x fault y select setting.
1002 *
1003 * This function gets the FlexTimer x fault y select setting.
1004 *
1005 * @param baseAddr Base address for current SIM instance.
1006 * @param instance device instance.
1007 * @param fault fault y
1008 * @return select FlexTimer x fault y select setting
1009 */
1010 sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault);
1011 #endif
1012
1013 #if FSL_FEATURE_SIM_OPT_HAS_TPM
1014 /*!
1015 * @brief Sets the Timer/PWM x external clock pin select setting.
1016 *
1017 * This function selects the source of the Timer/PWM x external clock pin select.
1018 *
1019 * @param baseAddr Base address for current SIM instance.
1020 * @param instance device instance.
1021 * @param select Timer/PWM x external clock pin select
1022 * - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin.
1023 * - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin.
1024 */
1025 void SIM_HAL_SetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance, sim_tpm_clk_sel_t select);
1026
1027 /*!
1028 * @brief Gets the Timer/PWM x external clock pin select setting.
1029 *
1030 * This function gets the Timer/PWM x external clock pin select setting.
1031 *
1032 * @param baseAddr Base address for current SIM instance.
1033 * @param instance device instance.
1034 * @return select Timer/PWM x external clock pin select setting
1035 */
1036 sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance);
1037
1038 /*!
1039 * @brief Sets the Timer/PWM x channel y input capture source select setting.
1040 *
1041 * This function selects the Timer/PWM x channel y input capture source.
1042 *
1043 * @param baseAddr Base address for current SIM instance.
1044 * @param instance device instance.
1045 * @param channel TPM channel y
1046 * @param select Timer/PWM x channel y input capture source
1047 * - 0: TPMx_CH0 signal
1048 * - 1: CMP0 output
1049 */
1050 void SIM_HAL_SetTpmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select);
1051
1052 /*!
1053 * @brief Gets the Timer/PWM x channel y input capture source select setting.
1054 *
1055 * This function gets the Timer/PWM x channel y input capture source select setting.
1056 *
1057 * @param baseAddr Base address for current SIM instance.
1058 * @param instance device instance.
1059 * @param channel Tpm channel y
1060 * @return select Timer/PWM x channel y input capture source select setting
1061 */
1062 sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel);
1063 #endif
1064
1065 #if FSL_FEATURE_SIM_SDID_HAS_FAMILYID
1066 /*!
1067 * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID).
1068 *
1069 * This function gets the Kinetis Family ID in the System Device ID register.
1070 *
1071 * @param baseAddr Base address for current SIM instance.
1072 * @return id Kinetis Family ID
1073 */
1074 static inline uint32_t SIM_HAL_GetFamilyId(uint32_t baseAddr)
1075 {
1076 return BR_SIM_SDID_FAMILYID(baseAddr);
1077 }
1078 #endif
1079
1080 #if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID
1081 /*!
1082 * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID).
1083 *
1084 * This function gets the Kinetis Sub-Family ID in System Device ID register.
1085 *
1086 * @param baseAddr Base address for current SIM instance.
1087 * @return id Kinetis Sub-Family ID
1088 */
1089 static inline uint32_t SIM_HAL_GetSubFamilyId(uint32_t baseAddr)
1090 {
1091 return BR_SIM_SDID_SUBFAMID(baseAddr);
1092 }
1093 #endif
1094
1095 #if FSL_FEATURE_SIM_SDID_HAS_SERIESID
1096 /*!
1097 * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID).
1098 *
1099 * This function gets the Kinetis Series ID in System Device ID register.
1100 *
1101 * @param baseAddr Base address for current SIM instance.
1102 * @return id Kinetis Series ID
1103 */
1104 static inline uint32_t SIM_HAL_GetSeriesId(uint32_t baseAddr)
1105 {
1106 return BR_SIM_SDID_SERIESID(baseAddr);
1107 }
1108 #endif
1109
1110 #if FSL_FEATURE_SIM_SDID_HAS_FAMID
1111 /*!
1112 * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID).
1113 *
1114 * This function gets the Kinetis Fam ID in System Device ID register.
1115 *
1116 * @param baseAddr Base address for current SIM instance.
1117 * @return id Kinetis Fam ID
1118 */
1119 static inline uint32_t SIM_HAL_GetFamId(uint32_t baseAddr)
1120 {
1121 return BR_SIM_SDID_FAMID(baseAddr);
1122 }
1123 #endif
1124
1125 /*!
1126 * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID).
1127 *
1128 * This function gets the Kinetis Pincount ID in System Device ID register.
1129 *
1130 * @param baseAddr Base address for current SIM instance.
1131 * @return id Kinetis Pincount ID
1132 */
1133 static inline uint32_t SIM_HAL_GetPinCntId(uint32_t baseAddr)
1134 {
1135 return BR_SIM_SDID_PINID(baseAddr);
1136 }
1137
1138 /*!
1139 * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID).
1140 *
1141 * This function gets the Kinetis Revision ID in System Device ID register.
1142 *
1143 * @param baseAddr Base address for current SIM instance.
1144 * @return id Kinetis Revision ID
1145 */
1146 static inline uint32_t SIM_HAL_GetRevId(uint32_t baseAddr)
1147 {
1148 return BR_SIM_SDID_REVID(baseAddr);
1149 }
1150
1151 #if FSL_FEATURE_SIM_SDID_HAS_DIEID
1152 /*!
1153 * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID).
1154 *
1155 * This function gets the Kinetis Die ID in System Device ID register.
1156 *
1157 * @param baseAddr Base address for current SIM instance.
1158 * @return id Kinetis Die ID
1159 */
1160 static inline uint32_t SIM_HAL_GetDieId(uint32_t baseAddr)
1161 {
1162 return BR_SIM_SDID_DIEID(baseAddr);
1163 }
1164 #endif
1165
1166 #if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE
1167 /*!
1168 * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID).
1169 *
1170 * This function gets the Kinetis SRAM Size in System Device ID register.
1171 *
1172 * @param baseAddr Base address for current SIM instance.
1173 * @return id Kinetis SRAM Size
1174 */
1175 static inline uint32_t SIM_HAL_GetSramSize(uint32_t baseAddr)
1176 {
1177 return BR_SIM_SDID_SRAMSIZE(baseAddr);
1178 }
1179 #endif
1180
1181 #if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE
1182 /*!
1183 * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG).
1184 *
1185 * This function gets the FlexNVM size in the Flash Configuration Register 1.
1186 *
1187 * @param baseAddr Base address for current SIM instance.
1188 * @return size FlexNVM Size
1189 */
1190 static inline uint32_t SIM_HAL_GetFlexnvmSize(uint32_t baseAddr)
1191 {
1192 return BR_SIM_FCFG1_NVMSIZE(baseAddr);
1193 }
1194 #endif
1195
1196 /*!
1197 * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG).
1198 *
1199 * This function gets the program flash size in the Flash Configuration Register 1.
1200 *
1201 * @param baseAddr Base address for current SIM instance.
1202 * @return size Program flash Size
1203 */
1204 static inline uint32_t SIM_HAL_GetProgramFlashSize(uint32_t baseAddr)
1205 {
1206 return BR_SIM_FCFG1_PFSIZE(baseAddr);
1207 }
1208
1209 #if FSL_FEATURE_SIM_FCFG_HAS_EESIZE
1210 /*!
1211 * @brief Gets the EEProm size in the Flash Configuration Register 1 (SIM_FCFG).
1212 *
1213 * This function gets the EEProm size in the Flash Configuration Register 1.
1214 *
1215 * @param baseAddr Base address for current SIM instance.
1216 * @return size EEProm Size
1217 */
1218 static inline uint32_t SIM_HAL_GetEepromSize(uint32_t baseAddr)
1219 {
1220 return BR_SIM_FCFG1_EESIZE(baseAddr);
1221 }
1222 #endif
1223
1224 #if FSL_FEATURE_SIM_FCFG_HAS_DEPART
1225 /*!
1226 * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG).
1227 *
1228 * This function gets the FlexNVM partition in the Flash Configuration Register 1
1229 *
1230 * @param baseAddr Base address for current SIM instance.
1231 * @return setting FlexNVM partition setting
1232 */
1233 static inline uint32_t SIM_HAL_GetFlexnvmPartition(uint32_t baseAddr)
1234 {
1235 return BR_SIM_FCFG1_DEPART(baseAddr);
1236 }
1237 #endif
1238
1239 #if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE
1240 /*!
1241 * @brief Sets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG).
1242 *
1243 * This function sets the Flash Doze in the Flash Configuration Register 1.
1244 *
1245 * @param baseAddr Base address for current SIM instance.
1246 * @param setting Flash Doze setting
1247 */
1248 static inline void SIM_HAL_SetFlashDoze(uint32_t baseAddr, uint32_t setting)
1249 {
1250 BW_SIM_FCFG1_FLASHDOZE(baseAddr, setting);
1251 }
1252
1253 /*!
1254 * @brief Gets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG).
1255 *
1256 * This function gets the Flash Doze in the Flash Configuration Register 1.
1257 *
1258 * @param baseAddr Base address for current SIM instance.
1259 * @return setting Flash Doze setting
1260 */
1261 static inline uint32_t SIM_HAL_GetFlashDoze(uint32_t baseAddr)
1262 {
1263 return BR_SIM_FCFG1_FLASHDOZE(baseAddr);
1264 }
1265 #endif
1266
1267 #if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS
1268 /*!
1269 * @brief Sets the Flash disable setting in the Flash Configuration Register 1 (SIM_FCFG).
1270 *
1271 * This function sets the Flash disable setting in the Flash Configuration Register 1.
1272 *
1273 * @param baseAddr Base address for current SIM instance.
1274 * @param disable Flash disable setting
1275 */
1276 static inline void SIM_HAL_SetFlashDisableCmd(uint32_t baseAddr, bool disable)
1277 {
1278 BW_SIM_FCFG1_FLASHDIS(baseAddr, disable);
1279 }
1280
1281 /*!
1282 * @brief Gets the Flash disable setting in the Flash Configuration Register 1 (SIM_FCFG).
1283 *
1284 * This function gets the Flash disable setting in the Flash Configuration Register 1.
1285 *
1286 * @param baseAddr Base address for current SIM instance.
1287 * @return setting Flash disable setting
1288 */
1289 static inline bool SIM_HAL_GetFlashDisableCmd(uint32_t baseAddr)
1290 {
1291 return (bool)BR_SIM_FCFG1_FLASHDIS(baseAddr);
1292 }
1293 #endif
1294
1295 #if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0
1296 /*!
1297 * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG).
1298 *
1299 * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
1300 *
1301 * @param baseAddr Base address for current SIM instance.
1302 * @return address Flash maximum block 0 address
1303 */
1304 static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(uint32_t baseAddr)
1305 {
1306 return BR_SIM_FCFG2_MAXADDR0(baseAddr);
1307 }
1308 #endif
1309
1310 #if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1
1311 /*!
1312 * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2.
1313 *
1314 * This function gets the Flash maximum block 1 in Flash Configuration Register 1.
1315 *
1316 * @param baseAddr Base address for current SIM instance.
1317 * @return address Flash maximum block 0 address
1318 */
1319 static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(uint32_t baseAddr)
1320 {
1321 return BR_SIM_FCFG2_MAXADDR1(baseAddr);
1322 }
1323 #endif
1324
1325 #if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01
1326 /*!
1327 * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG).
1328 *
1329 * This function gets the Flash maximum block 0 in Flash Configuration Register 2.
1330 *
1331 * @param baseAddr Base address for current SIM instance.
1332 * @return address Flash maximum block 0 address
1333 */
1334 static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(uint32_t baseAddr)
1335 {
1336 return BR_SIM_FCFG2_MAXADDR01(baseAddr);
1337 }
1338 #endif
1339
1340 #if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23
1341 /*!
1342 * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2.
1343 *
1344 * This function gets the Flash maximum block 1 in Flash Configuration Register 1.
1345 *
1346 * @param baseAddr Base address for current SIM instance.
1347 * @return address Flash maximum block 0 address
1348 */
1349 static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(uint32_t baseAddr)
1350 {
1351 return BR_SIM_FCFG2_MAXADDR23(baseAddr);
1352 }
1353 #endif
1354
1355 #if FSL_FEATURE_SIM_FCFG_HAS_PFLSH
1356 /*!
1357 * @brief Gets the program flash in the Flash Configuration Register 2.
1358 *
1359 * This function gets the program flash maximum block 0 in Flash Configuration Register 1.
1360 *
1361 * @param baseAddr Base address for current SIM instance.
1362 * @return status program flash status
1363 */
1364 static inline uint32_t SIM_HAL_GetProgramFlashCmd(uint32_t baseAddr)
1365 {
1366 return BR_SIM_FCFG2_PFLSH(baseAddr);
1367 }
1368 #endif
1369
1370 /*@}*/
1371
1372 #if defined(__cplusplus)
1373 }
1374 #endif /* __cplusplus*/
1375
1376 /*! @}*/
1377
1378
1379 /*
1380 * Include the CPU-specific clock API header files.
1381 */
1382 #if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
1383 defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
1384
1385 #define K02F12810_SERIES
1386
1387 #elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
1388 defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
1389 defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
1390 defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
1391 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
1392 defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
1393 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
1394 defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
1395 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
1396 defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
1397
1398 #define K20D5_SERIES
1399
1400
1401 #elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
1402 defined(CPU_MK22FN128VMP10))
1403
1404 #define K22F12810_SERIES
1405
1406 /* Clock System Level API header file */
1407 #include "MK22F12810/fsl_sim_hal_K22F12810.h"
1408
1409 #elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \
1410 defined(CPU_MK22FN256VMP12))
1411
1412 #define K22F25612_SERIES
1413
1414 /* Clock System Level API header file */
1415 #include "MK22F25612/fsl_sim_hal_K22F25612.h"
1416
1417
1418
1419 #elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12))
1420
1421 #define K22F51212_SERIES
1422
1423 /* Clock System Level API header file */
1424 #include "MK22F51212/fsl_sim_hal_K22F51212.h"
1425
1426
1427 #elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12))
1428
1429 #define K24F12_SERIES
1430
1431 /* Clock System Level API header file */
1432 #include "MK24F12/fsl_sim_hal_K24F12.h"
1433
1434 #elif (defined(CPU_MK24FN256VDC12))
1435
1436 #define K24F25612_SERIES
1437
1438
1439 #elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
1440
1441 #define K63F12_SERIES
1442
1443 /* Clock System Level API header file */
1444 #include "MK63F12/fsl_sim_hal_K63F12.h"
1445
1446 #elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
1447 defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
1448 defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
1449
1450 #define K64F12_SERIES
1451
1452 /* Clock System Level API header file */
1453 #include "MK64F12/fsl_sim_hal_K64F12.h"
1454
1455 #elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
1456 defined(CPU_MK65FX1M0VMI18))
1457
1458 #define K65F18_SERIES
1459
1460
1461 #elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
1462 defined(CPU_MK66FX1M0VMD18))
1463
1464 #define K66F18_SERIES
1465
1466
1467 #elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
1468 defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
1469 defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
1470
1471 #define K70F12_SERIES
1472
1473
1474 #elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
1475 defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
1476 defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
1477
1478 #define K70F15_SERIES
1479
1480
1481 #elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
1482 defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
1483 defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
1484
1485 #define KL02Z4_SERIES
1486
1487
1488 #elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
1489 defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
1490 defined(CPU_MKL03Z32VFK4))
1491
1492 #define KL03Z4_SERIES
1493
1494
1495 #elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
1496 defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
1497 defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
1498 defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
1499
1500 #define KL05Z4_SERIES
1501
1502
1503 #elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \
1504 defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \
1505 defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
1506 defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4))
1507
1508 #define KL13Z4_SERIES
1509
1510
1511 #elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \
1512 defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \
1513 defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
1514 defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4))
1515
1516 #define KL23Z4_SERIES
1517
1518
1519 #elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
1520 defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
1521 defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
1522 defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
1523
1524 #define KL25Z4_SERIES
1525
1526 /* Clock System Level API header file */
1527 #include "MKL25Z4/fsl_sim_hal_KL25Z4.h"
1528
1529 #elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \
1530 defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \
1531 defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
1532 defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \
1533 defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4))
1534
1535 #define KL26Z4_SERIES
1536
1537
1538 #elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
1539 defined(CPU_MKL33Z256VMP4))
1540
1541 #define KL33Z4_SERIES
1542
1543
1544 #elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \
1545 defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4))
1546
1547 #define KL43Z4_SERIES
1548
1549
1550 #elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
1551 defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4))
1552
1553 #define KL46Z4_SERIES
1554
1555
1556 #elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
1557 defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
1558
1559 #define KV30F12810_SERIES
1560
1561
1562 #elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
1563
1564 #define KV31F12810_SERIES
1565
1566 /* Clock System Level API header file */
1567 #include "MKV31F12810/fsl_sim_hal_KV31F12810.h"
1568
1569 #elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
1570
1571 #define KV31F25612_SERIES
1572
1573 /* Clock System Level API header file */
1574 #include "MKV31F25612/fsl_sim_hal_KV31F25612.h"
1575
1576
1577 #elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
1578
1579 #define KV31F51212_SERIES
1580
1581 /* Clock System Level API header file */
1582 #include "MKV31F51212/fsl_sim_hal_KV31F51212.h"
1583
1584 #elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
1585 defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
1586
1587 #define KV40F15_SERIES
1588
1589
1590 #elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
1591
1592 #define KV43F15_SERIES
1593
1594
1595 #elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
1596
1597 #define KV44F15_SERIES
1598
1599
1600 #elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
1601 defined(CPU_MKV45F256VLL15))
1602
1603 #define KV45F15_SERIES
1604
1605
1606 #elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
1607 defined(CPU_MKV46F256VLL15))
1608
1609 #define KV46F15_SERIES
1610
1611
1612 #else
1613 #error "No valid CPU defined!"
1614 #endif
1615
1616 #endif /* __FSL_SIM_HAL_H__*/
1617 /*******************************************************************************
1618 * EOF
1619 ******************************************************************************/
1620
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