tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_AXBS_REGISTERS_H__
  81 #define __HW_AXBS_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 AXBS
  88  *
  89  * Crossbar switch
  90  *
  91  * Registers defined in this header file:
  92  * - HW_AXBS_PRSn - Priority Registers Slave
  93  * - HW_AXBS_CRSn - Control Register
  94  * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
  95  * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
  96  * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
  97  * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
  98  * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
  99  * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
 100  *
 101  * - hw_axbs_t - Struct containing all module registers.
 102  */
 103
 104 #define HW_AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
 105
 106 /*******************************************************************************
 107  * HW_AXBS_PRSn - Priority Registers Slave
 108  ******************************************************************************/
 109
 110 /*!
 111  * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
 112  *
 113  * Reset value: 0x00543210U
 114  *
 115  * The priority registers (PRSn) set the priority of each master port on a per
 116  * slave port basis and reside in each slave port. The priority register can be
 117  * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
 118  * register can only be read; attempts to write to it have no effect on PRSn and
 119  * result in a bus-error response to the master initiating the write. Two available
 120  * masters must not be programmed with the same priority level. Attempts to
 121  * program two or more masters with the same priority level result in a bus-error
 122  * response and the PRSn is not updated. Valid values for the Mn priority fields
 123  * depend on which masters are available on the chip. This information can be found in
 124  * the chip-specific information for the crossbar. If the chip contains less
 125  * than five masters, values 0 to 3 are valid. Writing other values will result in
 126  * an error. If the chip contains five or more masters, valid values are 0 to n-1,
 127  * where n is the number of masters attached to the AXBS module. Other values
 128  * will result in an error.
 129  */
 130 typedef union _hw_axbs_prsn
 131 {
 132     uint32_t U;
 133     struct _hw_axbs_prsn_bitfields
 134     {
 135         uint32_t M0 : 3;               /*!< [2:0] Master 0 Priority. Sets the arbitration
 136                                         * priority for this port on the associated slave port. */
 137         uint32_t RESERVED0 : 1;        /*!< [3]  */
 138         uint32_t M1 : 3;               /*!< [6:4] Master 1 Priority. Sets the arbitration
 139                                         * priority for this port on the associated slave port. */
 140         uint32_t RESERVED1 : 1;        /*!< [7]  */
 141         uint32_t M2 : 3;               /*!< [10:8] Master 2 Priority. Sets the arbitration
 142                                         * priority for this port on the associated slave port. */
 143         uint32_t RESERVED2 : 1;        /*!< [11]  */
 144         uint32_t M3 : 3;               /*!< [14:12] Master 3 Priority. Sets the arbitration
 145                                         * priority for this port on the associated slave port. */
 146         uint32_t RESERVED3 : 1;        /*!< [15]  */
 147         uint32_t M4 : 3;               /*!< [18:16] Master 4 Priority. Sets the arbitration
 148                                         * priority for this port on the associated slave port. */
 149         uint32_t RESERVED4 : 1;        /*!< [19]  */
 150         uint32_t M5 : 3;               /*!< [22:20] Master 5 Priority. Sets the arbitration
 151                                         * priority for this port on the associated slave port. */
 152         uint32_t RESERVED5 : 9;        /*!< [31:23]  */
 153     } B;
 154 } hw_axbs_prsn_t;
 155
 156 /*!
 157  * @name Constants and macros for entire AXBS_PRSn register
 158  */
 159 /*@{*/
 160 #define HW_AXBS_PRSn_COUNT (5U)
 161
 162 #define HW_AXBS_PRSn_ADDR(x, n)  ((x) + 0x0U + (0x100U * (n)))
 163
 164 #define HW_AXBS_PRSn(x, n)       (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(x, n))
 165 #define HW_AXBS_PRSn_RD(x, n)    (HW_AXBS_PRSn(x, n).U)
 166 #define HW_AXBS_PRSn_WR(x, n, v) (HW_AXBS_PRSn(x, n).U = (v))
 167 #define HW_AXBS_PRSn_SET(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) |  (v)))
 168 #define HW_AXBS_PRSn_CLR(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) & ~(v)))
 169 #define HW_AXBS_PRSn_TOG(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) ^  (v)))
 170 /*@}*/
 171
 172 /*
 173  * Constants & macros for individual AXBS_PRSn bitfields
 174  */
 175
 176 /*!
 177  * @name Register AXBS_PRSn, field M0[2:0] (RW)
 178  *
 179  * Values:
 180  * - 000 - This master has level 1, or highest, priority when accessing the
 181  *     slave port.
 182  * - 001 - This master has level 2 priority when accessing the slave port.
 183  * - 010 - This master has level 3 priority when accessing the slave port.
 184  * - 011 - This master has level 4 priority when accessing the slave port.
 185  * - 100 - This master has level 5 priority when accessing the slave port.
 186  * - 101 - This master has level 6 priority when accessing the slave port.
 187  * - 110 - This master has level 7 priority when accessing the slave port.
 188  * - 111 - This master has level 8, or lowest, priority when accessing the slave
 189  *     port.
 190  */
 191 /*@{*/
 192 #define BP_AXBS_PRSn_M0      (0U)          /*!< Bit position for AXBS_PRSn_M0. */
 193 #define BM_AXBS_PRSn_M0      (0x00000007U) /*!< Bit mask for AXBS_PRSn_M0. */
 194 #define BS_AXBS_PRSn_M0      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M0. */
 195
 196 /*! @brief Read current value of the AXBS_PRSn_M0 field. */
 197 #define BR_AXBS_PRSn_M0(x, n) (HW_AXBS_PRSn(x, n).B.M0)
 198
 199 /*! @brief Format value for bitfield AXBS_PRSn_M0. */
 200 #define BF_AXBS_PRSn_M0(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M0) & BM_AXBS_PRSn_M0)
 201
 202 /*! @brief Set the M0 field to a new value. */
 203 #define BW_AXBS_PRSn_M0(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
 204 /*@}*/
 205
 206 /*!
 207  * @name Register AXBS_PRSn, field M1[6:4] (RW)
 208  *
 209  * Values:
 210  * - 000 - This master has level 1, or highest, priority when accessing the
 211  *     slave port.
 212  * - 001 - This master has level 2 priority when accessing the slave port.
 213  * - 010 - This master has level 3 priority when accessing the slave port.
 214  * - 011 - This master has level 4 priority when accessing the slave port.
 215  * - 100 - This master has level 5 priority when accessing the slave port.
 216  * - 101 - This master has level 6 priority when accessing the slave port.
 217  * - 110 - This master has level 7 priority when accessing the slave port.
 218  * - 111 - This master has level 8, or lowest, priority when accessing the slave
 219  *     port.
 220  */
 221 /*@{*/
 222 #define BP_AXBS_PRSn_M1      (4U)          /*!< Bit position for AXBS_PRSn_M1. */
 223 #define BM_AXBS_PRSn_M1      (0x00000070U) /*!< Bit mask for AXBS_PRSn_M1. */
 224 #define BS_AXBS_PRSn_M1      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M1. */
 225
 226 /*! @brief Read current value of the AXBS_PRSn_M1 field. */
 227 #define BR_AXBS_PRSn_M1(x, n) (HW_AXBS_PRSn(x, n).B.M1)
 228
 229 /*! @brief Format value for bitfield AXBS_PRSn_M1. */
 230 #define BF_AXBS_PRSn_M1(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M1) & BM_AXBS_PRSn_M1)
 231
 232 /*! @brief Set the M1 field to a new value. */
 233 #define BW_AXBS_PRSn_M1(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
 234 /*@}*/
 235
 236 /*!
 237  * @name Register AXBS_PRSn, field M2[10:8] (RW)
 238  *
 239  * Values:
 240  * - 000 - This master has level 1, or highest, priority when accessing the
 241  *     slave port.
 242  * - 001 - This master has level 2 priority when accessing the slave port.
 243  * - 010 - This master has level 3 priority when accessing the slave port.
 244  * - 011 - This master has level 4 priority when accessing the slave port.
 245  * - 100 - This master has level 5 priority when accessing the slave port.
 246  * - 101 - This master has level 6 priority when accessing the slave port.
 247  * - 110 - This master has level 7 priority when accessing the slave port.
 248  * - 111 - This master has level 8, or lowest, priority when accessing the slave
 249  *     port.
 250  */
 251 /*@{*/
 252 #define BP_AXBS_PRSn_M2      (8U)          /*!< Bit position for AXBS_PRSn_M2. */
 253 #define BM_AXBS_PRSn_M2      (0x00000700U) /*!< Bit mask for AXBS_PRSn_M2. */
 254 #define BS_AXBS_PRSn_M2      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M2. */
 255
 256 /*! @brief Read current value of the AXBS_PRSn_M2 field. */
 257 #define BR_AXBS_PRSn_M2(x, n) (HW_AXBS_PRSn(x, n).B.M2)
 258
 259 /*! @brief Format value for bitfield AXBS_PRSn_M2. */
 260 #define BF_AXBS_PRSn_M2(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M2) & BM_AXBS_PRSn_M2)
 261
 262 /*! @brief Set the M2 field to a new value. */
 263 #define BW_AXBS_PRSn_M2(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
 264 /*@}*/
 265
 266 /*!
 267  * @name Register AXBS_PRSn, field M3[14:12] (RW)
 268  *
 269  * Values:
 270  * - 000 - This master has level 1, or highest, priority when accessing the
 271  *     slave port.
 272  * - 001 - This master has level 2 priority when accessing the slave port.
 273  * - 010 - This master has level 3 priority when accessing the slave port.
 274  * - 011 - This master has level 4 priority when accessing the slave port.
 275  * - 100 - This master has level 5 priority when accessing the slave port.
 276  * - 101 - This master has level 6 priority when accessing the slave port.
 277  * - 110 - This master has level 7 priority when accessing the slave port.
 278  * - 111 - This master has level 8, or lowest, priority when accessing the slave
 279  *     port.
 280  */
 281 /*@{*/
 282 #define BP_AXBS_PRSn_M3      (12U)         /*!< Bit position for AXBS_PRSn_M3. */
 283 #define BM_AXBS_PRSn_M3      (0x00007000U) /*!< Bit mask for AXBS_PRSn_M3. */
 284 #define BS_AXBS_PRSn_M3      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M3. */
 285
 286 /*! @brief Read current value of the AXBS_PRSn_M3 field. */
 287 #define BR_AXBS_PRSn_M3(x, n) (HW_AXBS_PRSn(x, n).B.M3)
 288
 289 /*! @brief Format value for bitfield AXBS_PRSn_M3. */
 290 #define BF_AXBS_PRSn_M3(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M3) & BM_AXBS_PRSn_M3)
 291
 292 /*! @brief Set the M3 field to a new value. */
 293 #define BW_AXBS_PRSn_M3(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
 294 /*@}*/
 295
 296 /*!
 297  * @name Register AXBS_PRSn, field M4[18:16] (RW)
 298  *
 299  * Values:
 300  * - 000 - This master has level 1, or highest, priority when accessing the
 301  *     slave port.
 302  * - 001 - This master has level 2 priority when accessing the slave port.
 303  * - 010 - This master has level 3 priority when accessing the slave port.
 304  * - 011 - This master has level 4 priority when accessing the slave port.
 305  * - 100 - This master has level 5 priority when accessing the slave port.
 306  * - 101 - This master has level 6 priority when accessing the slave port.
 307  * - 110 - This master has level 7 priority when accessing the slave port.
 308  * - 111 - This master has level 8, or lowest, priority when accessing the slave
 309  *     port.
 310  */
 311 /*@{*/
 312 #define BP_AXBS_PRSn_M4      (16U)         /*!< Bit position for AXBS_PRSn_M4. */
 313 #define BM_AXBS_PRSn_M4      (0x00070000U) /*!< Bit mask for AXBS_PRSn_M4. */
 314 #define BS_AXBS_PRSn_M4      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M4. */
 315
 316 /*! @brief Read current value of the AXBS_PRSn_M4 field. */
 317 #define BR_AXBS_PRSn_M4(x, n) (HW_AXBS_PRSn(x, n).B.M4)
 318
 319 /*! @brief Format value for bitfield AXBS_PRSn_M4. */
 320 #define BF_AXBS_PRSn_M4(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M4) & BM_AXBS_PRSn_M4)
 321
 322 /*! @brief Set the M4 field to a new value. */
 323 #define BW_AXBS_PRSn_M4(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
 324 /*@}*/
 325
 326 /*!
 327  * @name Register AXBS_PRSn, field M5[22:20] (RW)
 328  *
 329  * Values:
 330  * - 000 - This master has level 1, or highest, priority when accessing the
 331  *     slave port.
 332  * - 001 - This master has level 2 priority when accessing the slave port.
 333  * - 010 - This master has level 3 priority when accessing the slave port.
 334  * - 011 - This master has level 4 priority when accessing the slave port.
 335  * - 100 - This master has level 5 priority when accessing the slave port.
 336  * - 101 - This master has level 6 priority when accessing the slave port.
 337  * - 110 - This master has level 7 priority when accessing the slave port.
 338  * - 111 - This master has level 8, or lowest, priority when accessing the slave
 339  *     port.
 340  */
 341 /*@{*/
 342 #define BP_AXBS_PRSn_M5      (20U)         /*!< Bit position for AXBS_PRSn_M5. */
 343 #define BM_AXBS_PRSn_M5      (0x00700000U) /*!< Bit mask for AXBS_PRSn_M5. */
 344 #define BS_AXBS_PRSn_M5      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M5. */
 345
 346 /*! @brief Read current value of the AXBS_PRSn_M5 field. */
 347 #define BR_AXBS_PRSn_M5(x, n) (HW_AXBS_PRSn(x, n).B.M5)
 348
 349 /*! @brief Format value for bitfield AXBS_PRSn_M5. */
 350 #define BF_AXBS_PRSn_M5(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M5) & BM_AXBS_PRSn_M5)
 351
 352 /*! @brief Set the M5 field to a new value. */
 353 #define BW_AXBS_PRSn_M5(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
 354 /*@}*/
 355 /*******************************************************************************
 356  * HW_AXBS_CRSn - Control Register
 357  ******************************************************************************/
 358
 359 /*!
 360  * @brief HW_AXBS_CRSn - Control Register (RW)
 361  *
 362  * Reset value: 0x00000000U
 363  *
 364  * These registers control several features of each slave port and must be
 365  * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
 366  * attempts to write to it have no effect and result in an error response.
 367  */
 368 typedef union _hw_axbs_crsn
 369 {
 370     uint32_t U;
 371     struct _hw_axbs_crsn_bitfields
 372     {
 373         uint32_t PARK : 3;             /*!< [2:0] Park */
 374         uint32_t RESERVED0 : 1;        /*!< [3]  */
 375         uint32_t PCTL : 2;             /*!< [5:4] Parking Control */
 376         uint32_t RESERVED1 : 2;        /*!< [7:6]  */
 377         uint32_t ARB : 2;              /*!< [9:8] Arbitration Mode */
 378         uint32_t RESERVED2 : 20;       /*!< [29:10]  */
 379         uint32_t HLP : 1;              /*!< [30] Halt Low Priority */
 380         uint32_t RO : 1;               /*!< [31] Read Only */
 381     } B;
 382 } hw_axbs_crsn_t;
 383
 384 /*!
 385  * @name Constants and macros for entire AXBS_CRSn register
 386  */
 387 /*@{*/
 388 #define HW_AXBS_CRSn_COUNT (5U)
 389
 390 #define HW_AXBS_CRSn_ADDR(x, n)  ((x) + 0x10U + (0x100U * (n)))
 391
 392 #define HW_AXBS_CRSn(x, n)       (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(x, n))
 393 #define HW_AXBS_CRSn_RD(x, n)    (HW_AXBS_CRSn(x, n).U)
 394 #define HW_AXBS_CRSn_WR(x, n, v) (HW_AXBS_CRSn(x, n).U = (v))
 395 #define HW_AXBS_CRSn_SET(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) |  (v)))
 396 #define HW_AXBS_CRSn_CLR(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) & ~(v)))
 397 #define HW_AXBS_CRSn_TOG(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) ^  (v)))
 398 /*@}*/
 399
 400 /*
 401  * Constants & macros for individual AXBS_CRSn bitfields
 402  */
 403
 404 /*!
 405  * @name Register AXBS_CRSn, field PARK[2:0] (RW)
 406  *
 407  * Determines which master port the current slave port parks on when no masters
 408  * are actively making requests and the PCTL bits are cleared. Select only master
 409  * ports that are present on the chip. Otherwise, undefined behavior might occur.
 410  *
 411  * Values:
 412  * - 000 - Park on master port M0
 413  * - 001 - Park on master port M1
 414  * - 010 - Park on master port M2
 415  * - 011 - Park on master port M3
 416  * - 100 - Park on master port M4
 417  * - 101 - Park on master port M5
 418  * - 110 - Park on master port M6
 419  * - 111 - Park on master port M7
 420  */
 421 /*@{*/
 422 #define BP_AXBS_CRSn_PARK    (0U)          /*!< Bit position for AXBS_CRSn_PARK. */
 423 #define BM_AXBS_CRSn_PARK    (0x00000007U) /*!< Bit mask for AXBS_CRSn_PARK. */
 424 #define BS_AXBS_CRSn_PARK    (3U)          /*!< Bit field size in bits for AXBS_CRSn_PARK. */
 425
 426 /*! @brief Read current value of the AXBS_CRSn_PARK field. */
 427 #define BR_AXBS_CRSn_PARK(x, n) (HW_AXBS_CRSn(x, n).B.PARK)
 428
 429 /*! @brief Format value for bitfield AXBS_CRSn_PARK. */
 430 #define BF_AXBS_CRSn_PARK(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PARK) & BM_AXBS_CRSn_PARK)
 431
 432 /*! @brief Set the PARK field to a new value. */
 433 #define BW_AXBS_CRSn_PARK(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
 434 /*@}*/
 435
 436 /*!
 437  * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
 438  *
 439  * Determines the slave port's parking control. The low-power park feature
 440  * results in an overall power savings if the slave port is not saturated. However,
 441  * this forces an extra latency clock when any master tries to access the slave
 442  * port while not in use because it is not parked on any master.
 443  *
 444  * Values:
 445  * - 00 - When no master makes a request, the arbiter parks the slave port on
 446  *     the master port defined by the PARK field
 447  * - 01 - When no master makes a request, the arbiter parks the slave port on
 448  *     the last master to be in control of the slave port
 449  * - 10 - When no master makes a request, the slave port is not parked on a
 450  *     master and the arbiter drives all outputs to a constant safe state
 451  * - 11 - Reserved
 452  */
 453 /*@{*/
 454 #define BP_AXBS_CRSn_PCTL    (4U)          /*!< Bit position for AXBS_CRSn_PCTL. */
 455 #define BM_AXBS_CRSn_PCTL    (0x00000030U) /*!< Bit mask for AXBS_CRSn_PCTL. */
 456 #define BS_AXBS_CRSn_PCTL    (2U)          /*!< Bit field size in bits for AXBS_CRSn_PCTL. */
 457
 458 /*! @brief Read current value of the AXBS_CRSn_PCTL field. */
 459 #define BR_AXBS_CRSn_PCTL(x, n) (HW_AXBS_CRSn(x, n).B.PCTL)
 460
 461 /*! @brief Format value for bitfield AXBS_CRSn_PCTL. */
 462 #define BF_AXBS_CRSn_PCTL(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PCTL) & BM_AXBS_CRSn_PCTL)
 463
 464 /*! @brief Set the PCTL field to a new value. */
 465 #define BW_AXBS_CRSn_PCTL(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
 466 /*@}*/
 467
 468 /*!
 469  * @name Register AXBS_CRSn, field ARB[9:8] (RW)
 470  *
 471  * Selects the arbitration policy for the slave port.
 472  *
 473  * Values:
 474  * - 00 - Fixed priority
 475  * - 01 - Round-robin, or rotating, priority
 476  * - 10 - Reserved
 477  * - 11 - Reserved
 478  */
 479 /*@{*/
 480 #define BP_AXBS_CRSn_ARB     (8U)          /*!< Bit position for AXBS_CRSn_ARB. */
 481 #define BM_AXBS_CRSn_ARB     (0x00000300U) /*!< Bit mask for AXBS_CRSn_ARB. */
 482 #define BS_AXBS_CRSn_ARB     (2U)          /*!< Bit field size in bits for AXBS_CRSn_ARB. */
 483
 484 /*! @brief Read current value of the AXBS_CRSn_ARB field. */
 485 #define BR_AXBS_CRSn_ARB(x, n) (HW_AXBS_CRSn(x, n).B.ARB)
 486
 487 /*! @brief Format value for bitfield AXBS_CRSn_ARB. */
 488 #define BF_AXBS_CRSn_ARB(v)  ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_ARB) & BM_AXBS_CRSn_ARB)
 489
 490 /*! @brief Set the ARB field to a new value. */
 491 #define BW_AXBS_CRSn_ARB(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
 492 /*@}*/
 493
 494 /*!
 495  * @name Register AXBS_CRSn, field HLP[30] (RW)
 496  *
 497  * Sets the initial arbitration priority for low power mode requests . Setting
 498  * this bit will not affect the request for low power mode from attaining highest
 499  * priority once it has control of the slave ports.
 500  *
 501  * Values:
 502  * - 0 - The low power mode request has the highest priority for arbitration on
 503  *     this slave port
 504  * - 1 - The low power mode request has the lowest initial priority for
 505  *     arbitration on this slave port
 506  */
 507 /*@{*/
 508 #define BP_AXBS_CRSn_HLP     (30U)         /*!< Bit position for AXBS_CRSn_HLP. */
 509 #define BM_AXBS_CRSn_HLP     (0x40000000U) /*!< Bit mask for AXBS_CRSn_HLP. */
 510 #define BS_AXBS_CRSn_HLP     (1U)          /*!< Bit field size in bits for AXBS_CRSn_HLP. */
 511
 512 /*! @brief Read current value of the AXBS_CRSn_HLP field. */
 513 #define BR_AXBS_CRSn_HLP(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP))
 514
 515 /*! @brief Format value for bitfield AXBS_CRSn_HLP. */
 516 #define BF_AXBS_CRSn_HLP(v)  ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_HLP) & BM_AXBS_CRSn_HLP)
 517
 518 /*! @brief Set the HLP field to a new value. */
 519 #define BW_AXBS_CRSn_HLP(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP) = (v))
 520 /*@}*/
 521
 522 /*!
 523  * @name Register AXBS_CRSn, field RO[31] (RW)
 524  *
 525  * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
 526  * only a hardware reset clears it.
 527  *
 528  * Values:
 529  * - 0 - The slave port's registers are writeable
 530  * - 1 - The slave port's registers are read-only and cannot be written.
 531  *     Attempted writes have no effect on the registers and result in a bus error
 532  *     response.
 533  */
 534 /*@{*/
 535 #define BP_AXBS_CRSn_RO      (31U)         /*!< Bit position for AXBS_CRSn_RO. */
 536 #define BM_AXBS_CRSn_RO      (0x80000000U) /*!< Bit mask for AXBS_CRSn_RO. */
 537 #define BS_AXBS_CRSn_RO      (1U)          /*!< Bit field size in bits for AXBS_CRSn_RO. */
 538
 539 /*! @brief Read current value of the AXBS_CRSn_RO field. */
 540 #define BR_AXBS_CRSn_RO(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO))
 541
 542 /*! @brief Format value for bitfield AXBS_CRSn_RO. */
 543 #define BF_AXBS_CRSn_RO(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_RO) & BM_AXBS_CRSn_RO)
 544
 545 /*! @brief Set the RO field to a new value. */
 546 #define BW_AXBS_CRSn_RO(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO) = (v))
 547 /*@}*/
 548
 549 /*******************************************************************************
 550  * HW_AXBS_MGPCR0 - Master General Purpose Control Register
 551  ******************************************************************************/
 552
 553 /*!
 554  * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
 555  *
 556  * Reset value: 0x00000000U
 557  *
 558  * The MGPCR controls only whether the master's undefined length burst accesses
 559  * are allowed to complete uninterrupted or whether they can be broken by
 560  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
 561  * mode with 32-bit accesses.
 562  */
 563 typedef union _hw_axbs_mgpcr0
 564 {
 565     uint32_t U;
 566     struct _hw_axbs_mgpcr0_bitfields
 567     {
 568         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
 569         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 570     } B;
 571 } hw_axbs_mgpcr0_t;
 572
 573 /*!
 574  * @name Constants and macros for entire AXBS_MGPCR0 register
 575  */
 576 /*@{*/
 577 #define HW_AXBS_MGPCR0_ADDR(x)   ((x) + 0x800U)
 578
 579 #define HW_AXBS_MGPCR0(x)        (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR(x))
 580 #define HW_AXBS_MGPCR0_RD(x)     (HW_AXBS_MGPCR0(x).U)
 581 #define HW_AXBS_MGPCR0_WR(x, v)  (HW_AXBS_MGPCR0(x).U = (v))
 582 #define HW_AXBS_MGPCR0_SET(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) |  (v)))
 583 #define HW_AXBS_MGPCR0_CLR(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) & ~(v)))
 584 #define HW_AXBS_MGPCR0_TOG(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) ^  (v)))
 585 /*@}*/
 586
 587 /*
 588  * Constants & macros for individual AXBS_MGPCR0 bitfields
 589  */
 590
 591 /*!
 592  * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
 593  *
 594  * Determines whether, and when, the crossbar switch arbitrates away the slave
 595  * port the master owns when the master is performing undefined length burst
 596  * accesses.
 597  *
 598  * Values:
 599  * - 000 - No arbitration is allowed during an undefined length burst
 600  * - 001 - Arbitration is allowed at any time during an undefined length burst
 601  * - 010 - Arbitration is allowed after four beats of an undefined length burst
 602  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
 603  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
 604  * - 101 - Reserved
 605  * - 110 - Reserved
 606  * - 111 - Reserved
 607  */
 608 /*@{*/
 609 #define BP_AXBS_MGPCR0_AULB  (0U)          /*!< Bit position for AXBS_MGPCR0_AULB. */
 610 #define BM_AXBS_MGPCR0_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR0_AULB. */
 611 #define BS_AXBS_MGPCR0_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR0_AULB. */
 612
 613 /*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
 614 #define BR_AXBS_MGPCR0_AULB(x) (HW_AXBS_MGPCR0(x).B.AULB)
 615
 616 /*! @brief Format value for bitfield AXBS_MGPCR0_AULB. */
 617 #define BF_AXBS_MGPCR0_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR0_AULB) & BM_AXBS_MGPCR0_AULB)
 618
 619 /*! @brief Set the AULB field to a new value. */
 620 #define BW_AXBS_MGPCR0_AULB(x, v) (HW_AXBS_MGPCR0_WR(x, (HW_AXBS_MGPCR0_RD(x) & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
 621 /*@}*/
 622
 623 /*******************************************************************************
 624  * HW_AXBS_MGPCR1 - Master General Purpose Control Register
 625  ******************************************************************************/
 626
 627 /*!
 628  * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
 629  *
 630  * Reset value: 0x00000000U
 631  *
 632  * The MGPCR controls only whether the master's undefined length burst accesses
 633  * are allowed to complete uninterrupted or whether they can be broken by
 634  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
 635  * mode with 32-bit accesses.
 636  */
 637 typedef union _hw_axbs_mgpcr1
 638 {
 639     uint32_t U;
 640     struct _hw_axbs_mgpcr1_bitfields
 641     {
 642         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
 643         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 644     } B;
 645 } hw_axbs_mgpcr1_t;
 646
 647 /*!
 648  * @name Constants and macros for entire AXBS_MGPCR1 register
 649  */
 650 /*@{*/
 651 #define HW_AXBS_MGPCR1_ADDR(x)   ((x) + 0x900U)
 652
 653 #define HW_AXBS_MGPCR1(x)        (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR(x))
 654 #define HW_AXBS_MGPCR1_RD(x)     (HW_AXBS_MGPCR1(x).U)
 655 #define HW_AXBS_MGPCR1_WR(x, v)  (HW_AXBS_MGPCR1(x).U = (v))
 656 #define HW_AXBS_MGPCR1_SET(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) |  (v)))
 657 #define HW_AXBS_MGPCR1_CLR(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) & ~(v)))
 658 #define HW_AXBS_MGPCR1_TOG(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) ^  (v)))
 659 /*@}*/
 660
 661 /*
 662  * Constants & macros for individual AXBS_MGPCR1 bitfields
 663  */
 664
 665 /*!
 666  * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
 667  *
 668  * Determines whether, and when, the crossbar switch arbitrates away the slave
 669  * port the master owns when the master is performing undefined length burst
 670  * accesses.
 671  *
 672  * Values:
 673  * - 000 - No arbitration is allowed during an undefined length burst
 674  * - 001 - Arbitration is allowed at any time during an undefined length burst
 675  * - 010 - Arbitration is allowed after four beats of an undefined length burst
 676  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
 677  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
 678  * - 101 - Reserved
 679  * - 110 - Reserved
 680  * - 111 - Reserved
 681  */
 682 /*@{*/
 683 #define BP_AXBS_MGPCR1_AULB  (0U)          /*!< Bit position for AXBS_MGPCR1_AULB. */
 684 #define BM_AXBS_MGPCR1_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR1_AULB. */
 685 #define BS_AXBS_MGPCR1_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR1_AULB. */
 686
 687 /*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
 688 #define BR_AXBS_MGPCR1_AULB(x) (HW_AXBS_MGPCR1(x).B.AULB)
 689
 690 /*! @brief Format value for bitfield AXBS_MGPCR1_AULB. */
 691 #define BF_AXBS_MGPCR1_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR1_AULB) & BM_AXBS_MGPCR1_AULB)
 692
 693 /*! @brief Set the AULB field to a new value. */
 694 #define BW_AXBS_MGPCR1_AULB(x, v) (HW_AXBS_MGPCR1_WR(x, (HW_AXBS_MGPCR1_RD(x) & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
 695 /*@}*/
 696
 697 /*******************************************************************************
 698  * HW_AXBS_MGPCR2 - Master General Purpose Control Register
 699  ******************************************************************************/
 700
 701 /*!
 702  * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
 703  *
 704  * Reset value: 0x00000000U
 705  *
 706  * The MGPCR controls only whether the master's undefined length burst accesses
 707  * are allowed to complete uninterrupted or whether they can be broken by
 708  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
 709  * mode with 32-bit accesses.
 710  */
 711 typedef union _hw_axbs_mgpcr2
 712 {
 713     uint32_t U;
 714     struct _hw_axbs_mgpcr2_bitfields
 715     {
 716         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
 717         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 718     } B;
 719 } hw_axbs_mgpcr2_t;
 720
 721 /*!
 722  * @name Constants and macros for entire AXBS_MGPCR2 register
 723  */
 724 /*@{*/
 725 #define HW_AXBS_MGPCR2_ADDR(x)   ((x) + 0xA00U)
 726
 727 #define HW_AXBS_MGPCR2(x)        (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR(x))
 728 #define HW_AXBS_MGPCR2_RD(x)     (HW_AXBS_MGPCR2(x).U)
 729 #define HW_AXBS_MGPCR2_WR(x, v)  (HW_AXBS_MGPCR2(x).U = (v))
 730 #define HW_AXBS_MGPCR2_SET(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) |  (v)))
 731 #define HW_AXBS_MGPCR2_CLR(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) & ~(v)))
 732 #define HW_AXBS_MGPCR2_TOG(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) ^  (v)))
 733 /*@}*/
 734
 735 /*
 736  * Constants & macros for individual AXBS_MGPCR2 bitfields
 737  */
 738
 739 /*!
 740  * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
 741  *
 742  * Determines whether, and when, the crossbar switch arbitrates away the slave
 743  * port the master owns when the master is performing undefined length burst
 744  * accesses.
 745  *
 746  * Values:
 747  * - 000 - No arbitration is allowed during an undefined length burst
 748  * - 001 - Arbitration is allowed at any time during an undefined length burst
 749  * - 010 - Arbitration is allowed after four beats of an undefined length burst
 750  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
 751  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
 752  * - 101 - Reserved
 753  * - 110 - Reserved
 754  * - 111 - Reserved
 755  */
 756 /*@{*/
 757 #define BP_AXBS_MGPCR2_AULB  (0U)          /*!< Bit position for AXBS_MGPCR2_AULB. */
 758 #define BM_AXBS_MGPCR2_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR2_AULB. */
 759 #define BS_AXBS_MGPCR2_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR2_AULB. */
 760
 761 /*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
 762 #define BR_AXBS_MGPCR2_AULB(x) (HW_AXBS_MGPCR2(x).B.AULB)
 763
 764 /*! @brief Format value for bitfield AXBS_MGPCR2_AULB. */
 765 #define BF_AXBS_MGPCR2_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR2_AULB) & BM_AXBS_MGPCR2_AULB)
 766
 767 /*! @brief Set the AULB field to a new value. */
 768 #define BW_AXBS_MGPCR2_AULB(x, v) (HW_AXBS_MGPCR2_WR(x, (HW_AXBS_MGPCR2_RD(x) & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
 769 /*@}*/
 770
 771 /*******************************************************************************
 772  * HW_AXBS_MGPCR3 - Master General Purpose Control Register
 773  ******************************************************************************/
 774
 775 /*!
 776  * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
 777  *
 778  * Reset value: 0x00000000U
 779  *
 780  * The MGPCR controls only whether the master's undefined length burst accesses
 781  * are allowed to complete uninterrupted or whether they can be broken by
 782  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
 783  * mode with 32-bit accesses.
 784  */
 785 typedef union _hw_axbs_mgpcr3
 786 {
 787     uint32_t U;
 788     struct _hw_axbs_mgpcr3_bitfields
 789     {
 790         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
 791         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 792     } B;
 793 } hw_axbs_mgpcr3_t;
 794
 795 /*!
 796  * @name Constants and macros for entire AXBS_MGPCR3 register
 797  */
 798 /*@{*/
 799 #define HW_AXBS_MGPCR3_ADDR(x)   ((x) + 0xB00U)
 800
 801 #define HW_AXBS_MGPCR3(x)        (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR(x))
 802 #define HW_AXBS_MGPCR3_RD(x)     (HW_AXBS_MGPCR3(x).U)
 803 #define HW_AXBS_MGPCR3_WR(x, v)  (HW_AXBS_MGPCR3(x).U = (v))
 804 #define HW_AXBS_MGPCR3_SET(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) |  (v)))
 805 #define HW_AXBS_MGPCR3_CLR(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) & ~(v)))
 806 #define HW_AXBS_MGPCR3_TOG(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) ^  (v)))
 807 /*@}*/
 808
 809 /*
 810  * Constants & macros for individual AXBS_MGPCR3 bitfields
 811  */
 812
 813 /*!
 814  * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
 815  *
 816  * Determines whether, and when, the crossbar switch arbitrates away the slave
 817  * port the master owns when the master is performing undefined length burst
 818  * accesses.
 819  *
 820  * Values:
 821  * - 000 - No arbitration is allowed during an undefined length burst
 822  * - 001 - Arbitration is allowed at any time during an undefined length burst
 823  * - 010 - Arbitration is allowed after four beats of an undefined length burst
 824  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
 825  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
 826  * - 101 - Reserved
 827  * - 110 - Reserved
 828  * - 111 - Reserved
 829  */
 830 /*@{*/
 831 #define BP_AXBS_MGPCR3_AULB  (0U)          /*!< Bit position for AXBS_MGPCR3_AULB. */
 832 #define BM_AXBS_MGPCR3_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR3_AULB. */
 833 #define BS_AXBS_MGPCR3_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR3_AULB. */
 834
 835 /*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
 836 #define BR_AXBS_MGPCR3_AULB(x) (HW_AXBS_MGPCR3(x).B.AULB)
 837
 838 /*! @brief Format value for bitfield AXBS_MGPCR3_AULB. */
 839 #define BF_AXBS_MGPCR3_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR3_AULB) & BM_AXBS_MGPCR3_AULB)
 840
 841 /*! @brief Set the AULB field to a new value. */
 842 #define BW_AXBS_MGPCR3_AULB(x, v) (HW_AXBS_MGPCR3_WR(x, (HW_AXBS_MGPCR3_RD(x) & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
 843 /*@}*/
 844
 845 /*******************************************************************************
 846  * HW_AXBS_MGPCR4 - Master General Purpose Control Register
 847  ******************************************************************************/
 848
 849 /*!
 850  * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
 851  *
 852  * Reset value: 0x00000000U
 853  *
 854  * The MGPCR controls only whether the master's undefined length burst accesses
 855  * are allowed to complete uninterrupted or whether they can be broken by
 856  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
 857  * mode with 32-bit accesses.
 858  */
 859 typedef union _hw_axbs_mgpcr4
 860 {
 861     uint32_t U;
 862     struct _hw_axbs_mgpcr4_bitfields
 863     {
 864         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
 865         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 866     } B;
 867 } hw_axbs_mgpcr4_t;
 868
 869 /*!
 870  * @name Constants and macros for entire AXBS_MGPCR4 register
 871  */
 872 /*@{*/
 873 #define HW_AXBS_MGPCR4_ADDR(x)   ((x) + 0xC00U)
 874
 875 #define HW_AXBS_MGPCR4(x)        (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR(x))
 876 #define HW_AXBS_MGPCR4_RD(x)     (HW_AXBS_MGPCR4(x).U)
 877 #define HW_AXBS_MGPCR4_WR(x, v)  (HW_AXBS_MGPCR4(x).U = (v))
 878 #define HW_AXBS_MGPCR4_SET(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) |  (v)))
 879 #define HW_AXBS_MGPCR4_CLR(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) & ~(v)))
 880 #define HW_AXBS_MGPCR4_TOG(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) ^  (v)))
 881 /*@}*/
 882
 883 /*
 884  * Constants & macros for individual AXBS_MGPCR4 bitfields
 885  */
 886
 887 /*!
 888  * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
 889  *
 890  * Determines whether, and when, the crossbar switch arbitrates away the slave
 891  * port the master owns when the master is performing undefined length burst
 892  * accesses.
 893  *
 894  * Values:
 895  * - 000 - No arbitration is allowed during an undefined length burst
 896  * - 001 - Arbitration is allowed at any time during an undefined length burst
 897  * - 010 - Arbitration is allowed after four beats of an undefined length burst
 898  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
 899  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
 900  * - 101 - Reserved
 901  * - 110 - Reserved
 902  * - 111 - Reserved
 903  */
 904 /*@{*/
 905 #define BP_AXBS_MGPCR4_AULB  (0U)          /*!< Bit position for AXBS_MGPCR4_AULB. */
 906 #define BM_AXBS_MGPCR4_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR4_AULB. */
 907 #define BS_AXBS_MGPCR4_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR4_AULB. */
 908
 909 /*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
 910 #define BR_AXBS_MGPCR4_AULB(x) (HW_AXBS_MGPCR4(x).B.AULB)
 911
 912 /*! @brief Format value for bitfield AXBS_MGPCR4_AULB. */
 913 #define BF_AXBS_MGPCR4_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR4_AULB) & BM_AXBS_MGPCR4_AULB)
 914
 915 /*! @brief Set the AULB field to a new value. */
 916 #define BW_AXBS_MGPCR4_AULB(x, v) (HW_AXBS_MGPCR4_WR(x, (HW_AXBS_MGPCR4_RD(x) & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
 917 /*@}*/
 918
 919 /*******************************************************************************
 920  * HW_AXBS_MGPCR5 - Master General Purpose Control Register
 921  ******************************************************************************/
 922
 923 /*!
 924  * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
 925  *
 926  * Reset value: 0x00000000U
 927  *
 928  * The MGPCR controls only whether the master's undefined length burst accesses
 929  * are allowed to complete uninterrupted or whether they can be broken by
 930  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
 931  * mode with 32-bit accesses.
 932  */
 933 typedef union _hw_axbs_mgpcr5
 934 {
 935     uint32_t U;
 936     struct _hw_axbs_mgpcr5_bitfields
 937     {
 938         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
 939         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 940     } B;
 941 } hw_axbs_mgpcr5_t;
 942
 943 /*!
 944  * @name Constants and macros for entire AXBS_MGPCR5 register
 945  */
 946 /*@{*/
 947 #define HW_AXBS_MGPCR5_ADDR(x)   ((x) + 0xD00U)
 948
 949 #define HW_AXBS_MGPCR5(x)        (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR(x))
 950 #define HW_AXBS_MGPCR5_RD(x)     (HW_AXBS_MGPCR5(x).U)
 951 #define HW_AXBS_MGPCR5_WR(x, v)  (HW_AXBS_MGPCR5(x).U = (v))
 952 #define HW_AXBS_MGPCR5_SET(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) |  (v)))
 953 #define HW_AXBS_MGPCR5_CLR(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) & ~(v)))
 954 #define HW_AXBS_MGPCR5_TOG(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) ^  (v)))
 955 /*@}*/
 956
 957 /*
 958  * Constants & macros for individual AXBS_MGPCR5 bitfields
 959  */
 960
 961 /*!
 962  * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
 963  *
 964  * Determines whether, and when, the crossbar switch arbitrates away the slave
 965  * port the master owns when the master is performing undefined length burst
 966  * accesses.
 967  *
 968  * Values:
 969  * - 000 - No arbitration is allowed during an undefined length burst
 970  * - 001 - Arbitration is allowed at any time during an undefined length burst
 971  * - 010 - Arbitration is allowed after four beats of an undefined length burst
 972  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
 973  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
 974  * - 101 - Reserved
 975  * - 110 - Reserved
 976  * - 111 - Reserved
 977  */
 978 /*@{*/
 979 #define BP_AXBS_MGPCR5_AULB  (0U)          /*!< Bit position for AXBS_MGPCR5_AULB. */
 980 #define BM_AXBS_MGPCR5_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR5_AULB. */
 981 #define BS_AXBS_MGPCR5_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR5_AULB. */
 982
 983 /*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
 984 #define BR_AXBS_MGPCR5_AULB(x) (HW_AXBS_MGPCR5(x).B.AULB)
 985
 986 /*! @brief Format value for bitfield AXBS_MGPCR5_AULB. */
 987 #define BF_AXBS_MGPCR5_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR5_AULB) & BM_AXBS_MGPCR5_AULB)
 988
 989 /*! @brief Set the AULB field to a new value. */
 990 #define BW_AXBS_MGPCR5_AULB(x, v) (HW_AXBS_MGPCR5_WR(x, (HW_AXBS_MGPCR5_RD(x) & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
 991 /*@}*/
 992
 993 /*******************************************************************************
 994  * hw_axbs_t - module struct
 995  ******************************************************************************/
 996 /*!
 997  * @brief All AXBS module registers.
 998  */
 999 #pragma pack(1)
1000 typedef struct _hw_axbs
1001 {
1002     struct {
1003         __IO hw_axbs_prsn_t PRSn;          /*!< [0x0] Priority Registers Slave */
1004         uint8_t _reserved0[12];
1005         __IO hw_axbs_crsn_t CRSn;          /*!< [0x10] Control Register */
1006         uint8_t _reserved1[236];
1007     } SLAVE[5];
1008     uint8_t _reserved0[768];
1009     __IO hw_axbs_mgpcr0_t MGPCR0;          /*!< [0x800] Master General Purpose Control Register */
1010     uint8_t _reserved1[252];
1011     __IO hw_axbs_mgpcr1_t MGPCR1;          /*!< [0x900] Master General Purpose Control Register */
1012     uint8_t _reserved2[252];
1013     __IO hw_axbs_mgpcr2_t MGPCR2;          /*!< [0xA00] Master General Purpose Control Register */
1014     uint8_t _reserved3[252];
1015     __IO hw_axbs_mgpcr3_t MGPCR3;          /*!< [0xB00] Master General Purpose Control Register */
1016     uint8_t _reserved4[252];
1017     __IO hw_axbs_mgpcr4_t MGPCR4;          /*!< [0xC00] Master General Purpose Control Register */
1018     uint8_t _reserved5[252];
1019     __IO hw_axbs_mgpcr5_t MGPCR5;          /*!< [0xD00] Master General Purpose Control Register */
1020 } hw_axbs_t;
1021 #pragma pack()
1022
1023 /*! @brief Macro to access all AXBS registers. */
1024 /*! @param x AXBS module instance base address. */
1025 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1026  *     use the '&' operator, like <code>&HW_AXBS(AXBS_BASE)</code>. */
1027 #define HW_AXBS(x)     (*(hw_axbs_t *)(x))
1028
1029 #endif /* __HW_AXBS_REGISTERS_H__ */
1030 /* EOF */