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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2s.h
2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_I2S_REGISTERS_H__
81 #define __HW_I2S_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Inter-IC Sound / Synchronous Audio Interface
91 * Registers defined in this header file:
92 * - HW_I2S_TCSR - SAI Transmit Control Register
93 * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
94 * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
95 * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
96 * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
97 * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
98 * - HW_I2S_TDRn - SAI Transmit Data Register
99 * - HW_I2S_TFRn - SAI Transmit FIFO Register
100 * - HW_I2S_TMR - SAI Transmit Mask Register
101 * - HW_I2S_RCSR - SAI Receive Control Register
102 * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
103 * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
104 * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
105 * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
106 * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
107 * - HW_I2S_RDRn - SAI Receive Data Register
108 * - HW_I2S_RFRn - SAI Receive FIFO Register
109 * - HW_I2S_RMR - SAI Receive Mask Register
110 * - HW_I2S_MCR - SAI MCLK Control Register
111 * - HW_I2S_MDR - SAI MCLK Divide Register
113 * - hw_i2s_t - Struct containing all module registers.
116 #define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
118 /*******************************************************************************
119 * HW_I2S_TCSR - SAI Transmit Control Register
120 ******************************************************************************/
123 * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
125 * Reset value: 0x00000000U
127 typedef union _hw_i2s_tcsr
130 struct _hw_i2s_tcsr_bitfields
132 uint32_t FRDE
: 1; /*!< [0] FIFO Request DMA Enable */
133 uint32_t FWDE
: 1; /*!< [1] FIFO Warning DMA Enable */
134 uint32_t RESERVED0
: 6; /*!< [7:2] */
135 uint32_t FRIE
: 1; /*!< [8] FIFO Request Interrupt Enable */
136 uint32_t FWIE
: 1; /*!< [9] FIFO Warning Interrupt Enable */
137 uint32_t FEIE
: 1; /*!< [10] FIFO Error Interrupt Enable */
138 uint32_t SEIE
: 1; /*!< [11] Sync Error Interrupt Enable */
139 uint32_t WSIE
: 1; /*!< [12] Word Start Interrupt Enable */
140 uint32_t RESERVED1
: 3; /*!< [15:13] */
141 uint32_t FRF
: 1; /*!< [16] FIFO Request Flag */
142 uint32_t FWF
: 1; /*!< [17] FIFO Warning Flag */
143 uint32_t FEF
: 1; /*!< [18] FIFO Error Flag */
144 uint32_t SEF
: 1; /*!< [19] Sync Error Flag */
145 uint32_t WSF
: 1; /*!< [20] Word Start Flag */
146 uint32_t RESERVED2
: 3; /*!< [23:21] */
147 uint32_t SR
: 1; /*!< [24] Software Reset */
148 uint32_t FR
: 1; /*!< [25] FIFO Reset */
149 uint32_t RESERVED3
: 2; /*!< [27:26] */
150 uint32_t BCE
: 1; /*!< [28] Bit Clock Enable */
151 uint32_t DBGE
: 1; /*!< [29] Debug Enable */
152 uint32_t STOPE
: 1; /*!< [30] Stop Enable */
153 uint32_t TE
: 1; /*!< [31] Transmitter Enable */
158 * @name Constants and macros for entire I2S_TCSR register
161 #define HW_I2S_TCSR_ADDR(x) ((x) + 0x0U)
163 #define HW_I2S_TCSR(x) (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
164 #define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
165 #define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
166 #define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) | (v)))
167 #define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
168 #define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
172 * Constants & macros for individual I2S_TCSR bitfields
176 * @name Register I2S_TCSR, field FRDE[0] (RW)
178 * Enables/disables DMA requests.
181 * - 0 - Disables the DMA request.
182 * - 1 - Enables the DMA request.
185 #define BP_I2S_TCSR_FRDE (0U) /*!< Bit position for I2S_TCSR_FRDE. */
186 #define BM_I2S_TCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */
187 #define BS_I2S_TCSR_FRDE (1U) /*!< Bit field size in bits for I2S_TCSR_FRDE. */
189 /*! @brief Read current value of the I2S_TCSR_FRDE field. */
190 #define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
192 /*! @brief Format value for bitfield I2S_TCSR_FRDE. */
193 #define BF_I2S_TCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE)
195 /*! @brief Set the FRDE field to a new value. */
196 #define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
200 * @name Register I2S_TCSR, field FWDE[1] (RW)
202 * Enables/disables DMA requests.
205 * - 0 - Disables the DMA request.
206 * - 1 - Enables the DMA request.
209 #define BP_I2S_TCSR_FWDE (1U) /*!< Bit position for I2S_TCSR_FWDE. */
210 #define BM_I2S_TCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */
211 #define BS_I2S_TCSR_FWDE (1U) /*!< Bit field size in bits for I2S_TCSR_FWDE. */
213 /*! @brief Read current value of the I2S_TCSR_FWDE field. */
214 #define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
216 /*! @brief Format value for bitfield I2S_TCSR_FWDE. */
217 #define BF_I2S_TCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE)
219 /*! @brief Set the FWDE field to a new value. */
220 #define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
224 * @name Register I2S_TCSR, field FRIE[8] (RW)
226 * Enables/disables FIFO request interrupts.
229 * - 0 - Disables the interrupt.
230 * - 1 - Enables the interrupt.
233 #define BP_I2S_TCSR_FRIE (8U) /*!< Bit position for I2S_TCSR_FRIE. */
234 #define BM_I2S_TCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */
235 #define BS_I2S_TCSR_FRIE (1U) /*!< Bit field size in bits for I2S_TCSR_FRIE. */
237 /*! @brief Read current value of the I2S_TCSR_FRIE field. */
238 #define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
240 /*! @brief Format value for bitfield I2S_TCSR_FRIE. */
241 #define BF_I2S_TCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE)
243 /*! @brief Set the FRIE field to a new value. */
244 #define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
248 * @name Register I2S_TCSR, field FWIE[9] (RW)
250 * Enables/disables FIFO warning interrupts.
253 * - 0 - Disables the interrupt.
254 * - 1 - Enables the interrupt.
257 #define BP_I2S_TCSR_FWIE (9U) /*!< Bit position for I2S_TCSR_FWIE. */
258 #define BM_I2S_TCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */
259 #define BS_I2S_TCSR_FWIE (1U) /*!< Bit field size in bits for I2S_TCSR_FWIE. */
261 /*! @brief Read current value of the I2S_TCSR_FWIE field. */
262 #define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
264 /*! @brief Format value for bitfield I2S_TCSR_FWIE. */
265 #define BF_I2S_TCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE)
267 /*! @brief Set the FWIE field to a new value. */
268 #define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
272 * @name Register I2S_TCSR, field FEIE[10] (RW)
274 * Enables/disables FIFO error interrupts.
277 * - 0 - Disables the interrupt.
278 * - 1 - Enables the interrupt.
281 #define BP_I2S_TCSR_FEIE (10U) /*!< Bit position for I2S_TCSR_FEIE. */
282 #define BM_I2S_TCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */
283 #define BS_I2S_TCSR_FEIE (1U) /*!< Bit field size in bits for I2S_TCSR_FEIE. */
285 /*! @brief Read current value of the I2S_TCSR_FEIE field. */
286 #define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
288 /*! @brief Format value for bitfield I2S_TCSR_FEIE. */
289 #define BF_I2S_TCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE)
291 /*! @brief Set the FEIE field to a new value. */
292 #define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
296 * @name Register I2S_TCSR, field SEIE[11] (RW)
298 * Enables/disables sync error interrupts.
301 * - 0 - Disables interrupt.
302 * - 1 - Enables interrupt.
305 #define BP_I2S_TCSR_SEIE (11U) /*!< Bit position for I2S_TCSR_SEIE. */
306 #define BM_I2S_TCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */
307 #define BS_I2S_TCSR_SEIE (1U) /*!< Bit field size in bits for I2S_TCSR_SEIE. */
309 /*! @brief Read current value of the I2S_TCSR_SEIE field. */
310 #define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
312 /*! @brief Format value for bitfield I2S_TCSR_SEIE. */
313 #define BF_I2S_TCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE)
315 /*! @brief Set the SEIE field to a new value. */
316 #define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
320 * @name Register I2S_TCSR, field WSIE[12] (RW)
322 * Enables/disables word start interrupts.
325 * - 0 - Disables interrupt.
326 * - 1 - Enables interrupt.
329 #define BP_I2S_TCSR_WSIE (12U) /*!< Bit position for I2S_TCSR_WSIE. */
330 #define BM_I2S_TCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */
331 #define BS_I2S_TCSR_WSIE (1U) /*!< Bit field size in bits for I2S_TCSR_WSIE. */
333 /*! @brief Read current value of the I2S_TCSR_WSIE field. */
334 #define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
336 /*! @brief Format value for bitfield I2S_TCSR_WSIE. */
337 #define BF_I2S_TCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE)
339 /*! @brief Set the WSIE field to a new value. */
340 #define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
344 * @name Register I2S_TCSR, field FRF[16] (RO)
346 * Indicates that the number of words in an enabled transmit channel FIFO is
347 * less than or equal to the transmit FIFO watermark.
350 * - 0 - Transmit FIFO watermark has not been reached.
351 * - 1 - Transmit FIFO watermark has been reached.
354 #define BP_I2S_TCSR_FRF (16U) /*!< Bit position for I2S_TCSR_FRF. */
355 #define BM_I2S_TCSR_FRF (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */
356 #define BS_I2S_TCSR_FRF (1U) /*!< Bit field size in bits for I2S_TCSR_FRF. */
358 /*! @brief Read current value of the I2S_TCSR_FRF field. */
359 #define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
363 * @name Register I2S_TCSR, field FWF[17] (RO)
365 * Indicates that an enabled transmit FIFO is empty.
368 * - 0 - No enabled transmit FIFO is empty.
369 * - 1 - Enabled transmit FIFO is empty.
372 #define BP_I2S_TCSR_FWF (17U) /*!< Bit position for I2S_TCSR_FWF. */
373 #define BM_I2S_TCSR_FWF (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */
374 #define BS_I2S_TCSR_FWF (1U) /*!< Bit field size in bits for I2S_TCSR_FWF. */
376 /*! @brief Read current value of the I2S_TCSR_FWF field. */
377 #define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
381 * @name Register I2S_TCSR, field FEF[18] (W1C)
383 * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
384 * field to clear this flag.
387 * - 0 - Transmit underrun not detected.
388 * - 1 - Transmit underrun detected.
391 #define BP_I2S_TCSR_FEF (18U) /*!< Bit position for I2S_TCSR_FEF. */
392 #define BM_I2S_TCSR_FEF (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */
393 #define BS_I2S_TCSR_FEF (1U) /*!< Bit field size in bits for I2S_TCSR_FEF. */
395 /*! @brief Read current value of the I2S_TCSR_FEF field. */
396 #define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
398 /*! @brief Format value for bitfield I2S_TCSR_FEF. */
399 #define BF_I2S_TCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF)
401 /*! @brief Set the FEF field to a new value. */
402 #define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
406 * @name Register I2S_TCSR, field SEF[19] (W1C)
408 * Indicates that an error in the externally-generated frame sync has been
409 * detected. Write a logic 1 to this field to clear this flag.
412 * - 0 - Sync error not detected.
413 * - 1 - Frame sync error detected.
416 #define BP_I2S_TCSR_SEF (19U) /*!< Bit position for I2S_TCSR_SEF. */
417 #define BM_I2S_TCSR_SEF (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */
418 #define BS_I2S_TCSR_SEF (1U) /*!< Bit field size in bits for I2S_TCSR_SEF. */
420 /*! @brief Read current value of the I2S_TCSR_SEF field. */
421 #define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
423 /*! @brief Format value for bitfield I2S_TCSR_SEF. */
424 #define BF_I2S_TCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF)
426 /*! @brief Set the SEF field to a new value. */
427 #define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
431 * @name Register I2S_TCSR, field WSF[20] (W1C)
433 * Indicates that the start of the configured word has been detected. Write a
434 * logic 1 to this field to clear this flag.
437 * - 0 - Start of word not detected.
438 * - 1 - Start of word detected.
441 #define BP_I2S_TCSR_WSF (20U) /*!< Bit position for I2S_TCSR_WSF. */
442 #define BM_I2S_TCSR_WSF (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */
443 #define BS_I2S_TCSR_WSF (1U) /*!< Bit field size in bits for I2S_TCSR_WSF. */
445 /*! @brief Read current value of the I2S_TCSR_WSF field. */
446 #define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
448 /*! @brief Format value for bitfield I2S_TCSR_WSF. */
449 #define BF_I2S_TCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF)
451 /*! @brief Set the WSF field to a new value. */
452 #define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
456 * @name Register I2S_TCSR, field SR[24] (RW)
458 * When set, resets the internal transmitter logic including the FIFO pointers.
459 * Software-visible registers are not affected, except for the status registers.
463 * - 1 - Software reset.
466 #define BP_I2S_TCSR_SR (24U) /*!< Bit position for I2S_TCSR_SR. */
467 #define BM_I2S_TCSR_SR (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */
468 #define BS_I2S_TCSR_SR (1U) /*!< Bit field size in bits for I2S_TCSR_SR. */
470 /*! @brief Read current value of the I2S_TCSR_SR field. */
471 #define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
473 /*! @brief Format value for bitfield I2S_TCSR_SR. */
474 #define BF_I2S_TCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR)
476 /*! @brief Set the SR field to a new value. */
477 #define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
481 * @name Register I2S_TCSR, field FR[25] (WORZ)
483 * Resets the FIFO pointers. Reading this field will always return zero. FIFO
484 * pointers should only be reset when the transmitter is disabled or the FIFO error
492 #define BP_I2S_TCSR_FR (25U) /*!< Bit position for I2S_TCSR_FR. */
493 #define BM_I2S_TCSR_FR (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */
494 #define BS_I2S_TCSR_FR (1U) /*!< Bit field size in bits for I2S_TCSR_FR. */
496 /*! @brief Format value for bitfield I2S_TCSR_FR. */
497 #define BF_I2S_TCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR)
499 /*! @brief Set the FR field to a new value. */
500 #define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
504 * @name Register I2S_TCSR, field BCE[28] (RW)
506 * Enables the transmit bit clock, separately from the TE. This field is
507 * automatically set whenever TE is set. When software clears this field, the transmit
508 * bit clock remains enabled, and this bit remains set, until the end of the
512 * - 0 - Transmit bit clock is disabled.
513 * - 1 - Transmit bit clock is enabled.
516 #define BP_I2S_TCSR_BCE (28U) /*!< Bit position for I2S_TCSR_BCE. */
517 #define BM_I2S_TCSR_BCE (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */
518 #define BS_I2S_TCSR_BCE (1U) /*!< Bit field size in bits for I2S_TCSR_BCE. */
520 /*! @brief Read current value of the I2S_TCSR_BCE field. */
521 #define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
523 /*! @brief Format value for bitfield I2S_TCSR_BCE. */
524 #define BF_I2S_TCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE)
526 /*! @brief Set the BCE field to a new value. */
527 #define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
531 * @name Register I2S_TCSR, field DBGE[29] (RW)
533 * Enables/disables transmitter operation in Debug mode. The transmit bit clock
534 * is not affected by debug mode.
537 * - 0 - Transmitter is disabled in Debug mode, after completing the current
539 * - 1 - Transmitter is enabled in Debug mode.
542 #define BP_I2S_TCSR_DBGE (29U) /*!< Bit position for I2S_TCSR_DBGE. */
543 #define BM_I2S_TCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */
544 #define BS_I2S_TCSR_DBGE (1U) /*!< Bit field size in bits for I2S_TCSR_DBGE. */
546 /*! @brief Read current value of the I2S_TCSR_DBGE field. */
547 #define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
549 /*! @brief Format value for bitfield I2S_TCSR_DBGE. */
550 #define BF_I2S_TCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE)
552 /*! @brief Set the DBGE field to a new value. */
553 #define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
557 * @name Register I2S_TCSR, field STOPE[30] (RW)
559 * Configures transmitter operation in Stop mode. This field is ignored and the
560 * transmitter is disabled in all low-leakage stop modes.
563 * - 0 - Transmitter disabled in Stop mode.
564 * - 1 - Transmitter enabled in Stop mode.
567 #define BP_I2S_TCSR_STOPE (30U) /*!< Bit position for I2S_TCSR_STOPE. */
568 #define BM_I2S_TCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */
569 #define BS_I2S_TCSR_STOPE (1U) /*!< Bit field size in bits for I2S_TCSR_STOPE. */
571 /*! @brief Read current value of the I2S_TCSR_STOPE field. */
572 #define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
574 /*! @brief Format value for bitfield I2S_TCSR_STOPE. */
575 #define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE)
577 /*! @brief Set the STOPE field to a new value. */
578 #define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
582 * @name Register I2S_TCSR, field TE[31] (RW)
584 * Enables/disables the transmitter. When software clears this field, the
585 * transmitter remains enabled, and this bit remains set, until the end of the current
589 * - 0 - Transmitter is disabled.
590 * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
591 * yet reached end of frame.
594 #define BP_I2S_TCSR_TE (31U) /*!< Bit position for I2S_TCSR_TE. */
595 #define BM_I2S_TCSR_TE (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */
596 #define BS_I2S_TCSR_TE (1U) /*!< Bit field size in bits for I2S_TCSR_TE. */
598 /*! @brief Read current value of the I2S_TCSR_TE field. */
599 #define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
601 /*! @brief Format value for bitfield I2S_TCSR_TE. */
602 #define BF_I2S_TCSR_TE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE)
604 /*! @brief Set the TE field to a new value. */
605 #define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
608 /*******************************************************************************
609 * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
610 ******************************************************************************/
613 * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
615 * Reset value: 0x00000000U
617 typedef union _hw_i2s_tcr1
620 struct _hw_i2s_tcr1_bitfields
622 uint32_t TFW
: 3; /*!< [2:0] Transmit FIFO Watermark */
623 uint32_t RESERVED0
: 29; /*!< [31:3] */
628 * @name Constants and macros for entire I2S_TCR1 register
631 #define HW_I2S_TCR1_ADDR(x) ((x) + 0x4U)
633 #define HW_I2S_TCR1(x) (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
634 #define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
635 #define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
636 #define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) | (v)))
637 #define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
638 #define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
642 * Constants & macros for individual I2S_TCR1 bitfields
646 * @name Register I2S_TCR1, field TFW[2:0] (RW)
648 * Configures the watermark level for all enabled transmit channels.
651 #define BP_I2S_TCR1_TFW (0U) /*!< Bit position for I2S_TCR1_TFW. */
652 #define BM_I2S_TCR1_TFW (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */
653 #define BS_I2S_TCR1_TFW (3U) /*!< Bit field size in bits for I2S_TCR1_TFW. */
655 /*! @brief Read current value of the I2S_TCR1_TFW field. */
656 #define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
658 /*! @brief Format value for bitfield I2S_TCR1_TFW. */
659 #define BF_I2S_TCR1_TFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW)
661 /*! @brief Set the TFW field to a new value. */
662 #define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
665 /*******************************************************************************
666 * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
667 ******************************************************************************/
670 * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
672 * Reset value: 0x00000000U
674 * This register must not be altered when TCSR[TE] is set.
676 typedef union _hw_i2s_tcr2
679 struct _hw_i2s_tcr2_bitfields
681 uint32_t DIV
: 8; /*!< [7:0] Bit Clock Divide */
682 uint32_t RESERVED0
: 16; /*!< [23:8] */
683 uint32_t BCD
: 1; /*!< [24] Bit Clock Direction */
684 uint32_t BCP
: 1; /*!< [25] Bit Clock Polarity */
685 uint32_t MSEL
: 2; /*!< [27:26] MCLK Select */
686 uint32_t BCI
: 1; /*!< [28] Bit Clock Input */
687 uint32_t BCS
: 1; /*!< [29] Bit Clock Swap */
688 uint32_t SYNC
: 2; /*!< [31:30] Synchronous Mode */
693 * @name Constants and macros for entire I2S_TCR2 register
696 #define HW_I2S_TCR2_ADDR(x) ((x) + 0x8U)
698 #define HW_I2S_TCR2(x) (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
699 #define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
700 #define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
701 #define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) | (v)))
702 #define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
703 #define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
707 * Constants & macros for individual I2S_TCR2 bitfields
711 * @name Register I2S_TCR2, field DIV[7:0] (RW)
713 * Divides down the audio master clock to generate the bit clock when configured
714 * for an internal bit clock. The division value is (DIV + 1) * 2.
717 #define BP_I2S_TCR2_DIV (0U) /*!< Bit position for I2S_TCR2_DIV. */
718 #define BM_I2S_TCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */
719 #define BS_I2S_TCR2_DIV (8U) /*!< Bit field size in bits for I2S_TCR2_DIV. */
721 /*! @brief Read current value of the I2S_TCR2_DIV field. */
722 #define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
724 /*! @brief Format value for bitfield I2S_TCR2_DIV. */
725 #define BF_I2S_TCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV)
727 /*! @brief Set the DIV field to a new value. */
728 #define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
732 * @name Register I2S_TCR2, field BCD[24] (RW)
734 * Configures the direction of the bit clock.
737 * - 0 - Bit clock is generated externally in Slave mode.
738 * - 1 - Bit clock is generated internally in Master mode.
741 #define BP_I2S_TCR2_BCD (24U) /*!< Bit position for I2S_TCR2_BCD. */
742 #define BM_I2S_TCR2_BCD (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */
743 #define BS_I2S_TCR2_BCD (1U) /*!< Bit field size in bits for I2S_TCR2_BCD. */
745 /*! @brief Read current value of the I2S_TCR2_BCD field. */
746 #define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
748 /*! @brief Format value for bitfield I2S_TCR2_BCD. */
749 #define BF_I2S_TCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD)
751 /*! @brief Set the BCD field to a new value. */
752 #define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
756 * @name Register I2S_TCR2, field BCP[25] (RW)
758 * Configures the polarity of the bit clock.
761 * - 0 - Bit clock is active high with drive outputs on rising edge and sample
762 * inputs on falling edge.
763 * - 1 - Bit clock is active low with drive outputs on falling edge and sample
764 * inputs on rising edge.
767 #define BP_I2S_TCR2_BCP (25U) /*!< Bit position for I2S_TCR2_BCP. */
768 #define BM_I2S_TCR2_BCP (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */
769 #define BS_I2S_TCR2_BCP (1U) /*!< Bit field size in bits for I2S_TCR2_BCP. */
771 /*! @brief Read current value of the I2S_TCR2_BCP field. */
772 #define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
774 /*! @brief Format value for bitfield I2S_TCR2_BCP. */
775 #define BF_I2S_TCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP)
777 /*! @brief Set the BCP field to a new value. */
778 #define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
782 * @name Register I2S_TCR2, field MSEL[27:26] (RW)
784 * Selects the audio Master Clock option used to generate an internally
785 * generated bit clock. This field has no effect when configured for an externally
786 * generated bit clock. Depending on the device, some Master Clock options might not be
787 * available. See the chip configuration details for the availability and
788 * chip-specific meaning of each option.
791 * - 00 - Bus Clock selected.
792 * - 01 - Master Clock (MCLK) 1 option selected.
793 * - 10 - Master Clock (MCLK) 2 option selected.
794 * - 11 - Master Clock (MCLK) 3 option selected.
797 #define BP_I2S_TCR2_MSEL (26U) /*!< Bit position for I2S_TCR2_MSEL. */
798 #define BM_I2S_TCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */
799 #define BS_I2S_TCR2_MSEL (2U) /*!< Bit field size in bits for I2S_TCR2_MSEL. */
801 /*! @brief Read current value of the I2S_TCR2_MSEL field. */
802 #define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
804 /*! @brief Format value for bitfield I2S_TCR2_MSEL. */
805 #define BF_I2S_TCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL)
807 /*! @brief Set the MSEL field to a new value. */
808 #define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
812 * @name Register I2S_TCR2, field BCI[28] (RW)
814 * When this field is set and using an internally generated bit clock in either
815 * synchronous or asynchronous mode, the bit clock actually used by the
816 * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
817 * input as if the clock was externally generated). This has the effect of
818 * decreasing the data input setup time, but increasing the data output valid time. The
819 * slave mode timing from the datasheet should be used for the transmitter when
820 * this bit is set. In synchronous mode, this bit allows the transmitter to use
821 * the slave mode timing from the datasheet, while the receiver uses the master
822 * mode timing. This field has no effect when configured for an externally generated
823 * bit clock or when synchronous to another SAI peripheral .
827 * - 1 - Internal logic is clocked as if bit clock was externally generated.
830 #define BP_I2S_TCR2_BCI (28U) /*!< Bit position for I2S_TCR2_BCI. */
831 #define BM_I2S_TCR2_BCI (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */
832 #define BS_I2S_TCR2_BCI (1U) /*!< Bit field size in bits for I2S_TCR2_BCI. */
834 /*! @brief Read current value of the I2S_TCR2_BCI field. */
835 #define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
837 /*! @brief Format value for bitfield I2S_TCR2_BCI. */
838 #define BF_I2S_TCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI)
840 /*! @brief Set the BCI field to a new value. */
841 #define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
845 * @name Register I2S_TCR2, field BCS[29] (RW)
847 * This field swaps the bit clock used by the transmitter. When the transmitter
848 * is configured in asynchronous mode and this bit is set, the transmitter is
849 * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
850 * receiver to share the same bit clock, but the transmitter continues to use the
851 * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
852 * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
853 * the same value. When both are set, the transmitter and receiver are both
854 * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
855 * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
859 * - 0 - Use the normal bit clock source.
860 * - 1 - Swap the bit clock source.
863 #define BP_I2S_TCR2_BCS (29U) /*!< Bit position for I2S_TCR2_BCS. */
864 #define BM_I2S_TCR2_BCS (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */
865 #define BS_I2S_TCR2_BCS (1U) /*!< Bit field size in bits for I2S_TCR2_BCS. */
867 /*! @brief Read current value of the I2S_TCR2_BCS field. */
868 #define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
870 /*! @brief Format value for bitfield I2S_TCR2_BCS. */
871 #define BF_I2S_TCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS)
873 /*! @brief Set the BCS field to a new value. */
874 #define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
878 * @name Register I2S_TCR2, field SYNC[31:30] (RW)
880 * Configures between asynchronous and synchronous modes of operation. When
881 * configured for a synchronous mode of operation, the receiver or other SAI
882 * peripheral must be configured for asynchronous operation.
885 * - 00 - Asynchronous mode.
886 * - 01 - Synchronous with receiver.
887 * - 10 - Synchronous with another SAI transmitter.
888 * - 11 - Synchronous with another SAI receiver.
891 #define BP_I2S_TCR2_SYNC (30U) /*!< Bit position for I2S_TCR2_SYNC. */
892 #define BM_I2S_TCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */
893 #define BS_I2S_TCR2_SYNC (2U) /*!< Bit field size in bits for I2S_TCR2_SYNC. */
895 /*! @brief Read current value of the I2S_TCR2_SYNC field. */
896 #define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
898 /*! @brief Format value for bitfield I2S_TCR2_SYNC. */
899 #define BF_I2S_TCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC)
901 /*! @brief Set the SYNC field to a new value. */
902 #define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
905 /*******************************************************************************
906 * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
907 ******************************************************************************/
910 * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
912 * Reset value: 0x00000000U
914 * This register must not be altered when TCSR[TE] is set.
916 typedef union _hw_i2s_tcr3
919 struct _hw_i2s_tcr3_bitfields
921 uint32_t WDFL
: 5; /*!< [4:0] Word Flag Configuration */
922 uint32_t RESERVED0
: 11; /*!< [15:5] */
923 uint32_t TCE
: 2; /*!< [17:16] Transmit Channel Enable */
924 uint32_t RESERVED1
: 14; /*!< [31:18] */
929 * @name Constants and macros for entire I2S_TCR3 register
932 #define HW_I2S_TCR3_ADDR(x) ((x) + 0xCU)
934 #define HW_I2S_TCR3(x) (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
935 #define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
936 #define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
937 #define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) | (v)))
938 #define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
939 #define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
943 * Constants & macros for individual I2S_TCR3 bitfields
947 * @name Register I2S_TCR3, field WDFL[4:0] (RW)
949 * Configures which word sets the start of word flag. The value written must be
950 * one less than the word number. For example, writing 0 configures the first
951 * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
952 * start of word flag is never set.
955 #define BP_I2S_TCR3_WDFL (0U) /*!< Bit position for I2S_TCR3_WDFL. */
956 #define BM_I2S_TCR3_WDFL (0x0000001FU) /*!< Bit mask for I2S_TCR3_WDFL. */
957 #define BS_I2S_TCR3_WDFL (5U) /*!< Bit field size in bits for I2S_TCR3_WDFL. */
959 /*! @brief Read current value of the I2S_TCR3_WDFL field. */
960 #define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
962 /*! @brief Format value for bitfield I2S_TCR3_WDFL. */
963 #define BF_I2S_TCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL)
965 /*! @brief Set the WDFL field to a new value. */
966 #define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
970 * @name Register I2S_TCR3, field TCE[17:16] (RW)
972 * Enables the corresponding data channel for transmit operation. A channel must
973 * be enabled before its FIFO is accessed.
976 * - 0 - Transmit data channel N is disabled.
977 * - 1 - Transmit data channel N is enabled.
980 #define BP_I2S_TCR3_TCE (16U) /*!< Bit position for I2S_TCR3_TCE. */
981 #define BM_I2S_TCR3_TCE (0x00030000U) /*!< Bit mask for I2S_TCR3_TCE. */
982 #define BS_I2S_TCR3_TCE (2U) /*!< Bit field size in bits for I2S_TCR3_TCE. */
984 /*! @brief Read current value of the I2S_TCR3_TCE field. */
985 #define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE)
987 /*! @brief Format value for bitfield I2S_TCR3_TCE. */
988 #define BF_I2S_TCR3_TCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE)
990 /*! @brief Set the TCE field to a new value. */
991 #define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v)))
994 /*******************************************************************************
995 * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
996 ******************************************************************************/
999 * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
1001 * Reset value: 0x00000000U
1003 * This register must not be altered when TCSR[TE] is set.
1005 typedef union _hw_i2s_tcr4
1008 struct _hw_i2s_tcr4_bitfields
1010 uint32_t FSD
: 1; /*!< [0] Frame Sync Direction */
1011 uint32_t FSP
: 1; /*!< [1] Frame Sync Polarity */
1012 uint32_t RESERVED0
: 1; /*!< [2] */
1013 uint32_t FSE
: 1; /*!< [3] Frame Sync Early */
1014 uint32_t MF
: 1; /*!< [4] MSB First */
1015 uint32_t RESERVED1
: 3; /*!< [7:5] */
1016 uint32_t SYWD
: 5; /*!< [12:8] Sync Width */
1017 uint32_t RESERVED2
: 3; /*!< [15:13] */
1018 uint32_t FRSZ
: 5; /*!< [20:16] Frame size */
1019 uint32_t RESERVED3
: 11; /*!< [31:21] */
1024 * @name Constants and macros for entire I2S_TCR4 register
1027 #define HW_I2S_TCR4_ADDR(x) ((x) + 0x10U)
1029 #define HW_I2S_TCR4(x) (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
1030 #define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
1031 #define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
1032 #define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) | (v)))
1033 #define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
1034 #define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
1038 * Constants & macros for individual I2S_TCR4 bitfields
1042 * @name Register I2S_TCR4, field FSD[0] (RW)
1044 * Configures the direction of the frame sync.
1047 * - 0 - Frame sync is generated externally in Slave mode.
1048 * - 1 - Frame sync is generated internally in Master mode.
1051 #define BP_I2S_TCR4_FSD (0U) /*!< Bit position for I2S_TCR4_FSD. */
1052 #define BM_I2S_TCR4_FSD (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */
1053 #define BS_I2S_TCR4_FSD (1U) /*!< Bit field size in bits for I2S_TCR4_FSD. */
1055 /*! @brief Read current value of the I2S_TCR4_FSD field. */
1056 #define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
1058 /*! @brief Format value for bitfield I2S_TCR4_FSD. */
1059 #define BF_I2S_TCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD)
1061 /*! @brief Set the FSD field to a new value. */
1062 #define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
1066 * @name Register I2S_TCR4, field FSP[1] (RW)
1068 * Configures the polarity of the frame sync.
1071 * - 0 - Frame sync is active high.
1072 * - 1 - Frame sync is active low.
1075 #define BP_I2S_TCR4_FSP (1U) /*!< Bit position for I2S_TCR4_FSP. */
1076 #define BM_I2S_TCR4_FSP (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */
1077 #define BS_I2S_TCR4_FSP (1U) /*!< Bit field size in bits for I2S_TCR4_FSP. */
1079 /*! @brief Read current value of the I2S_TCR4_FSP field. */
1080 #define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
1082 /*! @brief Format value for bitfield I2S_TCR4_FSP. */
1083 #define BF_I2S_TCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP)
1085 /*! @brief Set the FSP field to a new value. */
1086 #define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
1090 * @name Register I2S_TCR4, field FSE[3] (RW)
1093 * - 0 - Frame sync asserts with the first bit of the frame.
1094 * - 1 - Frame sync asserts one bit before the first bit of the frame.
1097 #define BP_I2S_TCR4_FSE (3U) /*!< Bit position for I2S_TCR4_FSE. */
1098 #define BM_I2S_TCR4_FSE (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */
1099 #define BS_I2S_TCR4_FSE (1U) /*!< Bit field size in bits for I2S_TCR4_FSE. */
1101 /*! @brief Read current value of the I2S_TCR4_FSE field. */
1102 #define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
1104 /*! @brief Format value for bitfield I2S_TCR4_FSE. */
1105 #define BF_I2S_TCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE)
1107 /*! @brief Set the FSE field to a new value. */
1108 #define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
1112 * @name Register I2S_TCR4, field MF[4] (RW)
1114 * Configures whether the LSB or the MSB is transmitted first.
1117 * - 0 - LSB is transmitted first.
1118 * - 1 - MSB is transmitted first.
1121 #define BP_I2S_TCR4_MF (4U) /*!< Bit position for I2S_TCR4_MF. */
1122 #define BM_I2S_TCR4_MF (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */
1123 #define BS_I2S_TCR4_MF (1U) /*!< Bit field size in bits for I2S_TCR4_MF. */
1125 /*! @brief Read current value of the I2S_TCR4_MF field. */
1126 #define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
1128 /*! @brief Format value for bitfield I2S_TCR4_MF. */
1129 #define BF_I2S_TCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF)
1131 /*! @brief Set the MF field to a new value. */
1132 #define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
1136 * @name Register I2S_TCR4, field SYWD[12:8] (RW)
1138 * Configures the length of the frame sync in number of bit clocks. The value
1139 * written must be one less than the number of bit clocks. For example, write 0 for
1140 * the frame sync to assert for one bit clock only. The sync width cannot be
1141 * configured longer than the first word of the frame.
1144 #define BP_I2S_TCR4_SYWD (8U) /*!< Bit position for I2S_TCR4_SYWD. */
1145 #define BM_I2S_TCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */
1146 #define BS_I2S_TCR4_SYWD (5U) /*!< Bit field size in bits for I2S_TCR4_SYWD. */
1148 /*! @brief Read current value of the I2S_TCR4_SYWD field. */
1149 #define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
1151 /*! @brief Format value for bitfield I2S_TCR4_SYWD. */
1152 #define BF_I2S_TCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD)
1154 /*! @brief Set the SYWD field to a new value. */
1155 #define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
1159 * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
1161 * Configures the number of words in each frame. The value written must be one
1162 * less than the number of words in the frame. For example, write 0 for one word
1163 * per frame. The maximum supported frame size is 32 words.
1166 #define BP_I2S_TCR4_FRSZ (16U) /*!< Bit position for I2S_TCR4_FRSZ. */
1167 #define BM_I2S_TCR4_FRSZ (0x001F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */
1168 #define BS_I2S_TCR4_FRSZ (5U) /*!< Bit field size in bits for I2S_TCR4_FRSZ. */
1170 /*! @brief Read current value of the I2S_TCR4_FRSZ field. */
1171 #define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
1173 /*! @brief Format value for bitfield I2S_TCR4_FRSZ. */
1174 #define BF_I2S_TCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ)
1176 /*! @brief Set the FRSZ field to a new value. */
1177 #define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
1180 /*******************************************************************************
1181 * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
1182 ******************************************************************************/
1185 * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
1187 * Reset value: 0x00000000U
1189 * This register must not be altered when TCSR[TE] is set.
1191 typedef union _hw_i2s_tcr5
1194 struct _hw_i2s_tcr5_bitfields
1196 uint32_t RESERVED0
: 8; /*!< [7:0] */
1197 uint32_t FBT
: 5; /*!< [12:8] First Bit Shifted */
1198 uint32_t RESERVED1
: 3; /*!< [15:13] */
1199 uint32_t W0W
: 5; /*!< [20:16] Word 0 Width */
1200 uint32_t RESERVED2
: 3; /*!< [23:21] */
1201 uint32_t WNW
: 5; /*!< [28:24] Word N Width */
1202 uint32_t RESERVED3
: 3; /*!< [31:29] */
1207 * @name Constants and macros for entire I2S_TCR5 register
1210 #define HW_I2S_TCR5_ADDR(x) ((x) + 0x14U)
1212 #define HW_I2S_TCR5(x) (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
1213 #define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
1214 #define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
1215 #define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) | (v)))
1216 #define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
1217 #define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
1221 * Constants & macros for individual I2S_TCR5 bitfields
1225 * @name Register I2S_TCR5, field FBT[12:8] (RW)
1227 * Configures the bit index for the first bit transmitted for each word in the
1228 * frame. If configured for MSB First, the index of the next bit transmitted is
1229 * one less than the current bit transmitted. If configured for LSB First, the
1230 * index of the next bit transmitted is one more than the current bit transmitted.
1231 * The value written must be greater than or equal to the word width when
1232 * configured for MSB First. The value written must be less than or equal to 31-word width
1233 * when configured for LSB First.
1236 #define BP_I2S_TCR5_FBT (8U) /*!< Bit position for I2S_TCR5_FBT. */
1237 #define BM_I2S_TCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */
1238 #define BS_I2S_TCR5_FBT (5U) /*!< Bit field size in bits for I2S_TCR5_FBT. */
1240 /*! @brief Read current value of the I2S_TCR5_FBT field. */
1241 #define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
1243 /*! @brief Format value for bitfield I2S_TCR5_FBT. */
1244 #define BF_I2S_TCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT)
1246 /*! @brief Set the FBT field to a new value. */
1247 #define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
1251 * @name Register I2S_TCR5, field W0W[20:16] (RW)
1253 * Configures the number of bits in the first word in each frame. The value
1254 * written must be one less than the number of bits in the first word. Word width of
1255 * less than 8 bits is not supported if there is only one word per frame.
1258 #define BP_I2S_TCR5_W0W (16U) /*!< Bit position for I2S_TCR5_W0W. */
1259 #define BM_I2S_TCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */
1260 #define BS_I2S_TCR5_W0W (5U) /*!< Bit field size in bits for I2S_TCR5_W0W. */
1262 /*! @brief Read current value of the I2S_TCR5_W0W field. */
1263 #define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
1265 /*! @brief Format value for bitfield I2S_TCR5_W0W. */
1266 #define BF_I2S_TCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W)
1268 /*! @brief Set the W0W field to a new value. */
1269 #define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
1273 * @name Register I2S_TCR5, field WNW[28:24] (RW)
1275 * Configures the number of bits in each word, for each word except the first in
1276 * the frame. The value written must be one less than the number of bits per
1277 * word. Word width of less than 8 bits is not supported.
1280 #define BP_I2S_TCR5_WNW (24U) /*!< Bit position for I2S_TCR5_WNW. */
1281 #define BM_I2S_TCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */
1282 #define BS_I2S_TCR5_WNW (5U) /*!< Bit field size in bits for I2S_TCR5_WNW. */
1284 /*! @brief Read current value of the I2S_TCR5_WNW field. */
1285 #define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
1287 /*! @brief Format value for bitfield I2S_TCR5_WNW. */
1288 #define BF_I2S_TCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW)
1290 /*! @brief Set the WNW field to a new value. */
1291 #define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
1294 /*******************************************************************************
1295 * HW_I2S_TDRn - SAI Transmit Data Register
1296 ******************************************************************************/
1299 * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
1301 * Reset value: 0x00000000U
1303 typedef union _hw_i2s_tdrn
1306 struct _hw_i2s_tdrn_bitfields
1308 uint32_t TDR
: 32; /*!< [31:0] Transmit Data Register */
1313 * @name Constants and macros for entire I2S_TDRn register
1316 #define HW_I2S_TDRn_COUNT (2U)
1318 #define HW_I2S_TDRn_ADDR(x, n) ((x) + 0x20U + (0x4U * (n)))
1320 #define HW_I2S_TDRn(x, n) (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
1321 #define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
1322 #define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
1326 * Constants & macros for individual I2S_TDRn bitfields
1330 * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
1332 * The corresponding TCR3[TCE] bit must be set before accessing the channel's
1333 * transmit data register. Writes to this register when the transmit FIFO is not
1334 * full will push the data written into the transmit data FIFO. Writes to this
1335 * register when the transmit FIFO is full are ignored.
1338 #define BP_I2S_TDRn_TDR (0U) /*!< Bit position for I2S_TDRn_TDR. */
1339 #define BM_I2S_TDRn_TDR (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */
1340 #define BS_I2S_TDRn_TDR (32U) /*!< Bit field size in bits for I2S_TDRn_TDR. */
1342 /*! @brief Format value for bitfield I2S_TDRn_TDR. */
1343 #define BF_I2S_TDRn_TDR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR)
1345 /*! @brief Set the TDR field to a new value. */
1346 #define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
1349 /*******************************************************************************
1350 * HW_I2S_TFRn - SAI Transmit FIFO Register
1351 ******************************************************************************/
1354 * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
1356 * Reset value: 0x00000000U
1358 * The MSB of the read and write pointers is used to distinguish between FIFO
1359 * full and empty conditions. If the read and write pointers are identical, then
1360 * the FIFO is empty. If the read and write pointers are identical except for the
1361 * MSB, then the FIFO is full.
1363 typedef union _hw_i2s_tfrn
1366 struct _hw_i2s_tfrn_bitfields
1368 uint32_t RFP
: 4; /*!< [3:0] Read FIFO Pointer */
1369 uint32_t RESERVED0
: 12; /*!< [15:4] */
1370 uint32_t WFP
: 4; /*!< [19:16] Write FIFO Pointer */
1371 uint32_t RESERVED1
: 12; /*!< [31:20] */
1376 * @name Constants and macros for entire I2S_TFRn register
1379 #define HW_I2S_TFRn_COUNT (2U)
1381 #define HW_I2S_TFRn_ADDR(x, n) ((x) + 0x40U + (0x4U * (n)))
1383 #define HW_I2S_TFRn(x, n) (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
1384 #define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
1388 * Constants & macros for individual I2S_TFRn bitfields
1392 * @name Register I2S_TFRn, field RFP[3:0] (RO)
1394 * FIFO read pointer for transmit data channel.
1397 #define BP_I2S_TFRn_RFP (0U) /*!< Bit position for I2S_TFRn_RFP. */
1398 #define BM_I2S_TFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */
1399 #define BS_I2S_TFRn_RFP (4U) /*!< Bit field size in bits for I2S_TFRn_RFP. */
1401 /*! @brief Read current value of the I2S_TFRn_RFP field. */
1402 #define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
1406 * @name Register I2S_TFRn, field WFP[19:16] (RO)
1408 * FIFO write pointer for transmit data channel.
1411 #define BP_I2S_TFRn_WFP (16U) /*!< Bit position for I2S_TFRn_WFP. */
1412 #define BM_I2S_TFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */
1413 #define BS_I2S_TFRn_WFP (4U) /*!< Bit field size in bits for I2S_TFRn_WFP. */
1415 /*! @brief Read current value of the I2S_TFRn_WFP field. */
1416 #define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
1419 /*******************************************************************************
1420 * HW_I2S_TMR - SAI Transmit Mask Register
1421 ******************************************************************************/
1424 * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
1426 * Reset value: 0x00000000U
1428 * This register is double-buffered and updates: When TCSR[TE] is first set At
1429 * the end of each frame. This allows the masked words in each frame to change
1430 * from frame to frame.
1432 typedef union _hw_i2s_tmr
1435 struct _hw_i2s_tmr_bitfields
1437 uint32_t TWM
: 32; /*!< [31:0] Transmit Word Mask */
1442 * @name Constants and macros for entire I2S_TMR register
1445 #define HW_I2S_TMR_ADDR(x) ((x) + 0x60U)
1447 #define HW_I2S_TMR(x) (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
1448 #define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
1449 #define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
1450 #define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) | (v)))
1451 #define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
1452 #define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
1456 * Constants & macros for individual I2S_TMR bitfields
1460 * @name Register I2S_TMR, field TWM[31:0] (RW)
1462 * Configures whether the transmit word is masked (transmit data pin tristated
1463 * and transmit data not read from FIFO) for the corresponding word in the frame.
1466 * - 0 - Word N is enabled.
1467 * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
1470 #define BP_I2S_TMR_TWM (0U) /*!< Bit position for I2S_TMR_TWM. */
1471 #define BM_I2S_TMR_TWM (0xFFFFFFFFU) /*!< Bit mask for I2S_TMR_TWM. */
1472 #define BS_I2S_TMR_TWM (32U) /*!< Bit field size in bits for I2S_TMR_TWM. */
1474 /*! @brief Read current value of the I2S_TMR_TWM field. */
1475 #define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U)
1477 /*! @brief Format value for bitfield I2S_TMR_TWM. */
1478 #define BF_I2S_TMR_TWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM)
1480 /*! @brief Set the TWM field to a new value. */
1481 #define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
1484 /*******************************************************************************
1485 * HW_I2S_RCSR - SAI Receive Control Register
1486 ******************************************************************************/
1489 * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
1491 * Reset value: 0x00000000U
1493 typedef union _hw_i2s_rcsr
1496 struct _hw_i2s_rcsr_bitfields
1498 uint32_t FRDE
: 1; /*!< [0] FIFO Request DMA Enable */
1499 uint32_t FWDE
: 1; /*!< [1] FIFO Warning DMA Enable */
1500 uint32_t RESERVED0
: 6; /*!< [7:2] */
1501 uint32_t FRIE
: 1; /*!< [8] FIFO Request Interrupt Enable */
1502 uint32_t FWIE
: 1; /*!< [9] FIFO Warning Interrupt Enable */
1503 uint32_t FEIE
: 1; /*!< [10] FIFO Error Interrupt Enable */
1504 uint32_t SEIE
: 1; /*!< [11] Sync Error Interrupt Enable */
1505 uint32_t WSIE
: 1; /*!< [12] Word Start Interrupt Enable */
1506 uint32_t RESERVED1
: 3; /*!< [15:13] */
1507 uint32_t FRF
: 1; /*!< [16] FIFO Request Flag */
1508 uint32_t FWF
: 1; /*!< [17] FIFO Warning Flag */
1509 uint32_t FEF
: 1; /*!< [18] FIFO Error Flag */
1510 uint32_t SEF
: 1; /*!< [19] Sync Error Flag */
1511 uint32_t WSF
: 1; /*!< [20] Word Start Flag */
1512 uint32_t RESERVED2
: 3; /*!< [23:21] */
1513 uint32_t SR
: 1; /*!< [24] Software Reset */
1514 uint32_t FR
: 1; /*!< [25] FIFO Reset */
1515 uint32_t RESERVED3
: 2; /*!< [27:26] */
1516 uint32_t BCE
: 1; /*!< [28] Bit Clock Enable */
1517 uint32_t DBGE
: 1; /*!< [29] Debug Enable */
1518 uint32_t STOPE
: 1; /*!< [30] Stop Enable */
1519 uint32_t RE
: 1; /*!< [31] Receiver Enable */
1524 * @name Constants and macros for entire I2S_RCSR register
1527 #define HW_I2S_RCSR_ADDR(x) ((x) + 0x80U)
1529 #define HW_I2S_RCSR(x) (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
1530 #define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
1531 #define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
1532 #define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) | (v)))
1533 #define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
1534 #define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
1538 * Constants & macros for individual I2S_RCSR bitfields
1542 * @name Register I2S_RCSR, field FRDE[0] (RW)
1544 * Enables/disables DMA requests.
1547 * - 0 - Disables the DMA request.
1548 * - 1 - Enables the DMA request.
1551 #define BP_I2S_RCSR_FRDE (0U) /*!< Bit position for I2S_RCSR_FRDE. */
1552 #define BM_I2S_RCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */
1553 #define BS_I2S_RCSR_FRDE (1U) /*!< Bit field size in bits for I2S_RCSR_FRDE. */
1555 /*! @brief Read current value of the I2S_RCSR_FRDE field. */
1556 #define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
1558 /*! @brief Format value for bitfield I2S_RCSR_FRDE. */
1559 #define BF_I2S_RCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE)
1561 /*! @brief Set the FRDE field to a new value. */
1562 #define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
1566 * @name Register I2S_RCSR, field FWDE[1] (RW)
1568 * Enables/disables DMA requests.
1571 * - 0 - Disables the DMA request.
1572 * - 1 - Enables the DMA request.
1575 #define BP_I2S_RCSR_FWDE (1U) /*!< Bit position for I2S_RCSR_FWDE. */
1576 #define BM_I2S_RCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */
1577 #define BS_I2S_RCSR_FWDE (1U) /*!< Bit field size in bits for I2S_RCSR_FWDE. */
1579 /*! @brief Read current value of the I2S_RCSR_FWDE field. */
1580 #define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
1582 /*! @brief Format value for bitfield I2S_RCSR_FWDE. */
1583 #define BF_I2S_RCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE)
1585 /*! @brief Set the FWDE field to a new value. */
1586 #define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
1590 * @name Register I2S_RCSR, field FRIE[8] (RW)
1592 * Enables/disables FIFO request interrupts.
1595 * - 0 - Disables the interrupt.
1596 * - 1 - Enables the interrupt.
1599 #define BP_I2S_RCSR_FRIE (8U) /*!< Bit position for I2S_RCSR_FRIE. */
1600 #define BM_I2S_RCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */
1601 #define BS_I2S_RCSR_FRIE (1U) /*!< Bit field size in bits for I2S_RCSR_FRIE. */
1603 /*! @brief Read current value of the I2S_RCSR_FRIE field. */
1604 #define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
1606 /*! @brief Format value for bitfield I2S_RCSR_FRIE. */
1607 #define BF_I2S_RCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE)
1609 /*! @brief Set the FRIE field to a new value. */
1610 #define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
1614 * @name Register I2S_RCSR, field FWIE[9] (RW)
1616 * Enables/disables FIFO warning interrupts.
1619 * - 0 - Disables the interrupt.
1620 * - 1 - Enables the interrupt.
1623 #define BP_I2S_RCSR_FWIE (9U) /*!< Bit position for I2S_RCSR_FWIE. */
1624 #define BM_I2S_RCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */
1625 #define BS_I2S_RCSR_FWIE (1U) /*!< Bit field size in bits for I2S_RCSR_FWIE. */
1627 /*! @brief Read current value of the I2S_RCSR_FWIE field. */
1628 #define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
1630 /*! @brief Format value for bitfield I2S_RCSR_FWIE. */
1631 #define BF_I2S_RCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE)
1633 /*! @brief Set the FWIE field to a new value. */
1634 #define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
1638 * @name Register I2S_RCSR, field FEIE[10] (RW)
1640 * Enables/disables FIFO error interrupts.
1643 * - 0 - Disables the interrupt.
1644 * - 1 - Enables the interrupt.
1647 #define BP_I2S_RCSR_FEIE (10U) /*!< Bit position for I2S_RCSR_FEIE. */
1648 #define BM_I2S_RCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */
1649 #define BS_I2S_RCSR_FEIE (1U) /*!< Bit field size in bits for I2S_RCSR_FEIE. */
1651 /*! @brief Read current value of the I2S_RCSR_FEIE field. */
1652 #define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
1654 /*! @brief Format value for bitfield I2S_RCSR_FEIE. */
1655 #define BF_I2S_RCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE)
1657 /*! @brief Set the FEIE field to a new value. */
1658 #define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
1662 * @name Register I2S_RCSR, field SEIE[11] (RW)
1664 * Enables/disables sync error interrupts.
1667 * - 0 - Disables interrupt.
1668 * - 1 - Enables interrupt.
1671 #define BP_I2S_RCSR_SEIE (11U) /*!< Bit position for I2S_RCSR_SEIE. */
1672 #define BM_I2S_RCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */
1673 #define BS_I2S_RCSR_SEIE (1U) /*!< Bit field size in bits for I2S_RCSR_SEIE. */
1675 /*! @brief Read current value of the I2S_RCSR_SEIE field. */
1676 #define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
1678 /*! @brief Format value for bitfield I2S_RCSR_SEIE. */
1679 #define BF_I2S_RCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE)
1681 /*! @brief Set the SEIE field to a new value. */
1682 #define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
1686 * @name Register I2S_RCSR, field WSIE[12] (RW)
1688 * Enables/disables word start interrupts.
1691 * - 0 - Disables interrupt.
1692 * - 1 - Enables interrupt.
1695 #define BP_I2S_RCSR_WSIE (12U) /*!< Bit position for I2S_RCSR_WSIE. */
1696 #define BM_I2S_RCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */
1697 #define BS_I2S_RCSR_WSIE (1U) /*!< Bit field size in bits for I2S_RCSR_WSIE. */
1699 /*! @brief Read current value of the I2S_RCSR_WSIE field. */
1700 #define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
1702 /*! @brief Format value for bitfield I2S_RCSR_WSIE. */
1703 #define BF_I2S_RCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE)
1705 /*! @brief Set the WSIE field to a new value. */
1706 #define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
1710 * @name Register I2S_RCSR, field FRF[16] (RO)
1712 * Indicates that the number of words in an enabled receive channel FIFO is
1713 * greater than the receive FIFO watermark.
1716 * - 0 - Receive FIFO watermark not reached.
1717 * - 1 - Receive FIFO watermark has been reached.
1720 #define BP_I2S_RCSR_FRF (16U) /*!< Bit position for I2S_RCSR_FRF. */
1721 #define BM_I2S_RCSR_FRF (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */
1722 #define BS_I2S_RCSR_FRF (1U) /*!< Bit field size in bits for I2S_RCSR_FRF. */
1724 /*! @brief Read current value of the I2S_RCSR_FRF field. */
1725 #define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
1729 * @name Register I2S_RCSR, field FWF[17] (RO)
1731 * Indicates that an enabled receive FIFO is full.
1734 * - 0 - No enabled receive FIFO is full.
1735 * - 1 - Enabled receive FIFO is full.
1738 #define BP_I2S_RCSR_FWF (17U) /*!< Bit position for I2S_RCSR_FWF. */
1739 #define BM_I2S_RCSR_FWF (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */
1740 #define BS_I2S_RCSR_FWF (1U) /*!< Bit field size in bits for I2S_RCSR_FWF. */
1742 /*! @brief Read current value of the I2S_RCSR_FWF field. */
1743 #define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
1747 * @name Register I2S_RCSR, field FEF[18] (W1C)
1749 * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
1750 * this field to clear this flag.
1753 * - 0 - Receive overflow not detected.
1754 * - 1 - Receive overflow detected.
1757 #define BP_I2S_RCSR_FEF (18U) /*!< Bit position for I2S_RCSR_FEF. */
1758 #define BM_I2S_RCSR_FEF (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */
1759 #define BS_I2S_RCSR_FEF (1U) /*!< Bit field size in bits for I2S_RCSR_FEF. */
1761 /*! @brief Read current value of the I2S_RCSR_FEF field. */
1762 #define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
1764 /*! @brief Format value for bitfield I2S_RCSR_FEF. */
1765 #define BF_I2S_RCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF)
1767 /*! @brief Set the FEF field to a new value. */
1768 #define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
1772 * @name Register I2S_RCSR, field SEF[19] (W1C)
1774 * Indicates that an error in the externally-generated frame sync has been
1775 * detected. Write a logic 1 to this field to clear this flag.
1778 * - 0 - Sync error not detected.
1779 * - 1 - Frame sync error detected.
1782 #define BP_I2S_RCSR_SEF (19U) /*!< Bit position for I2S_RCSR_SEF. */
1783 #define BM_I2S_RCSR_SEF (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */
1784 #define BS_I2S_RCSR_SEF (1U) /*!< Bit field size in bits for I2S_RCSR_SEF. */
1786 /*! @brief Read current value of the I2S_RCSR_SEF field. */
1787 #define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
1789 /*! @brief Format value for bitfield I2S_RCSR_SEF. */
1790 #define BF_I2S_RCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF)
1792 /*! @brief Set the SEF field to a new value. */
1793 #define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
1797 * @name Register I2S_RCSR, field WSF[20] (W1C)
1799 * Indicates that the start of the configured word has been detected. Write a
1800 * logic 1 to this field to clear this flag.
1803 * - 0 - Start of word not detected.
1804 * - 1 - Start of word detected.
1807 #define BP_I2S_RCSR_WSF (20U) /*!< Bit position for I2S_RCSR_WSF. */
1808 #define BM_I2S_RCSR_WSF (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */
1809 #define BS_I2S_RCSR_WSF (1U) /*!< Bit field size in bits for I2S_RCSR_WSF. */
1811 /*! @brief Read current value of the I2S_RCSR_WSF field. */
1812 #define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
1814 /*! @brief Format value for bitfield I2S_RCSR_WSF. */
1815 #define BF_I2S_RCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF)
1817 /*! @brief Set the WSF field to a new value. */
1818 #define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
1822 * @name Register I2S_RCSR, field SR[24] (RW)
1824 * Resets the internal receiver logic including the FIFO pointers.
1825 * Software-visible registers are not affected, except for the status registers.
1829 * - 1 - Software reset.
1832 #define BP_I2S_RCSR_SR (24U) /*!< Bit position for I2S_RCSR_SR. */
1833 #define BM_I2S_RCSR_SR (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */
1834 #define BS_I2S_RCSR_SR (1U) /*!< Bit field size in bits for I2S_RCSR_SR. */
1836 /*! @brief Read current value of the I2S_RCSR_SR field. */
1837 #define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
1839 /*! @brief Format value for bitfield I2S_RCSR_SR. */
1840 #define BF_I2S_RCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR)
1842 /*! @brief Set the SR field to a new value. */
1843 #define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
1847 * @name Register I2S_RCSR, field FR[25] (WORZ)
1849 * Resets the FIFO pointers. Reading this field will always return zero. FIFO
1850 * pointers should only be reset when the receiver is disabled or the FIFO error
1858 #define BP_I2S_RCSR_FR (25U) /*!< Bit position for I2S_RCSR_FR. */
1859 #define BM_I2S_RCSR_FR (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */
1860 #define BS_I2S_RCSR_FR (1U) /*!< Bit field size in bits for I2S_RCSR_FR. */
1862 /*! @brief Format value for bitfield I2S_RCSR_FR. */
1863 #define BF_I2S_RCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR)
1865 /*! @brief Set the FR field to a new value. */
1866 #define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
1870 * @name Register I2S_RCSR, field BCE[28] (RW)
1872 * Enables the receive bit clock, separately from RE. This field is
1873 * automatically set whenever RE is set. When software clears this field, the receive bit
1874 * clock remains enabled, and this field remains set, until the end of the current
1878 * - 0 - Receive bit clock is disabled.
1879 * - 1 - Receive bit clock is enabled.
1882 #define BP_I2S_RCSR_BCE (28U) /*!< Bit position for I2S_RCSR_BCE. */
1883 #define BM_I2S_RCSR_BCE (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */
1884 #define BS_I2S_RCSR_BCE (1U) /*!< Bit field size in bits for I2S_RCSR_BCE. */
1886 /*! @brief Read current value of the I2S_RCSR_BCE field. */
1887 #define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
1889 /*! @brief Format value for bitfield I2S_RCSR_BCE. */
1890 #define BF_I2S_RCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE)
1892 /*! @brief Set the BCE field to a new value. */
1893 #define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
1897 * @name Register I2S_RCSR, field DBGE[29] (RW)
1899 * Enables/disables receiver operation in Debug mode. The receive bit clock is
1900 * not affected by Debug mode.
1903 * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
1904 * - 1 - Receiver is enabled in Debug mode.
1907 #define BP_I2S_RCSR_DBGE (29U) /*!< Bit position for I2S_RCSR_DBGE. */
1908 #define BM_I2S_RCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */
1909 #define BS_I2S_RCSR_DBGE (1U) /*!< Bit field size in bits for I2S_RCSR_DBGE. */
1911 /*! @brief Read current value of the I2S_RCSR_DBGE field. */
1912 #define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
1914 /*! @brief Format value for bitfield I2S_RCSR_DBGE. */
1915 #define BF_I2S_RCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE)
1917 /*! @brief Set the DBGE field to a new value. */
1918 #define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
1922 * @name Register I2S_RCSR, field STOPE[30] (RW)
1924 * Configures receiver operation in Stop mode. This bit is ignored and the
1925 * receiver is disabled in all low-leakage stop modes.
1928 * - 0 - Receiver disabled in Stop mode.
1929 * - 1 - Receiver enabled in Stop mode.
1932 #define BP_I2S_RCSR_STOPE (30U) /*!< Bit position for I2S_RCSR_STOPE. */
1933 #define BM_I2S_RCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */
1934 #define BS_I2S_RCSR_STOPE (1U) /*!< Bit field size in bits for I2S_RCSR_STOPE. */
1936 /*! @brief Read current value of the I2S_RCSR_STOPE field. */
1937 #define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
1939 /*! @brief Format value for bitfield I2S_RCSR_STOPE. */
1940 #define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE)
1942 /*! @brief Set the STOPE field to a new value. */
1943 #define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
1947 * @name Register I2S_RCSR, field RE[31] (RW)
1949 * Enables/disables the receiver. When software clears this field, the receiver
1950 * remains enabled, and this bit remains set, until the end of the current frame.
1953 * - 0 - Receiver is disabled.
1954 * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
1955 * reached end of frame.
1958 #define BP_I2S_RCSR_RE (31U) /*!< Bit position for I2S_RCSR_RE. */
1959 #define BM_I2S_RCSR_RE (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */
1960 #define BS_I2S_RCSR_RE (1U) /*!< Bit field size in bits for I2S_RCSR_RE. */
1962 /*! @brief Read current value of the I2S_RCSR_RE field. */
1963 #define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
1965 /*! @brief Format value for bitfield I2S_RCSR_RE. */
1966 #define BF_I2S_RCSR_RE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE)
1968 /*! @brief Set the RE field to a new value. */
1969 #define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
1972 /*******************************************************************************
1973 * HW_I2S_RCR1 - SAI Receive Configuration 1 Register
1974 ******************************************************************************/
1977 * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
1979 * Reset value: 0x00000000U
1981 typedef union _hw_i2s_rcr1
1984 struct _hw_i2s_rcr1_bitfields
1986 uint32_t RFW
: 3; /*!< [2:0] Receive FIFO Watermark */
1987 uint32_t RESERVED0
: 29; /*!< [31:3] */
1992 * @name Constants and macros for entire I2S_RCR1 register
1995 #define HW_I2S_RCR1_ADDR(x) ((x) + 0x84U)
1997 #define HW_I2S_RCR1(x) (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
1998 #define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
1999 #define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
2000 #define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) | (v)))
2001 #define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
2002 #define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
2006 * Constants & macros for individual I2S_RCR1 bitfields
2010 * @name Register I2S_RCR1, field RFW[2:0] (RW)
2012 * Configures the watermark level for all enabled receiver channels.
2015 #define BP_I2S_RCR1_RFW (0U) /*!< Bit position for I2S_RCR1_RFW. */
2016 #define BM_I2S_RCR1_RFW (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */
2017 #define BS_I2S_RCR1_RFW (3U) /*!< Bit field size in bits for I2S_RCR1_RFW. */
2019 /*! @brief Read current value of the I2S_RCR1_RFW field. */
2020 #define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
2022 /*! @brief Format value for bitfield I2S_RCR1_RFW. */
2023 #define BF_I2S_RCR1_RFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW)
2025 /*! @brief Set the RFW field to a new value. */
2026 #define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
2029 /*******************************************************************************
2030 * HW_I2S_RCR2 - SAI Receive Configuration 2 Register
2031 ******************************************************************************/
2034 * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
2036 * Reset value: 0x00000000U
2038 * This register must not be altered when RCSR[RE] is set.
2040 typedef union _hw_i2s_rcr2
2043 struct _hw_i2s_rcr2_bitfields
2045 uint32_t DIV
: 8; /*!< [7:0] Bit Clock Divide */
2046 uint32_t RESERVED0
: 16; /*!< [23:8] */
2047 uint32_t BCD
: 1; /*!< [24] Bit Clock Direction */
2048 uint32_t BCP
: 1; /*!< [25] Bit Clock Polarity */
2049 uint32_t MSEL
: 2; /*!< [27:26] MCLK Select */
2050 uint32_t BCI
: 1; /*!< [28] Bit Clock Input */
2051 uint32_t BCS
: 1; /*!< [29] Bit Clock Swap */
2052 uint32_t SYNC
: 2; /*!< [31:30] Synchronous Mode */
2057 * @name Constants and macros for entire I2S_RCR2 register
2060 #define HW_I2S_RCR2_ADDR(x) ((x) + 0x88U)
2062 #define HW_I2S_RCR2(x) (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
2063 #define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
2064 #define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
2065 #define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) | (v)))
2066 #define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
2067 #define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
2071 * Constants & macros for individual I2S_RCR2 bitfields
2075 * @name Register I2S_RCR2, field DIV[7:0] (RW)
2077 * Divides down the audio master clock to generate the bit clock when configured
2078 * for an internal bit clock. The division value is (DIV + 1) * 2.
2081 #define BP_I2S_RCR2_DIV (0U) /*!< Bit position for I2S_RCR2_DIV. */
2082 #define BM_I2S_RCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */
2083 #define BS_I2S_RCR2_DIV (8U) /*!< Bit field size in bits for I2S_RCR2_DIV. */
2085 /*! @brief Read current value of the I2S_RCR2_DIV field. */
2086 #define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
2088 /*! @brief Format value for bitfield I2S_RCR2_DIV. */
2089 #define BF_I2S_RCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV)
2091 /*! @brief Set the DIV field to a new value. */
2092 #define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
2096 * @name Register I2S_RCR2, field BCD[24] (RW)
2098 * Configures the direction of the bit clock.
2101 * - 0 - Bit clock is generated externally in Slave mode.
2102 * - 1 - Bit clock is generated internally in Master mode.
2105 #define BP_I2S_RCR2_BCD (24U) /*!< Bit position for I2S_RCR2_BCD. */
2106 #define BM_I2S_RCR2_BCD (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */
2107 #define BS_I2S_RCR2_BCD (1U) /*!< Bit field size in bits for I2S_RCR2_BCD. */
2109 /*! @brief Read current value of the I2S_RCR2_BCD field. */
2110 #define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
2112 /*! @brief Format value for bitfield I2S_RCR2_BCD. */
2113 #define BF_I2S_RCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD)
2115 /*! @brief Set the BCD field to a new value. */
2116 #define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
2120 * @name Register I2S_RCR2, field BCP[25] (RW)
2122 * Configures the polarity of the bit clock.
2125 * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
2126 * inputs on falling edge.
2127 * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
2128 * inputs on rising edge.
2131 #define BP_I2S_RCR2_BCP (25U) /*!< Bit position for I2S_RCR2_BCP. */
2132 #define BM_I2S_RCR2_BCP (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */
2133 #define BS_I2S_RCR2_BCP (1U) /*!< Bit field size in bits for I2S_RCR2_BCP. */
2135 /*! @brief Read current value of the I2S_RCR2_BCP field. */
2136 #define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
2138 /*! @brief Format value for bitfield I2S_RCR2_BCP. */
2139 #define BF_I2S_RCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP)
2141 /*! @brief Set the BCP field to a new value. */
2142 #define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
2146 * @name Register I2S_RCR2, field MSEL[27:26] (RW)
2148 * Selects the audio Master Clock option used to generate an internally
2149 * generated bit clock. This field has no effect when configured for an externally
2150 * generated bit clock. Depending on the device, some Master Clock options might not be
2151 * available. See the chip configuration details for the availability and
2152 * chip-specific meaning of each option.
2155 * - 00 - Bus Clock selected.
2156 * - 01 - Master Clock (MCLK) 1 option selected.
2157 * - 10 - Master Clock (MCLK) 2 option selected.
2158 * - 11 - Master Clock (MCLK) 3 option selected.
2161 #define BP_I2S_RCR2_MSEL (26U) /*!< Bit position for I2S_RCR2_MSEL. */
2162 #define BM_I2S_RCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */
2163 #define BS_I2S_RCR2_MSEL (2U) /*!< Bit field size in bits for I2S_RCR2_MSEL. */
2165 /*! @brief Read current value of the I2S_RCR2_MSEL field. */
2166 #define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
2168 /*! @brief Format value for bitfield I2S_RCR2_MSEL. */
2169 #define BF_I2S_RCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL)
2171 /*! @brief Set the MSEL field to a new value. */
2172 #define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
2176 * @name Register I2S_RCR2, field BCI[28] (RW)
2178 * When this field is set and using an internally generated bit clock in either
2179 * synchronous or asynchronous mode, the bit clock actually used by the receiver
2180 * is delayed by the pad output delay (the receiver is clocked by the pad input
2181 * as if the clock was externally generated). This has the effect of decreasing
2182 * the data input setup time, but increasing the data output valid time. The slave
2183 * mode timing from the datasheet should be used for the receiver when this bit
2184 * is set. In synchronous mode, this bit allows the receiver to use the slave mode
2185 * timing from the datasheet, while the transmitter uses the master mode timing.
2186 * This field has no effect when configured for an externally generated bit
2187 * clock or when synchronous to another SAI peripheral .
2191 * - 1 - Internal logic is clocked as if bit clock was externally generated.
2194 #define BP_I2S_RCR2_BCI (28U) /*!< Bit position for I2S_RCR2_BCI. */
2195 #define BM_I2S_RCR2_BCI (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */
2196 #define BS_I2S_RCR2_BCI (1U) /*!< Bit field size in bits for I2S_RCR2_BCI. */
2198 /*! @brief Read current value of the I2S_RCR2_BCI field. */
2199 #define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
2201 /*! @brief Format value for bitfield I2S_RCR2_BCI. */
2202 #define BF_I2S_RCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI)
2204 /*! @brief Set the BCI field to a new value. */
2205 #define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
2209 * @name Register I2S_RCR2, field BCS[29] (RW)
2211 * This field swaps the bit clock used by the receiver. When the receiver is
2212 * configured in asynchronous mode and this bit is set, the receiver is clocked by
2213 * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
2214 * receiver to share the same bit clock, but the receiver continues to use the receiver
2215 * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
2216 * mode, the transmitter BCS field and receiver BCS field must be set to the same
2217 * value. When both are set, the transmitter and receiver are both clocked by the
2218 * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
2219 * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
2222 * - 0 - Use the normal bit clock source.
2223 * - 1 - Swap the bit clock source.
2226 #define BP_I2S_RCR2_BCS (29U) /*!< Bit position for I2S_RCR2_BCS. */
2227 #define BM_I2S_RCR2_BCS (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */
2228 #define BS_I2S_RCR2_BCS (1U) /*!< Bit field size in bits for I2S_RCR2_BCS. */
2230 /*! @brief Read current value of the I2S_RCR2_BCS field. */
2231 #define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
2233 /*! @brief Format value for bitfield I2S_RCR2_BCS. */
2234 #define BF_I2S_RCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS)
2236 /*! @brief Set the BCS field to a new value. */
2237 #define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
2241 * @name Register I2S_RCR2, field SYNC[31:30] (RW)
2243 * Configures between asynchronous and synchronous modes of operation. When
2244 * configured for a synchronous mode of operation, the transmitter or other SAI
2245 * peripheral must be configured for asynchronous operation.
2248 * - 00 - Asynchronous mode.
2249 * - 01 - Synchronous with transmitter.
2250 * - 10 - Synchronous with another SAI receiver.
2251 * - 11 - Synchronous with another SAI transmitter.
2254 #define BP_I2S_RCR2_SYNC (30U) /*!< Bit position for I2S_RCR2_SYNC. */
2255 #define BM_I2S_RCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */
2256 #define BS_I2S_RCR2_SYNC (2U) /*!< Bit field size in bits for I2S_RCR2_SYNC. */
2258 /*! @brief Read current value of the I2S_RCR2_SYNC field. */
2259 #define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
2261 /*! @brief Format value for bitfield I2S_RCR2_SYNC. */
2262 #define BF_I2S_RCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC)
2264 /*! @brief Set the SYNC field to a new value. */
2265 #define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
2268 /*******************************************************************************
2269 * HW_I2S_RCR3 - SAI Receive Configuration 3 Register
2270 ******************************************************************************/
2273 * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
2275 * Reset value: 0x00000000U
2277 * This register must not be altered when RCSR[RE] is set.
2279 typedef union _hw_i2s_rcr3
2282 struct _hw_i2s_rcr3_bitfields
2284 uint32_t WDFL
: 5; /*!< [4:0] Word Flag Configuration */
2285 uint32_t RESERVED0
: 11; /*!< [15:5] */
2286 uint32_t RCE
: 2; /*!< [17:16] Receive Channel Enable */
2287 uint32_t RESERVED1
: 14; /*!< [31:18] */
2292 * @name Constants and macros for entire I2S_RCR3 register
2295 #define HW_I2S_RCR3_ADDR(x) ((x) + 0x8CU)
2297 #define HW_I2S_RCR3(x) (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
2298 #define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
2299 #define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
2300 #define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) | (v)))
2301 #define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
2302 #define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
2306 * Constants & macros for individual I2S_RCR3 bitfields
2310 * @name Register I2S_RCR3, field WDFL[4:0] (RW)
2312 * Configures which word the start of word flag is set. The value written should
2313 * be one less than the word number (for example, write zero to configure for
2314 * the first word in the frame). When configured to a value greater than the Frame
2315 * Size field, then the start of word flag is never set.
2318 #define BP_I2S_RCR3_WDFL (0U) /*!< Bit position for I2S_RCR3_WDFL. */
2319 #define BM_I2S_RCR3_WDFL (0x0000001FU) /*!< Bit mask for I2S_RCR3_WDFL. */
2320 #define BS_I2S_RCR3_WDFL (5U) /*!< Bit field size in bits for I2S_RCR3_WDFL. */
2322 /*! @brief Read current value of the I2S_RCR3_WDFL field. */
2323 #define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
2325 /*! @brief Format value for bitfield I2S_RCR3_WDFL. */
2326 #define BF_I2S_RCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL)
2328 /*! @brief Set the WDFL field to a new value. */
2329 #define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
2333 * @name Register I2S_RCR3, field RCE[17:16] (RW)
2335 * Enables the corresponding data channel for receive operation. A channel must
2336 * be enabled before its FIFO is accessed.
2339 * - 0 - Receive data channel N is disabled.
2340 * - 1 - Receive data channel N is enabled.
2343 #define BP_I2S_RCR3_RCE (16U) /*!< Bit position for I2S_RCR3_RCE. */
2344 #define BM_I2S_RCR3_RCE (0x00030000U) /*!< Bit mask for I2S_RCR3_RCE. */
2345 #define BS_I2S_RCR3_RCE (2U) /*!< Bit field size in bits for I2S_RCR3_RCE. */
2347 /*! @brief Read current value of the I2S_RCR3_RCE field. */
2348 #define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE)
2350 /*! @brief Format value for bitfield I2S_RCR3_RCE. */
2351 #define BF_I2S_RCR3_RCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE)
2353 /*! @brief Set the RCE field to a new value. */
2354 #define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v)))
2357 /*******************************************************************************
2358 * HW_I2S_RCR4 - SAI Receive Configuration 4 Register
2359 ******************************************************************************/
2362 * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
2364 * Reset value: 0x00000000U
2366 * This register must not be altered when RCSR[RE] is set.
2368 typedef union _hw_i2s_rcr4
2371 struct _hw_i2s_rcr4_bitfields
2373 uint32_t FSD
: 1; /*!< [0] Frame Sync Direction */
2374 uint32_t FSP
: 1; /*!< [1] Frame Sync Polarity */
2375 uint32_t RESERVED0
: 1; /*!< [2] */
2376 uint32_t FSE
: 1; /*!< [3] Frame Sync Early */
2377 uint32_t MF
: 1; /*!< [4] MSB First */
2378 uint32_t RESERVED1
: 3; /*!< [7:5] */
2379 uint32_t SYWD
: 5; /*!< [12:8] Sync Width */
2380 uint32_t RESERVED2
: 3; /*!< [15:13] */
2381 uint32_t FRSZ
: 5; /*!< [20:16] Frame Size */
2382 uint32_t RESERVED3
: 11; /*!< [31:21] */
2387 * @name Constants and macros for entire I2S_RCR4 register
2390 #define HW_I2S_RCR4_ADDR(x) ((x) + 0x90U)
2392 #define HW_I2S_RCR4(x) (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
2393 #define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
2394 #define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
2395 #define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) | (v)))
2396 #define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
2397 #define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
2401 * Constants & macros for individual I2S_RCR4 bitfields
2405 * @name Register I2S_RCR4, field FSD[0] (RW)
2407 * Configures the direction of the frame sync.
2410 * - 0 - Frame Sync is generated externally in Slave mode.
2411 * - 1 - Frame Sync is generated internally in Master mode.
2414 #define BP_I2S_RCR4_FSD (0U) /*!< Bit position for I2S_RCR4_FSD. */
2415 #define BM_I2S_RCR4_FSD (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */
2416 #define BS_I2S_RCR4_FSD (1U) /*!< Bit field size in bits for I2S_RCR4_FSD. */
2418 /*! @brief Read current value of the I2S_RCR4_FSD field. */
2419 #define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
2421 /*! @brief Format value for bitfield I2S_RCR4_FSD. */
2422 #define BF_I2S_RCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD)
2424 /*! @brief Set the FSD field to a new value. */
2425 #define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
2429 * @name Register I2S_RCR4, field FSP[1] (RW)
2431 * Configures the polarity of the frame sync.
2434 * - 0 - Frame sync is active high.
2435 * - 1 - Frame sync is active low.
2438 #define BP_I2S_RCR4_FSP (1U) /*!< Bit position for I2S_RCR4_FSP. */
2439 #define BM_I2S_RCR4_FSP (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */
2440 #define BS_I2S_RCR4_FSP (1U) /*!< Bit field size in bits for I2S_RCR4_FSP. */
2442 /*! @brief Read current value of the I2S_RCR4_FSP field. */
2443 #define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
2445 /*! @brief Format value for bitfield I2S_RCR4_FSP. */
2446 #define BF_I2S_RCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP)
2448 /*! @brief Set the FSP field to a new value. */
2449 #define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
2453 * @name Register I2S_RCR4, field FSE[3] (RW)
2456 * - 0 - Frame sync asserts with the first bit of the frame.
2457 * - 1 - Frame sync asserts one bit before the first bit of the frame.
2460 #define BP_I2S_RCR4_FSE (3U) /*!< Bit position for I2S_RCR4_FSE. */
2461 #define BM_I2S_RCR4_FSE (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */
2462 #define BS_I2S_RCR4_FSE (1U) /*!< Bit field size in bits for I2S_RCR4_FSE. */
2464 /*! @brief Read current value of the I2S_RCR4_FSE field. */
2465 #define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
2467 /*! @brief Format value for bitfield I2S_RCR4_FSE. */
2468 #define BF_I2S_RCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE)
2470 /*! @brief Set the FSE field to a new value. */
2471 #define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
2475 * @name Register I2S_RCR4, field MF[4] (RW)
2477 * Configures whether the LSB or the MSB is received first.
2480 * - 0 - LSB is received first.
2481 * - 1 - MSB is received first.
2484 #define BP_I2S_RCR4_MF (4U) /*!< Bit position for I2S_RCR4_MF. */
2485 #define BM_I2S_RCR4_MF (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */
2486 #define BS_I2S_RCR4_MF (1U) /*!< Bit field size in bits for I2S_RCR4_MF. */
2488 /*! @brief Read current value of the I2S_RCR4_MF field. */
2489 #define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
2491 /*! @brief Format value for bitfield I2S_RCR4_MF. */
2492 #define BF_I2S_RCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF)
2494 /*! @brief Set the MF field to a new value. */
2495 #define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
2499 * @name Register I2S_RCR4, field SYWD[12:8] (RW)
2501 * Configures the length of the frame sync in number of bit clocks. The value
2502 * written must be one less than the number of bit clocks. For example, write 0 for
2503 * the frame sync to assert for one bit clock only. The sync width cannot be
2504 * configured longer than the first word of the frame.
2507 #define BP_I2S_RCR4_SYWD (8U) /*!< Bit position for I2S_RCR4_SYWD. */
2508 #define BM_I2S_RCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */
2509 #define BS_I2S_RCR4_SYWD (5U) /*!< Bit field size in bits for I2S_RCR4_SYWD. */
2511 /*! @brief Read current value of the I2S_RCR4_SYWD field. */
2512 #define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
2514 /*! @brief Format value for bitfield I2S_RCR4_SYWD. */
2515 #define BF_I2S_RCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD)
2517 /*! @brief Set the SYWD field to a new value. */
2518 #define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
2522 * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
2524 * Configures the number of words in each frame. The value written must be one
2525 * less than the number of words in the frame. For example, write 0 for one word
2526 * per frame. The maximum supported frame size is 32 words.
2529 #define BP_I2S_RCR4_FRSZ (16U) /*!< Bit position for I2S_RCR4_FRSZ. */
2530 #define BM_I2S_RCR4_FRSZ (0x001F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */
2531 #define BS_I2S_RCR4_FRSZ (5U) /*!< Bit field size in bits for I2S_RCR4_FRSZ. */
2533 /*! @brief Read current value of the I2S_RCR4_FRSZ field. */
2534 #define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
2536 /*! @brief Format value for bitfield I2S_RCR4_FRSZ. */
2537 #define BF_I2S_RCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ)
2539 /*! @brief Set the FRSZ field to a new value. */
2540 #define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
2543 /*******************************************************************************
2544 * HW_I2S_RCR5 - SAI Receive Configuration 5 Register
2545 ******************************************************************************/
2548 * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
2550 * Reset value: 0x00000000U
2552 * This register must not be altered when RCSR[RE] is set.
2554 typedef union _hw_i2s_rcr5
2557 struct _hw_i2s_rcr5_bitfields
2559 uint32_t RESERVED0
: 8; /*!< [7:0] */
2560 uint32_t FBT
: 5; /*!< [12:8] First Bit Shifted */
2561 uint32_t RESERVED1
: 3; /*!< [15:13] */
2562 uint32_t W0W
: 5; /*!< [20:16] Word 0 Width */
2563 uint32_t RESERVED2
: 3; /*!< [23:21] */
2564 uint32_t WNW
: 5; /*!< [28:24] Word N Width */
2565 uint32_t RESERVED3
: 3; /*!< [31:29] */
2570 * @name Constants and macros for entire I2S_RCR5 register
2573 #define HW_I2S_RCR5_ADDR(x) ((x) + 0x94U)
2575 #define HW_I2S_RCR5(x) (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
2576 #define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
2577 #define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
2578 #define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) | (v)))
2579 #define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
2580 #define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
2584 * Constants & macros for individual I2S_RCR5 bitfields
2588 * @name Register I2S_RCR5, field FBT[12:8] (RW)
2590 * Configures the bit index for the first bit received for each word in the
2591 * frame. If configured for MSB First, the index of the next bit received is one less
2592 * than the current bit received. If configured for LSB First, the index of the
2593 * next bit received is one more than the current bit received. The value written
2594 * must be greater than or equal to the word width when configured for MSB
2595 * First. The value written must be less than or equal to 31-word width when
2596 * configured for LSB First.
2599 #define BP_I2S_RCR5_FBT (8U) /*!< Bit position for I2S_RCR5_FBT. */
2600 #define BM_I2S_RCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */
2601 #define BS_I2S_RCR5_FBT (5U) /*!< Bit field size in bits for I2S_RCR5_FBT. */
2603 /*! @brief Read current value of the I2S_RCR5_FBT field. */
2604 #define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
2606 /*! @brief Format value for bitfield I2S_RCR5_FBT. */
2607 #define BF_I2S_RCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT)
2609 /*! @brief Set the FBT field to a new value. */
2610 #define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
2614 * @name Register I2S_RCR5, field W0W[20:16] (RW)
2616 * Configures the number of bits in the first word in each frame. The value
2617 * written must be one less than the number of bits in the first word. Word width of
2618 * less than 8 bits is not supported if there is only one word per frame.
2621 #define BP_I2S_RCR5_W0W (16U) /*!< Bit position for I2S_RCR5_W0W. */
2622 #define BM_I2S_RCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */
2623 #define BS_I2S_RCR5_W0W (5U) /*!< Bit field size in bits for I2S_RCR5_W0W. */
2625 /*! @brief Read current value of the I2S_RCR5_W0W field. */
2626 #define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
2628 /*! @brief Format value for bitfield I2S_RCR5_W0W. */
2629 #define BF_I2S_RCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W)
2631 /*! @brief Set the W0W field to a new value. */
2632 #define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
2636 * @name Register I2S_RCR5, field WNW[28:24] (RW)
2638 * Configures the number of bits in each word, for each word except the first in
2639 * the frame. The value written must be one less than the number of bits per
2640 * word. Word width of less than 8 bits is not supported.
2643 #define BP_I2S_RCR5_WNW (24U) /*!< Bit position for I2S_RCR5_WNW. */
2644 #define BM_I2S_RCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */
2645 #define BS_I2S_RCR5_WNW (5U) /*!< Bit field size in bits for I2S_RCR5_WNW. */
2647 /*! @brief Read current value of the I2S_RCR5_WNW field. */
2648 #define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
2650 /*! @brief Format value for bitfield I2S_RCR5_WNW. */
2651 #define BF_I2S_RCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW)
2653 /*! @brief Set the WNW field to a new value. */
2654 #define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
2657 /*******************************************************************************
2658 * HW_I2S_RDRn - SAI Receive Data Register
2659 ******************************************************************************/
2662 * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
2664 * Reset value: 0x00000000U
2666 * Reading this register introduces one additional peripheral clock wait state
2669 typedef union _hw_i2s_rdrn
2672 struct _hw_i2s_rdrn_bitfields
2674 uint32_t RDR
: 32; /*!< [31:0] Receive Data Register */
2679 * @name Constants and macros for entire I2S_RDRn register
2682 #define HW_I2S_RDRn_COUNT (2U)
2684 #define HW_I2S_RDRn_ADDR(x, n) ((x) + 0xA0U + (0x4U * (n)))
2686 #define HW_I2S_RDRn(x, n) (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
2687 #define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
2691 * Constants & macros for individual I2S_RDRn bitfields
2695 * @name Register I2S_RDRn, field RDR[31:0] (RO)
2697 * The corresponding RCR3[RCE] bit must be set before accessing the channel's
2698 * receive data register. Reads from this register when the receive FIFO is not
2699 * empty will return the data from the top of the receive FIFO. Reads from this
2700 * register when the receive FIFO is empty are ignored.
2703 #define BP_I2S_RDRn_RDR (0U) /*!< Bit position for I2S_RDRn_RDR. */
2704 #define BM_I2S_RDRn_RDR (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */
2705 #define BS_I2S_RDRn_RDR (32U) /*!< Bit field size in bits for I2S_RDRn_RDR. */
2707 /*! @brief Read current value of the I2S_RDRn_RDR field. */
2708 #define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
2711 /*******************************************************************************
2712 * HW_I2S_RFRn - SAI Receive FIFO Register
2713 ******************************************************************************/
2716 * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
2718 * Reset value: 0x00000000U
2720 * The MSB of the read and write pointers is used to distinguish between FIFO
2721 * full and empty conditions. If the read and write pointers are identical, then
2722 * the FIFO is empty. If the read and write pointers are identical except for the
2723 * MSB, then the FIFO is full.
2725 typedef union _hw_i2s_rfrn
2728 struct _hw_i2s_rfrn_bitfields
2730 uint32_t RFP
: 4; /*!< [3:0] Read FIFO Pointer */
2731 uint32_t RESERVED0
: 12; /*!< [15:4] */
2732 uint32_t WFP
: 4; /*!< [19:16] Write FIFO Pointer */
2733 uint32_t RESERVED1
: 12; /*!< [31:20] */
2738 * @name Constants and macros for entire I2S_RFRn register
2741 #define HW_I2S_RFRn_COUNT (2U)
2743 #define HW_I2S_RFRn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n)))
2745 #define HW_I2S_RFRn(x, n) (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
2746 #define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
2750 * Constants & macros for individual I2S_RFRn bitfields
2754 * @name Register I2S_RFRn, field RFP[3:0] (RO)
2756 * FIFO read pointer for receive data channel.
2759 #define BP_I2S_RFRn_RFP (0U) /*!< Bit position for I2S_RFRn_RFP. */
2760 #define BM_I2S_RFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */
2761 #define BS_I2S_RFRn_RFP (4U) /*!< Bit field size in bits for I2S_RFRn_RFP. */
2763 /*! @brief Read current value of the I2S_RFRn_RFP field. */
2764 #define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
2768 * @name Register I2S_RFRn, field WFP[19:16] (RO)
2770 * FIFO write pointer for receive data channel.
2773 #define BP_I2S_RFRn_WFP (16U) /*!< Bit position for I2S_RFRn_WFP. */
2774 #define BM_I2S_RFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */
2775 #define BS_I2S_RFRn_WFP (4U) /*!< Bit field size in bits for I2S_RFRn_WFP. */
2777 /*! @brief Read current value of the I2S_RFRn_WFP field. */
2778 #define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
2781 /*******************************************************************************
2782 * HW_I2S_RMR - SAI Receive Mask Register
2783 ******************************************************************************/
2786 * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
2788 * Reset value: 0x00000000U
2790 * This register is double-buffered and updates: When RCSR[RE] is first set At
2791 * the end of each frame This allows the masked words in each frame to change from
2794 typedef union _hw_i2s_rmr
2797 struct _hw_i2s_rmr_bitfields
2799 uint32_t RWM
: 32; /*!< [31:0] Receive Word Mask */
2804 * @name Constants and macros for entire I2S_RMR register
2807 #define HW_I2S_RMR_ADDR(x) ((x) + 0xE0U)
2809 #define HW_I2S_RMR(x) (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
2810 #define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
2811 #define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
2812 #define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) | (v)))
2813 #define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
2814 #define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
2818 * Constants & macros for individual I2S_RMR bitfields
2822 * @name Register I2S_RMR, field RWM[31:0] (RW)
2824 * Configures whether the receive word is masked (received data ignored and not
2825 * written to receive FIFO) for the corresponding word in the frame.
2828 * - 0 - Word N is enabled.
2829 * - 1 - Word N is masked.
2832 #define BP_I2S_RMR_RWM (0U) /*!< Bit position for I2S_RMR_RWM. */
2833 #define BM_I2S_RMR_RWM (0xFFFFFFFFU) /*!< Bit mask for I2S_RMR_RWM. */
2834 #define BS_I2S_RMR_RWM (32U) /*!< Bit field size in bits for I2S_RMR_RWM. */
2836 /*! @brief Read current value of the I2S_RMR_RWM field. */
2837 #define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U)
2839 /*! @brief Format value for bitfield I2S_RMR_RWM. */
2840 #define BF_I2S_RMR_RWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM)
2842 /*! @brief Set the RWM field to a new value. */
2843 #define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
2846 /*******************************************************************************
2847 * HW_I2S_MCR - SAI MCLK Control Register
2848 ******************************************************************************/
2851 * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
2853 * Reset value: 0x00000000U
2855 * The MCLK Control Register (MCR) controls the clock source and direction of
2856 * the audio master clock.
2858 typedef union _hw_i2s_mcr
2861 struct _hw_i2s_mcr_bitfields
2863 uint32_t RESERVED0
: 24; /*!< [23:0] */
2864 uint32_t MICS
: 2; /*!< [25:24] MCLK Input Clock Select */
2865 uint32_t RESERVED1
: 4; /*!< [29:26] */
2866 uint32_t MOE
: 1; /*!< [30] MCLK Output Enable */
2867 uint32_t DUF
: 1; /*!< [31] Divider Update Flag */
2872 * @name Constants and macros for entire I2S_MCR register
2875 #define HW_I2S_MCR_ADDR(x) ((x) + 0x100U)
2877 #define HW_I2S_MCR(x) (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
2878 #define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
2879 #define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
2880 #define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) | (v)))
2881 #define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
2882 #define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
2886 * Constants & macros for individual I2S_MCR bitfields
2890 * @name Register I2S_MCR, field MICS[25:24] (RW)
2892 * Selects the clock input to the MCLK divider. This field cannot be changed
2893 * while the MCLK divider is enabled. See the chip configuration details for
2894 * information about the connections to these inputs.
2897 * - 00 - MCLK divider input clock 0 selected.
2898 * - 01 - MCLK divider input clock 1 selected.
2899 * - 10 - MCLK divider input clock 2 selected.
2900 * - 11 - MCLK divider input clock 3 selected.
2903 #define BP_I2S_MCR_MICS (24U) /*!< Bit position for I2S_MCR_MICS. */
2904 #define BM_I2S_MCR_MICS (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */
2905 #define BS_I2S_MCR_MICS (2U) /*!< Bit field size in bits for I2S_MCR_MICS. */
2907 /*! @brief Read current value of the I2S_MCR_MICS field. */
2908 #define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
2910 /*! @brief Format value for bitfield I2S_MCR_MICS. */
2911 #define BF_I2S_MCR_MICS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS)
2913 /*! @brief Set the MICS field to a new value. */
2914 #define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
2918 * @name Register I2S_MCR, field MOE[30] (RW)
2920 * Enables the MCLK divider and configures the MCLK signal pin as an output.
2921 * When software clears this field, it remains set until the MCLK divider is fully
2925 * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
2927 * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
2928 * the MCLK divider is enabled.
2931 #define BP_I2S_MCR_MOE (30U) /*!< Bit position for I2S_MCR_MOE. */
2932 #define BM_I2S_MCR_MOE (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */
2933 #define BS_I2S_MCR_MOE (1U) /*!< Bit field size in bits for I2S_MCR_MOE. */
2935 /*! @brief Read current value of the I2S_MCR_MOE field. */
2936 #define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
2938 /*! @brief Format value for bitfield I2S_MCR_MOE. */
2939 #define BF_I2S_MCR_MOE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE)
2941 /*! @brief Set the MOE field to a new value. */
2942 #define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
2946 * @name Register I2S_MCR, field DUF[31] (RO)
2948 * Provides the status of on-the-fly updates to the MCLK divider ratio.
2951 * - 0 - MCLK divider ratio is not being updated currently.
2952 * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
2953 * divider ratio are blocked while this flag remains set.
2956 #define BP_I2S_MCR_DUF (31U) /*!< Bit position for I2S_MCR_DUF. */
2957 #define BM_I2S_MCR_DUF (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */
2958 #define BS_I2S_MCR_DUF (1U) /*!< Bit field size in bits for I2S_MCR_DUF. */
2960 /*! @brief Read current value of the I2S_MCR_DUF field. */
2961 #define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
2964 /*******************************************************************************
2965 * HW_I2S_MDR - SAI MCLK Divide Register
2966 ******************************************************************************/
2969 * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
2971 * Reset value: 0x00000000U
2973 * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
2974 * MDR can be changed when the MCLK divider clock is enabled, additional writes
2975 * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
2976 * divided clock is disabled do not set MCR[DUF].
2978 typedef union _hw_i2s_mdr
2981 struct _hw_i2s_mdr_bitfields
2983 uint32_t DIVIDE
: 12; /*!< [11:0] MCLK Divide */
2984 uint32_t FRACT
: 8; /*!< [19:12] MCLK Fraction */
2985 uint32_t RESERVED0
: 12; /*!< [31:20] */
2990 * @name Constants and macros for entire I2S_MDR register
2993 #define HW_I2S_MDR_ADDR(x) ((x) + 0x104U)
2995 #define HW_I2S_MDR(x) (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
2996 #define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
2997 #define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
2998 #define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) | (v)))
2999 #define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
3000 #define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
3004 * Constants & macros for individual I2S_MDR bitfields
3008 * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
3010 * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
3011 * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
3015 #define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */
3016 #define BM_I2S_MDR_DIVIDE (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */
3017 #define BS_I2S_MDR_DIVIDE (12U) /*!< Bit field size in bits for I2S_MDR_DIVIDE. */
3019 /*! @brief Read current value of the I2S_MDR_DIVIDE field. */
3020 #define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
3022 /*! @brief Format value for bitfield I2S_MDR_DIVIDE. */
3023 #define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE)
3025 /*! @brief Set the DIVIDE field to a new value. */
3026 #define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
3030 * @name Register I2S_MDR, field FRACT[19:12] (RW)
3032 * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
3033 * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
3037 #define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */
3038 #define BM_I2S_MDR_FRACT (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */
3039 #define BS_I2S_MDR_FRACT (8U) /*!< Bit field size in bits for I2S_MDR_FRACT. */
3041 /*! @brief Read current value of the I2S_MDR_FRACT field. */
3042 #define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
3044 /*! @brief Format value for bitfield I2S_MDR_FRACT. */
3045 #define BF_I2S_MDR_FRACT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT)
3047 /*! @brief Set the FRACT field to a new value. */
3048 #define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
3051 /*******************************************************************************
3052 * hw_i2s_t - module struct
3053 ******************************************************************************/
3055 * @brief All I2S module registers.
3058 typedef struct _hw_i2s
3060 __IO hw_i2s_tcsr_t TCSR
; /*!< [0x0] SAI Transmit Control Register */
3061 __IO hw_i2s_tcr1_t TCR1
; /*!< [0x4] SAI Transmit Configuration 1 Register */
3062 __IO hw_i2s_tcr2_t TCR2
; /*!< [0x8] SAI Transmit Configuration 2 Register */
3063 __IO hw_i2s_tcr3_t TCR3
; /*!< [0xC] SAI Transmit Configuration 3 Register */
3064 __IO hw_i2s_tcr4_t TCR4
; /*!< [0x10] SAI Transmit Configuration 4 Register */
3065 __IO hw_i2s_tcr5_t TCR5
; /*!< [0x14] SAI Transmit Configuration 5 Register */
3066 uint8_t _reserved0
[8];
3067 __O hw_i2s_tdrn_t TDRn
[2]; /*!< [0x20] SAI Transmit Data Register */
3068 uint8_t _reserved1
[24];
3069 __I hw_i2s_tfrn_t TFRn
[2]; /*!< [0x40] SAI Transmit FIFO Register */
3070 uint8_t _reserved2
[24];
3071 __IO hw_i2s_tmr_t TMR
; /*!< [0x60] SAI Transmit Mask Register */
3072 uint8_t _reserved3
[28];
3073 __IO hw_i2s_rcsr_t RCSR
; /*!< [0x80] SAI Receive Control Register */
3074 __IO hw_i2s_rcr1_t RCR1
; /*!< [0x84] SAI Receive Configuration 1 Register */
3075 __IO hw_i2s_rcr2_t RCR2
; /*!< [0x88] SAI Receive Configuration 2 Register */
3076 __IO hw_i2s_rcr3_t RCR3
; /*!< [0x8C] SAI Receive Configuration 3 Register */
3077 __IO hw_i2s_rcr4_t RCR4
; /*!< [0x90] SAI Receive Configuration 4 Register */
3078 __IO hw_i2s_rcr5_t RCR5
; /*!< [0x94] SAI Receive Configuration 5 Register */
3079 uint8_t _reserved4
[8];
3080 __I hw_i2s_rdrn_t RDRn
[2]; /*!< [0xA0] SAI Receive Data Register */
3081 uint8_t _reserved5
[24];
3082 __I hw_i2s_rfrn_t RFRn
[2]; /*!< [0xC0] SAI Receive FIFO Register */
3083 uint8_t _reserved6
[24];
3084 __IO hw_i2s_rmr_t RMR
; /*!< [0xE0] SAI Receive Mask Register */
3085 uint8_t _reserved7
[28];
3086 __IO hw_i2s_mcr_t MCR
; /*!< [0x100] SAI MCLK Control Register */
3087 __IO hw_i2s_mdr_t MDR
; /*!< [0x104] SAI MCLK Divide Register */
3091 /*! @brief Macro to access all I2S registers. */
3092 /*! @param x I2S module instance base address. */
3093 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
3094 * use the '&' operator, like <code>&HW_I2S(I2S0_BASE)</code>. */
3095 #define HW_I2S(x) (*(hw_i2s_t *)(x))
3097 #endif /* __HW_I2S_REGISTERS_H__ */