tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcm.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_MCM_REGISTERS_H__
  81 #define __HW_MCM_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 MCM
  88  *
  89  * Core Platform Miscellaneous Control Module
  90  *
  91  * Registers defined in this header file:
  92  * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
  93  * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
  94  * - HW_MCM_CR - Control Register
  95  * - HW_MCM_ISCR - Interrupt Status Register
  96  * - HW_MCM_ETBCC - ETB Counter Control register
  97  * - HW_MCM_ETBRL - ETB Reload register
  98  * - HW_MCM_ETBCNT - ETB Counter Value register
  99  * - HW_MCM_PID - Process ID register
 100  *
 101  * - hw_mcm_t - Struct containing all module registers.
 102  */
 103
 104 #define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
 105
 106 /*******************************************************************************
 107  * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
 108  ******************************************************************************/
 109
 110 /*!
 111  * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
 112  *
 113  * Reset value: 0x001FU
 114  *
 115  * PLASC is a 16-bit read-only register identifying the presence/absence of bus
 116  * slave connections to the device's crossbar switch.
 117  */
 118 typedef union _hw_mcm_plasc
 119 {
 120     uint16_t U;
 121     struct _hw_mcm_plasc_bitfields
 122     {
 123         uint16_t ASC : 8;              /*!< [7:0] Each bit in the ASC field indicates
 124                                         * whether there is a corresponding connection to the crossbar switch's slave
 125                                         * input port. */
 126         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
 127     } B;
 128 } hw_mcm_plasc_t;
 129
 130 /*!
 131  * @name Constants and macros for entire MCM_PLASC register
 132  */
 133 /*@{*/
 134 #define HW_MCM_PLASC_ADDR(x)     ((x) + 0x8U)
 135
 136 #define HW_MCM_PLASC(x)          (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
 137 #define HW_MCM_PLASC_RD(x)       (HW_MCM_PLASC(x).U)
 138 /*@}*/
 139
 140 /*
 141  * Constants & macros for individual MCM_PLASC bitfields
 142  */
 143
 144 /*!
 145  * @name Register MCM_PLASC, field ASC[7:0] (RO)
 146  *
 147  * Values:
 148  * - 0 - A bus slave connection to AXBS input port n is absent
 149  * - 1 - A bus slave connection to AXBS input port n is present
 150  */
 151 /*@{*/
 152 #define BP_MCM_PLASC_ASC     (0U)          /*!< Bit position for MCM_PLASC_ASC. */
 153 #define BM_MCM_PLASC_ASC     (0x00FFU)     /*!< Bit mask for MCM_PLASC_ASC. */
 154 #define BS_MCM_PLASC_ASC     (8U)          /*!< Bit field size in bits for MCM_PLASC_ASC. */
 155
 156 /*! @brief Read current value of the MCM_PLASC_ASC field. */
 157 #define BR_MCM_PLASC_ASC(x)  (HW_MCM_PLASC(x).B.ASC)
 158 /*@}*/
 159
 160 /*******************************************************************************
 161  * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
 162  ******************************************************************************/
 163
 164 /*!
 165  * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
 166  *
 167  * Reset value: 0x0037U
 168  *
 169  * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
 170  * master connections to the device's crossbar switch.
 171  */
 172 typedef union _hw_mcm_plamc
 173 {
 174     uint16_t U;
 175     struct _hw_mcm_plamc_bitfields
 176     {
 177         uint16_t AMC : 8;              /*!< [7:0] Each bit in the AMC field indicates
 178                                         * whether there is a corresponding connection to the AXBS master input port. */
 179         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
 180     } B;
 181 } hw_mcm_plamc_t;
 182
 183 /*!
 184  * @name Constants and macros for entire MCM_PLAMC register
 185  */
 186 /*@{*/
 187 #define HW_MCM_PLAMC_ADDR(x)     ((x) + 0xAU)
 188
 189 #define HW_MCM_PLAMC(x)          (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
 190 #define HW_MCM_PLAMC_RD(x)       (HW_MCM_PLAMC(x).U)
 191 /*@}*/
 192
 193 /*
 194  * Constants & macros for individual MCM_PLAMC bitfields
 195  */
 196
 197 /*!
 198  * @name Register MCM_PLAMC, field AMC[7:0] (RO)
 199  *
 200  * Values:
 201  * - 0 - A bus master connection to AXBS input port n is absent
 202  * - 1 - A bus master connection to AXBS input port n is present
 203  */
 204 /*@{*/
 205 #define BP_MCM_PLAMC_AMC     (0U)          /*!< Bit position for MCM_PLAMC_AMC. */
 206 #define BM_MCM_PLAMC_AMC     (0x00FFU)     /*!< Bit mask for MCM_PLAMC_AMC. */
 207 #define BS_MCM_PLAMC_AMC     (8U)          /*!< Bit field size in bits for MCM_PLAMC_AMC. */
 208
 209 /*! @brief Read current value of the MCM_PLAMC_AMC field. */
 210 #define BR_MCM_PLAMC_AMC(x)  (HW_MCM_PLAMC(x).B.AMC)
 211 /*@}*/
 212
 213 /*******************************************************************************
 214  * HW_MCM_CR - Control Register
 215  ******************************************************************************/
 216
 217 /*!
 218  * @brief HW_MCM_CR - Control Register (RW)
 219  *
 220  * Reset value: 0x00000000U
 221  *
 222  * CR defines the arbitration and protection schemes for the two system RAM
 223  * arrays.
 224  */
 225 typedef union _hw_mcm_cr
 226 {
 227     uint32_t U;
 228     struct _hw_mcm_cr_bitfields
 229     {
 230         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
 231         uint32_t SRAMUAP : 2;          /*!< [25:24] SRAM_U arbitration priority */
 232         uint32_t SRAMUWP : 1;          /*!< [26] SRAM_U write protect */
 233         uint32_t RESERVED1 : 1;        /*!< [27]  */
 234         uint32_t SRAMLAP : 2;          /*!< [29:28] SRAM_L arbitration priority */
 235         uint32_t SRAMLWP : 1;          /*!< [30] SRAM_L Write Protect */
 236         uint32_t RESERVED2 : 1;        /*!< [31]  */
 237     } B;
 238 } hw_mcm_cr_t;
 239
 240 /*!
 241  * @name Constants and macros for entire MCM_CR register
 242  */
 243 /*@{*/
 244 #define HW_MCM_CR_ADDR(x)        ((x) + 0xCU)
 245
 246 #define HW_MCM_CR(x)             (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR(x))
 247 #define HW_MCM_CR_RD(x)          (HW_MCM_CR(x).U)
 248 #define HW_MCM_CR_WR(x, v)       (HW_MCM_CR(x).U = (v))
 249 #define HW_MCM_CR_SET(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) |  (v)))
 250 #define HW_MCM_CR_CLR(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) & ~(v)))
 251 #define HW_MCM_CR_TOG(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) ^  (v)))
 252 /*@}*/
 253
 254 /*
 255  * Constants & macros for individual MCM_CR bitfields
 256  */
 257
 258 /*!
 259  * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
 260  *
 261  * Defines the arbitration scheme and priority for the processor and SRAM
 262  * backdoor accesses to the SRAM_U array.
 263  *
 264  * Values:
 265  * - 00 - Round robin
 266  * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
 267  * - 10 - Fixed priority. Processor has highest, backdoor has lowest
 268  * - 11 - Fixed priority. Backdoor has highest, processor has lowest
 269  */
 270 /*@{*/
 271 #define BP_MCM_CR_SRAMUAP    (24U)         /*!< Bit position for MCM_CR_SRAMUAP. */
 272 #define BM_MCM_CR_SRAMUAP    (0x03000000U) /*!< Bit mask for MCM_CR_SRAMUAP. */
 273 #define BS_MCM_CR_SRAMUAP    (2U)          /*!< Bit field size in bits for MCM_CR_SRAMUAP. */
 274
 275 /*! @brief Read current value of the MCM_CR_SRAMUAP field. */
 276 #define BR_MCM_CR_SRAMUAP(x) (HW_MCM_CR(x).B.SRAMUAP)
 277
 278 /*! @brief Format value for bitfield MCM_CR_SRAMUAP. */
 279 #define BF_MCM_CR_SRAMUAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUAP) & BM_MCM_CR_SRAMUAP)
 280
 281 /*! @brief Set the SRAMUAP field to a new value. */
 282 #define BW_MCM_CR_SRAMUAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
 283 /*@}*/
 284
 285 /*!
 286  * @name Register MCM_CR, field SRAMUWP[26] (RW)
 287  *
 288  * When this bit is set, writes to SRAM_U array generates a bus error.
 289  */
 290 /*@{*/
 291 #define BP_MCM_CR_SRAMUWP    (26U)         /*!< Bit position for MCM_CR_SRAMUWP. */
 292 #define BM_MCM_CR_SRAMUWP    (0x04000000U) /*!< Bit mask for MCM_CR_SRAMUWP. */
 293 #define BS_MCM_CR_SRAMUWP    (1U)          /*!< Bit field size in bits for MCM_CR_SRAMUWP. */
 294
 295 /*! @brief Read current value of the MCM_CR_SRAMUWP field. */
 296 #define BR_MCM_CR_SRAMUWP(x) (HW_MCM_CR(x).B.SRAMUWP)
 297
 298 /*! @brief Format value for bitfield MCM_CR_SRAMUWP. */
 299 #define BF_MCM_CR_SRAMUWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUWP) & BM_MCM_CR_SRAMUWP)
 300
 301 /*! @brief Set the SRAMUWP field to a new value. */
 302 #define BW_MCM_CR_SRAMUWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUWP) | BF_MCM_CR_SRAMUWP(v)))
 303 /*@}*/
 304
 305 /*!
 306  * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
 307  *
 308  * Defines the arbitration scheme and priority for the processor and SRAM
 309  * backdoor accesses to the SRAM_L array.
 310  *
 311  * Values:
 312  * - 00 - Round robin
 313  * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
 314  * - 10 - Fixed priority. Processor has highest, backdoor has lowest
 315  * - 11 - Fixed priority. Backdoor has highest, processor has lowest
 316  */
 317 /*@{*/
 318 #define BP_MCM_CR_SRAMLAP    (28U)         /*!< Bit position for MCM_CR_SRAMLAP. */
 319 #define BM_MCM_CR_SRAMLAP    (0x30000000U) /*!< Bit mask for MCM_CR_SRAMLAP. */
 320 #define BS_MCM_CR_SRAMLAP    (2U)          /*!< Bit field size in bits for MCM_CR_SRAMLAP. */
 321
 322 /*! @brief Read current value of the MCM_CR_SRAMLAP field. */
 323 #define BR_MCM_CR_SRAMLAP(x) (HW_MCM_CR(x).B.SRAMLAP)
 324
 325 /*! @brief Format value for bitfield MCM_CR_SRAMLAP. */
 326 #define BF_MCM_CR_SRAMLAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLAP) & BM_MCM_CR_SRAMLAP)
 327
 328 /*! @brief Set the SRAMLAP field to a new value. */
 329 #define BW_MCM_CR_SRAMLAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
 330 /*@}*/
 331
 332 /*!
 333  * @name Register MCM_CR, field SRAMLWP[30] (RW)
 334  *
 335  * When this bit is set, writes to SRAM_L array generates a bus error.
 336  */
 337 /*@{*/
 338 #define BP_MCM_CR_SRAMLWP    (30U)         /*!< Bit position for MCM_CR_SRAMLWP. */
 339 #define BM_MCM_CR_SRAMLWP    (0x40000000U) /*!< Bit mask for MCM_CR_SRAMLWP. */
 340 #define BS_MCM_CR_SRAMLWP    (1U)          /*!< Bit field size in bits for MCM_CR_SRAMLWP. */
 341
 342 /*! @brief Read current value of the MCM_CR_SRAMLWP field. */
 343 #define BR_MCM_CR_SRAMLWP(x) (HW_MCM_CR(x).B.SRAMLWP)
 344
 345 /*! @brief Format value for bitfield MCM_CR_SRAMLWP. */
 346 #define BF_MCM_CR_SRAMLWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLWP) & BM_MCM_CR_SRAMLWP)
 347
 348 /*! @brief Set the SRAMLWP field to a new value. */
 349 #define BW_MCM_CR_SRAMLWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLWP) | BF_MCM_CR_SRAMLWP(v)))
 350 /*@}*/
 351
 352 /*******************************************************************************
 353  * HW_MCM_ISCR - Interrupt Status Register
 354  ******************************************************************************/
 355
 356 /*!
 357  * @brief HW_MCM_ISCR - Interrupt Status Register (RW)
 358  *
 359  * Reset value: 0x00000000U
 360  */
 361 typedef union _hw_mcm_iscr
 362 {
 363     uint32_t U;
 364     struct _hw_mcm_iscr_bitfields
 365     {
 366         uint32_t RESERVED0 : 1;        /*!< [0]  */
 367         uint32_t IRQ : 1;              /*!< [1] Normal Interrupt Pending */
 368         uint32_t NMI : 1;              /*!< [2] Non-maskable Interrupt Pending */
 369         uint32_t DHREQ : 1;            /*!< [3] Debug Halt Request Indicator */
 370         uint32_t RESERVED1 : 4;        /*!< [7:4]  */
 371         uint32_t FIOC : 1;             /*!< [8] FPU invalid operation interrupt status */
 372         uint32_t FDZC : 1;             /*!< [9] FPU divide-by-zero interrupt status */
 373         uint32_t FOFC : 1;             /*!< [10] FPU overflow interrupt status */
 374         uint32_t FUFC : 1;             /*!< [11] FPU underflow interrupt status */
 375         uint32_t FIXC : 1;             /*!< [12] FPU inexact interrupt status */
 376         uint32_t RESERVED2 : 2;        /*!< [14:13]  */
 377         uint32_t FIDC : 1;             /*!< [15] FPU input denormal interrupt status */
 378         uint32_t RESERVED3 : 8;        /*!< [23:16]  */
 379         uint32_t FIOCE : 1;            /*!< [24] FPU invalid operation interrupt enable
 380                                         * */
 381         uint32_t FDZCE : 1;            /*!< [25] FPU divide-by-zero interrupt enable */
 382         uint32_t FOFCE : 1;            /*!< [26] FPU overflow interrupt enable */
 383         uint32_t FUFCE : 1;            /*!< [27] FPU underflow interrupt enable */
 384         uint32_t FIXCE : 1;            /*!< [28] FPU inexact interrupt enable */
 385         uint32_t RESERVED4 : 2;        /*!< [30:29]  */
 386         uint32_t FIDCE : 1;            /*!< [31] FPU input denormal interrupt enable */
 387     } B;
 388 } hw_mcm_iscr_t;
 389
 390 /*!
 391  * @name Constants and macros for entire MCM_ISCR register
 392  */
 393 /*@{*/
 394 #define HW_MCM_ISCR_ADDR(x)      ((x) + 0x10U)
 395
 396 #define HW_MCM_ISCR(x)           (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
 397 #define HW_MCM_ISCR_RD(x)        (HW_MCM_ISCR(x).U)
 398 #define HW_MCM_ISCR_WR(x, v)     (HW_MCM_ISCR(x).U = (v))
 399 #define HW_MCM_ISCR_SET(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) |  (v)))
 400 #define HW_MCM_ISCR_CLR(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
 401 #define HW_MCM_ISCR_TOG(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^  (v)))
 402 /*@}*/
 403
 404 /*
 405  * Constants & macros for individual MCM_ISCR bitfields
 406  */
 407
 408 /*!
 409  * @name Register MCM_ISCR, field IRQ[1] (W1C)
 410  *
 411  * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
 412  *
 413  * Values:
 414  * - 0 - No pending interrupt
 415  * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
 416  */
 417 /*@{*/
 418 #define BP_MCM_ISCR_IRQ      (1U)          /*!< Bit position for MCM_ISCR_IRQ. */
 419 #define BM_MCM_ISCR_IRQ      (0x00000002U) /*!< Bit mask for MCM_ISCR_IRQ. */
 420 #define BS_MCM_ISCR_IRQ      (1U)          /*!< Bit field size in bits for MCM_ISCR_IRQ. */
 421
 422 /*! @brief Read current value of the MCM_ISCR_IRQ field. */
 423 #define BR_MCM_ISCR_IRQ(x)   (HW_MCM_ISCR(x).B.IRQ)
 424
 425 /*! @brief Format value for bitfield MCM_ISCR_IRQ. */
 426 #define BF_MCM_ISCR_IRQ(v)   ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_IRQ) & BM_MCM_ISCR_IRQ)
 427
 428 /*! @brief Set the IRQ field to a new value. */
 429 #define BW_MCM_ISCR_IRQ(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_IRQ) | BF_MCM_ISCR_IRQ(v)))
 430 /*@}*/
 431
 432 /*!
 433  * @name Register MCM_ISCR, field NMI[2] (W1C)
 434  *
 435  * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
 436  *
 437  * Values:
 438  * - 0 - No pending NMI
 439  * - 1 - Due to the ETB counter expiring, an NMI is pending
 440  */
 441 /*@{*/
 442 #define BP_MCM_ISCR_NMI      (2U)          /*!< Bit position for MCM_ISCR_NMI. */
 443 #define BM_MCM_ISCR_NMI      (0x00000004U) /*!< Bit mask for MCM_ISCR_NMI. */
 444 #define BS_MCM_ISCR_NMI      (1U)          /*!< Bit field size in bits for MCM_ISCR_NMI. */
 445
 446 /*! @brief Read current value of the MCM_ISCR_NMI field. */
 447 #define BR_MCM_ISCR_NMI(x)   (HW_MCM_ISCR(x).B.NMI)
 448
 449 /*! @brief Format value for bitfield MCM_ISCR_NMI. */
 450 #define BF_MCM_ISCR_NMI(v)   ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_NMI) & BM_MCM_ISCR_NMI)
 451
 452 /*! @brief Set the NMI field to a new value. */
 453 #define BW_MCM_ISCR_NMI(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_NMI) | BF_MCM_ISCR_NMI(v)))
 454 /*@}*/
 455
 456 /*!
 457  * @name Register MCM_ISCR, field DHREQ[3] (RO)
 458  *
 459  * Indicates that a debug halt request is initiated due to a ETB counter
 460  * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
 461  * counter is disabled or when the ETB counter is reloaded.
 462  *
 463  * Values:
 464  * - 0 - No debug halt request
 465  * - 1 - Debug halt request initiated
 466  */
 467 /*@{*/
 468 #define BP_MCM_ISCR_DHREQ    (3U)          /*!< Bit position for MCM_ISCR_DHREQ. */
 469 #define BM_MCM_ISCR_DHREQ    (0x00000008U) /*!< Bit mask for MCM_ISCR_DHREQ. */
 470 #define BS_MCM_ISCR_DHREQ    (1U)          /*!< Bit field size in bits for MCM_ISCR_DHREQ. */
 471
 472 /*! @brief Read current value of the MCM_ISCR_DHREQ field. */
 473 #define BR_MCM_ISCR_DHREQ(x) (HW_MCM_ISCR(x).B.DHREQ)
 474 /*@}*/
 475
 476 /*!
 477  * @name Register MCM_ISCR, field FIOC[8] (RO)
 478  *
 479  * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
 480  * illegal operation has been detected in the processor's FPU. Once set, this bit
 481  * remains set until software clears the FPSCR[IOC] bit.
 482  *
 483  * Values:
 484  * - 0 - No interrupt
 485  * - 1 - Interrupt occurred
 486  */
 487 /*@{*/
 488 #define BP_MCM_ISCR_FIOC     (8U)          /*!< Bit position for MCM_ISCR_FIOC. */
 489 #define BM_MCM_ISCR_FIOC     (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
 490 #define BS_MCM_ISCR_FIOC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOC. */
 491
 492 /*! @brief Read current value of the MCM_ISCR_FIOC field. */
 493 #define BR_MCM_ISCR_FIOC(x)  (HW_MCM_ISCR(x).B.FIOC)
 494 /*@}*/
 495
 496 /*!
 497  * @name Register MCM_ISCR, field FDZC[9] (RO)
 498  *
 499  * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
 500  * divide by zero has been detected in the processor's FPU. Once set, this bit remains
 501  * set until software clears the FPSCR[DZC] bit.
 502  *
 503  * Values:
 504  * - 0 - No interrupt
 505  * - 1 - Interrupt occurred
 506  */
 507 /*@{*/
 508 #define BP_MCM_ISCR_FDZC     (9U)          /*!< Bit position for MCM_ISCR_FDZC. */
 509 #define BM_MCM_ISCR_FDZC     (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
 510 #define BS_MCM_ISCR_FDZC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZC. */
 511
 512 /*! @brief Read current value of the MCM_ISCR_FDZC field. */
 513 #define BR_MCM_ISCR_FDZC(x)  (HW_MCM_ISCR(x).B.FDZC)
 514 /*@}*/
 515
 516 /*!
 517  * @name Register MCM_ISCR, field FOFC[10] (RO)
 518  *
 519  * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
 520  * overflow has been detected in the processor's FPU. Once set, this bit remains set
 521  * until software clears the FPSCR[OFC] bit.
 522  *
 523  * Values:
 524  * - 0 - No interrupt
 525  * - 1 - Interrupt occurred
 526  */
 527 /*@{*/
 528 #define BP_MCM_ISCR_FOFC     (10U)         /*!< Bit position for MCM_ISCR_FOFC. */
 529 #define BM_MCM_ISCR_FOFC     (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
 530 #define BS_MCM_ISCR_FOFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFC. */
 531
 532 /*! @brief Read current value of the MCM_ISCR_FOFC field. */
 533 #define BR_MCM_ISCR_FOFC(x)  (HW_MCM_ISCR(x).B.FOFC)
 534 /*@}*/
 535
 536 /*!
 537  * @name Register MCM_ISCR, field FUFC[11] (RO)
 538  *
 539  * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
 540  * underflow has been detected in the processor's FPU. Once set, this bit remains set
 541  * until software clears the FPSCR[UFC] bit.
 542  *
 543  * Values:
 544  * - 0 - No interrupt
 545  * - 1 - Interrupt occurred
 546  */
 547 /*@{*/
 548 #define BP_MCM_ISCR_FUFC     (11U)         /*!< Bit position for MCM_ISCR_FUFC. */
 549 #define BM_MCM_ISCR_FUFC     (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
 550 #define BS_MCM_ISCR_FUFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFC. */
 551
 552 /*! @brief Read current value of the MCM_ISCR_FUFC field. */
 553 #define BR_MCM_ISCR_FUFC(x)  (HW_MCM_ISCR(x).B.FUFC)
 554 /*@}*/
 555
 556 /*!
 557  * @name Register MCM_ISCR, field FIXC[12] (RO)
 558  *
 559  * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
 560  * inexact number has been detected in the processor's FPU. Once set, this bit
 561  * remains set until software clears the FPSCR[IXC] bit.
 562  *
 563  * Values:
 564  * - 0 - No interrupt
 565  * - 1 - Interrupt occurred
 566  */
 567 /*@{*/
 568 #define BP_MCM_ISCR_FIXC     (12U)         /*!< Bit position for MCM_ISCR_FIXC. */
 569 #define BM_MCM_ISCR_FIXC     (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
 570 #define BS_MCM_ISCR_FIXC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXC. */
 571
 572 /*! @brief Read current value of the MCM_ISCR_FIXC field. */
 573 #define BR_MCM_ISCR_FIXC(x)  (HW_MCM_ISCR(x).B.FIXC)
 574 /*@}*/
 575
 576 /*!
 577  * @name Register MCM_ISCR, field FIDC[15] (RO)
 578  *
 579  * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
 580  * denormalized number has been detected in the processor's FPU. Once set, this
 581  * bit remains set until software clears the FPSCR[IDC] bit.
 582  *
 583  * Values:
 584  * - 0 - No interrupt
 585  * - 1 - Interrupt occurred
 586  */
 587 /*@{*/
 588 #define BP_MCM_ISCR_FIDC     (15U)         /*!< Bit position for MCM_ISCR_FIDC. */
 589 #define BM_MCM_ISCR_FIDC     (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
 590 #define BS_MCM_ISCR_FIDC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDC. */
 591
 592 /*! @brief Read current value of the MCM_ISCR_FIDC field. */
 593 #define BR_MCM_ISCR_FIDC(x)  (HW_MCM_ISCR(x).B.FIDC)
 594 /*@}*/
 595
 596 /*!
 597  * @name Register MCM_ISCR, field FIOCE[24] (RW)
 598  *
 599  * Values:
 600  * - 0 - Disable interrupt
 601  * - 1 - Enable interrupt
 602  */
 603 /*@{*/
 604 #define BP_MCM_ISCR_FIOCE    (24U)         /*!< Bit position for MCM_ISCR_FIOCE. */
 605 #define BM_MCM_ISCR_FIOCE    (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
 606 #define BS_MCM_ISCR_FIOCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
 607
 608 /*! @brief Read current value of the MCM_ISCR_FIOCE field. */
 609 #define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE)
 610
 611 /*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
 612 #define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
 613
 614 /*! @brief Set the FIOCE field to a new value. */
 615 #define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
 616 /*@}*/
 617
 618 /*!
 619  * @name Register MCM_ISCR, field FDZCE[25] (RW)
 620  *
 621  * Values:
 622  * - 0 - Disable interrupt
 623  * - 1 - Enable interrupt
 624  */
 625 /*@{*/
 626 #define BP_MCM_ISCR_FDZCE    (25U)         /*!< Bit position for MCM_ISCR_FDZCE. */
 627 #define BM_MCM_ISCR_FDZCE    (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
 628 #define BS_MCM_ISCR_FDZCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
 629
 630 /*! @brief Read current value of the MCM_ISCR_FDZCE field. */
 631 #define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE)
 632
 633 /*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
 634 #define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
 635
 636 /*! @brief Set the FDZCE field to a new value. */
 637 #define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
 638 /*@}*/
 639
 640 /*!
 641  * @name Register MCM_ISCR, field FOFCE[26] (RW)
 642  *
 643  * Values:
 644  * - 0 - Disable interrupt
 645  * - 1 - Enable interrupt
 646  */
 647 /*@{*/
 648 #define BP_MCM_ISCR_FOFCE    (26U)         /*!< Bit position for MCM_ISCR_FOFCE. */
 649 #define BM_MCM_ISCR_FOFCE    (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
 650 #define BS_MCM_ISCR_FOFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
 651
 652 /*! @brief Read current value of the MCM_ISCR_FOFCE field. */
 653 #define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE)
 654
 655 /*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
 656 #define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
 657
 658 /*! @brief Set the FOFCE field to a new value. */
 659 #define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
 660 /*@}*/
 661
 662 /*!
 663  * @name Register MCM_ISCR, field FUFCE[27] (RW)
 664  *
 665  * Values:
 666  * - 0 - Disable interrupt
 667  * - 1 - Enable interrupt
 668  */
 669 /*@{*/
 670 #define BP_MCM_ISCR_FUFCE    (27U)         /*!< Bit position for MCM_ISCR_FUFCE. */
 671 #define BM_MCM_ISCR_FUFCE    (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
 672 #define BS_MCM_ISCR_FUFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
 673
 674 /*! @brief Read current value of the MCM_ISCR_FUFCE field. */
 675 #define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE)
 676
 677 /*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
 678 #define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
 679
 680 /*! @brief Set the FUFCE field to a new value. */
 681 #define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
 682 /*@}*/
 683
 684 /*!
 685  * @name Register MCM_ISCR, field FIXCE[28] (RW)
 686  *
 687  * Values:
 688  * - 0 - Disable interrupt
 689  * - 1 - Enable interrupt
 690  */
 691 /*@{*/
 692 #define BP_MCM_ISCR_FIXCE    (28U)         /*!< Bit position for MCM_ISCR_FIXCE. */
 693 #define BM_MCM_ISCR_FIXCE    (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
 694 #define BS_MCM_ISCR_FIXCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
 695
 696 /*! @brief Read current value of the MCM_ISCR_FIXCE field. */
 697 #define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE)
 698
 699 /*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
 700 #define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
 701
 702 /*! @brief Set the FIXCE field to a new value. */
 703 #define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
 704 /*@}*/
 705
 706 /*!
 707  * @name Register MCM_ISCR, field FIDCE[31] (RW)
 708  *
 709  * Values:
 710  * - 0 - Disable interrupt
 711  * - 1 - Enable interrupt
 712  */
 713 /*@{*/
 714 #define BP_MCM_ISCR_FIDCE    (31U)         /*!< Bit position for MCM_ISCR_FIDCE. */
 715 #define BM_MCM_ISCR_FIDCE    (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
 716 #define BS_MCM_ISCR_FIDCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
 717
 718 /*! @brief Read current value of the MCM_ISCR_FIDCE field. */
 719 #define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE)
 720
 721 /*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
 722 #define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
 723
 724 /*! @brief Set the FIDCE field to a new value. */
 725 #define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
 726 /*@}*/
 727
 728 /*******************************************************************************
 729  * HW_MCM_ETBCC - ETB Counter Control register
 730  ******************************************************************************/
 731
 732 /*!
 733  * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
 734  *
 735  * Reset value: 0x00000000U
 736  */
 737 typedef union _hw_mcm_etbcc
 738 {
 739     uint32_t U;
 740     struct _hw_mcm_etbcc_bitfields
 741     {
 742         uint32_t CNTEN : 1;            /*!< [0] Counter Enable */
 743         uint32_t RSPT : 2;             /*!< [2:1] Response Type */
 744         uint32_t RLRQ : 1;             /*!< [3] Reload Request */
 745         uint32_t ETDIS : 1;            /*!< [4] ETM-To-TPIU Disable */
 746         uint32_t ITDIS : 1;            /*!< [5] ITM-To-TPIU Disable */
 747         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
 748     } B;
 749 } hw_mcm_etbcc_t;
 750
 751 /*!
 752  * @name Constants and macros for entire MCM_ETBCC register
 753  */
 754 /*@{*/
 755 #define HW_MCM_ETBCC_ADDR(x)     ((x) + 0x14U)
 756
 757 #define HW_MCM_ETBCC(x)          (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR(x))
 758 #define HW_MCM_ETBCC_RD(x)       (HW_MCM_ETBCC(x).U)
 759 #define HW_MCM_ETBCC_WR(x, v)    (HW_MCM_ETBCC(x).U = (v))
 760 #define HW_MCM_ETBCC_SET(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) |  (v)))
 761 #define HW_MCM_ETBCC_CLR(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) & ~(v)))
 762 #define HW_MCM_ETBCC_TOG(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) ^  (v)))
 763 /*@}*/
 764
 765 /*
 766  * Constants & macros for individual MCM_ETBCC bitfields
 767  */
 768
 769 /*!
 770  * @name Register MCM_ETBCC, field CNTEN[0] (RW)
 771  *
 772  * Enables the ETB counter.
 773  *
 774  * Values:
 775  * - 0 - ETB counter disabled
 776  * - 1 - ETB counter enabled
 777  */
 778 /*@{*/
 779 #define BP_MCM_ETBCC_CNTEN   (0U)          /*!< Bit position for MCM_ETBCC_CNTEN. */
 780 #define BM_MCM_ETBCC_CNTEN   (0x00000001U) /*!< Bit mask for MCM_ETBCC_CNTEN. */
 781 #define BS_MCM_ETBCC_CNTEN   (1U)          /*!< Bit field size in bits for MCM_ETBCC_CNTEN. */
 782
 783 /*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
 784 #define BR_MCM_ETBCC_CNTEN(x) (HW_MCM_ETBCC(x).B.CNTEN)
 785
 786 /*! @brief Format value for bitfield MCM_ETBCC_CNTEN. */
 787 #define BF_MCM_ETBCC_CNTEN(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_CNTEN) & BM_MCM_ETBCC_CNTEN)
 788
 789 /*! @brief Set the CNTEN field to a new value. */
 790 #define BW_MCM_ETBCC_CNTEN(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_CNTEN) | BF_MCM_ETBCC_CNTEN(v)))
 791 /*@}*/
 792
 793 /*!
 794  * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
 795  *
 796  * Values:
 797  * - 00 - No response when the ETB count expires
 798  * - 01 - Generate a normal interrupt when the ETB count expires
 799  * - 10 - Generate an NMI when the ETB count expires
 800  * - 11 - Generate a debug halt when the ETB count expires
 801  */
 802 /*@{*/
 803 #define BP_MCM_ETBCC_RSPT    (1U)          /*!< Bit position for MCM_ETBCC_RSPT. */
 804 #define BM_MCM_ETBCC_RSPT    (0x00000006U) /*!< Bit mask for MCM_ETBCC_RSPT. */
 805 #define BS_MCM_ETBCC_RSPT    (2U)          /*!< Bit field size in bits for MCM_ETBCC_RSPT. */
 806
 807 /*! @brief Read current value of the MCM_ETBCC_RSPT field. */
 808 #define BR_MCM_ETBCC_RSPT(x) (HW_MCM_ETBCC(x).B.RSPT)
 809
 810 /*! @brief Format value for bitfield MCM_ETBCC_RSPT. */
 811 #define BF_MCM_ETBCC_RSPT(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RSPT) & BM_MCM_ETBCC_RSPT)
 812
 813 /*! @brief Set the RSPT field to a new value. */
 814 #define BW_MCM_ETBCC_RSPT(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
 815 /*@}*/
 816
 817 /*!
 818  * @name Register MCM_ETBCC, field RLRQ[3] (RW)
 819  *
 820  * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
 821  * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
 822  * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
 823  * If debug halt was enabled and a debug halt request was asserted on counter
 824  * expiration, setting this bit clears the debug halt request.
 825  *
 826  * Values:
 827  * - 0 - No effect
 828  * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
 829  */
 830 /*@{*/
 831 #define BP_MCM_ETBCC_RLRQ    (3U)          /*!< Bit position for MCM_ETBCC_RLRQ. */
 832 #define BM_MCM_ETBCC_RLRQ    (0x00000008U) /*!< Bit mask for MCM_ETBCC_RLRQ. */
 833 #define BS_MCM_ETBCC_RLRQ    (1U)          /*!< Bit field size in bits for MCM_ETBCC_RLRQ. */
 834
 835 /*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
 836 #define BR_MCM_ETBCC_RLRQ(x) (HW_MCM_ETBCC(x).B.RLRQ)
 837
 838 /*! @brief Format value for bitfield MCM_ETBCC_RLRQ. */
 839 #define BF_MCM_ETBCC_RLRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RLRQ) & BM_MCM_ETBCC_RLRQ)
 840
 841 /*! @brief Set the RLRQ field to a new value. */
 842 #define BW_MCM_ETBCC_RLRQ(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RLRQ) | BF_MCM_ETBCC_RLRQ(v)))
 843 /*@}*/
 844
 845 /*!
 846  * @name Register MCM_ETBCC, field ETDIS[4] (RW)
 847  *
 848  * Disables the trace path from ETM to TPIU.
 849  *
 850  * Values:
 851  * - 0 - ETM-to-TPIU trace path enabled
 852  * - 1 - ETM-to-TPIU trace path disabled
 853  */
 854 /*@{*/
 855 #define BP_MCM_ETBCC_ETDIS   (4U)          /*!< Bit position for MCM_ETBCC_ETDIS. */
 856 #define BM_MCM_ETBCC_ETDIS   (0x00000010U) /*!< Bit mask for MCM_ETBCC_ETDIS. */
 857 #define BS_MCM_ETBCC_ETDIS   (1U)          /*!< Bit field size in bits for MCM_ETBCC_ETDIS. */
 858
 859 /*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
 860 #define BR_MCM_ETBCC_ETDIS(x) (HW_MCM_ETBCC(x).B.ETDIS)
 861
 862 /*! @brief Format value for bitfield MCM_ETBCC_ETDIS. */
 863 #define BF_MCM_ETBCC_ETDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ETDIS) & BM_MCM_ETBCC_ETDIS)
 864
 865 /*! @brief Set the ETDIS field to a new value. */
 866 #define BW_MCM_ETBCC_ETDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ETDIS) | BF_MCM_ETBCC_ETDIS(v)))
 867 /*@}*/
 868
 869 /*!
 870  * @name Register MCM_ETBCC, field ITDIS[5] (RW)
 871  *
 872  * Disables the trace path from ITM to TPIU.
 873  *
 874  * Values:
 875  * - 0 - ITM-to-TPIU trace path enabled
 876  * - 1 - ITM-to-TPIU trace path disabled
 877  */
 878 /*@{*/
 879 #define BP_MCM_ETBCC_ITDIS   (5U)          /*!< Bit position for MCM_ETBCC_ITDIS. */
 880 #define BM_MCM_ETBCC_ITDIS   (0x00000020U) /*!< Bit mask for MCM_ETBCC_ITDIS. */
 881 #define BS_MCM_ETBCC_ITDIS   (1U)          /*!< Bit field size in bits for MCM_ETBCC_ITDIS. */
 882
 883 /*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
 884 #define BR_MCM_ETBCC_ITDIS(x) (HW_MCM_ETBCC(x).B.ITDIS)
 885
 886 /*! @brief Format value for bitfield MCM_ETBCC_ITDIS. */
 887 #define BF_MCM_ETBCC_ITDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ITDIS) & BM_MCM_ETBCC_ITDIS)
 888
 889 /*! @brief Set the ITDIS field to a new value. */
 890 #define BW_MCM_ETBCC_ITDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ITDIS) | BF_MCM_ETBCC_ITDIS(v)))
 891 /*@}*/
 892
 893 /*******************************************************************************
 894  * HW_MCM_ETBRL - ETB Reload register
 895  ******************************************************************************/
 896
 897 /*!
 898  * @brief HW_MCM_ETBRL - ETB Reload register (RW)
 899  *
 900  * Reset value: 0x00000000U
 901  */
 902 typedef union _hw_mcm_etbrl
 903 {
 904     uint32_t U;
 905     struct _hw_mcm_etbrl_bitfields
 906     {
 907         uint32_t RELOAD : 11;          /*!< [10:0] Byte Count Reload Value */
 908         uint32_t RESERVED0 : 21;       /*!< [31:11]  */
 909     } B;
 910 } hw_mcm_etbrl_t;
 911
 912 /*!
 913  * @name Constants and macros for entire MCM_ETBRL register
 914  */
 915 /*@{*/
 916 #define HW_MCM_ETBRL_ADDR(x)     ((x) + 0x18U)
 917
 918 #define HW_MCM_ETBRL(x)          (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR(x))
 919 #define HW_MCM_ETBRL_RD(x)       (HW_MCM_ETBRL(x).U)
 920 #define HW_MCM_ETBRL_WR(x, v)    (HW_MCM_ETBRL(x).U = (v))
 921 #define HW_MCM_ETBRL_SET(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) |  (v)))
 922 #define HW_MCM_ETBRL_CLR(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) & ~(v)))
 923 #define HW_MCM_ETBRL_TOG(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) ^  (v)))
 924 /*@}*/
 925
 926 /*
 927  * Constants & macros for individual MCM_ETBRL bitfields
 928  */
 929
 930 /*!
 931  * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
 932  *
 933  * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
 934  * value to this field results in a bus error.
 935  */
 936 /*@{*/
 937 #define BP_MCM_ETBRL_RELOAD  (0U)          /*!< Bit position for MCM_ETBRL_RELOAD. */
 938 #define BM_MCM_ETBRL_RELOAD  (0x000007FFU) /*!< Bit mask for MCM_ETBRL_RELOAD. */
 939 #define BS_MCM_ETBRL_RELOAD  (11U)         /*!< Bit field size in bits for MCM_ETBRL_RELOAD. */
 940
 941 /*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
 942 #define BR_MCM_ETBRL_RELOAD(x) (HW_MCM_ETBRL(x).B.RELOAD)
 943
 944 /*! @brief Format value for bitfield MCM_ETBRL_RELOAD. */
 945 #define BF_MCM_ETBRL_RELOAD(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBRL_RELOAD) & BM_MCM_ETBRL_RELOAD)
 946
 947 /*! @brief Set the RELOAD field to a new value. */
 948 #define BW_MCM_ETBRL_RELOAD(x, v) (HW_MCM_ETBRL_WR(x, (HW_MCM_ETBRL_RD(x) & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
 949 /*@}*/
 950
 951 /*******************************************************************************
 952  * HW_MCM_ETBCNT - ETB Counter Value register
 953  ******************************************************************************/
 954
 955 /*!
 956  * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
 957  *
 958  * Reset value: 0x00000000U
 959  */
 960 typedef union _hw_mcm_etbcnt
 961 {
 962     uint32_t U;
 963     struct _hw_mcm_etbcnt_bitfields
 964     {
 965         uint32_t COUNTER : 11;         /*!< [10:0] Byte Count Counter Value */
 966         uint32_t RESERVED0 : 21;       /*!< [31:11]  */
 967     } B;
 968 } hw_mcm_etbcnt_t;
 969
 970 /*!
 971  * @name Constants and macros for entire MCM_ETBCNT register
 972  */
 973 /*@{*/
 974 #define HW_MCM_ETBCNT_ADDR(x)    ((x) + 0x1CU)
 975
 976 #define HW_MCM_ETBCNT(x)         (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR(x))
 977 #define HW_MCM_ETBCNT_RD(x)      (HW_MCM_ETBCNT(x).U)
 978 /*@}*/
 979
 980 /*
 981  * Constants & macros for individual MCM_ETBCNT bitfields
 982  */
 983
 984 /*!
 985  * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
 986  *
 987  * Indicates the current 0-mod-4 value of the counter.
 988  */
 989 /*@{*/
 990 #define BP_MCM_ETBCNT_COUNTER (0U)         /*!< Bit position for MCM_ETBCNT_COUNTER. */
 991 #define BM_MCM_ETBCNT_COUNTER (0x000007FFU) /*!< Bit mask for MCM_ETBCNT_COUNTER. */
 992 #define BS_MCM_ETBCNT_COUNTER (11U)        /*!< Bit field size in bits for MCM_ETBCNT_COUNTER. */
 993
 994 /*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
 995 #define BR_MCM_ETBCNT_COUNTER(x) (HW_MCM_ETBCNT(x).B.COUNTER)
 996 /*@}*/
 997
 998 /*******************************************************************************
 999  * HW_MCM_PID - Process ID register
1000  ******************************************************************************/
1001
1002 /*!
1003  * @brief HW_MCM_PID - Process ID register (RW)
1004  *
1005  * Reset value: 0x00000000U
1006  *
1007  * This register drives the M0_PID and M1_PID values in the Memory Protection
1008  * Unit(MPU). System software loads this register before passing control to a given
1009  * user mode process. If the PID of the process does not match the value in this
1010  * register, a bus error occurs. See the MPU chapter for more details.
1011  */
1012 typedef union _hw_mcm_pid
1013 {
1014     uint32_t U;
1015     struct _hw_mcm_pid_bitfields
1016     {
1017         uint32_t PID : 8;              /*!< [7:0] M0_PID And M1_PID For MPU */
1018         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
1019     } B;
1020 } hw_mcm_pid_t;
1021
1022 /*!
1023  * @name Constants and macros for entire MCM_PID register
1024  */
1025 /*@{*/
1026 #define HW_MCM_PID_ADDR(x)       ((x) + 0x30U)
1027
1028 #define HW_MCM_PID(x)            (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR(x))
1029 #define HW_MCM_PID_RD(x)         (HW_MCM_PID(x).U)
1030 #define HW_MCM_PID_WR(x, v)      (HW_MCM_PID(x).U = (v))
1031 #define HW_MCM_PID_SET(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) |  (v)))
1032 #define HW_MCM_PID_CLR(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) & ~(v)))
1033 #define HW_MCM_PID_TOG(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) ^  (v)))
1034 /*@}*/
1035
1036 /*
1037  * Constants & macros for individual MCM_PID bitfields
1038  */
1039
1040 /*!
1041  * @name Register MCM_PID, field PID[7:0] (RW)
1042  *
1043  * Drives the M0_PID and M1_PID values in the MPU.
1044  */
1045 /*@{*/
1046 #define BP_MCM_PID_PID       (0U)          /*!< Bit position for MCM_PID_PID. */
1047 #define BM_MCM_PID_PID       (0x000000FFU) /*!< Bit mask for MCM_PID_PID. */
1048 #define BS_MCM_PID_PID       (8U)          /*!< Bit field size in bits for MCM_PID_PID. */
1049
1050 /*! @brief Read current value of the MCM_PID_PID field. */
1051 #define BR_MCM_PID_PID(x)    (HW_MCM_PID(x).B.PID)
1052
1053 /*! @brief Format value for bitfield MCM_PID_PID. */
1054 #define BF_MCM_PID_PID(v)    ((uint32_t)((uint32_t)(v) << BP_MCM_PID_PID) & BM_MCM_PID_PID)
1055
1056 /*! @brief Set the PID field to a new value. */
1057 #define BW_MCM_PID_PID(x, v) (HW_MCM_PID_WR(x, (HW_MCM_PID_RD(x) & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
1058 /*@}*/
1059
1060 /*******************************************************************************
1061  * hw_mcm_t - module struct
1062  ******************************************************************************/
1063 /*!
1064  * @brief All MCM module registers.
1065  */
1066 #pragma pack(1)
1067 typedef struct _hw_mcm
1068 {
1069     uint8_t _reserved0[8];
1070     __I hw_mcm_plasc_t PLASC;              /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
1071     __I hw_mcm_plamc_t PLAMC;              /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
1072     __IO hw_mcm_cr_t CR;                   /*!< [0xC] Control Register */
1073     __IO hw_mcm_iscr_t ISCR;               /*!< [0x10] Interrupt Status Register */
1074     __IO hw_mcm_etbcc_t ETBCC;             /*!< [0x14] ETB Counter Control register */
1075     __IO hw_mcm_etbrl_t ETBRL;             /*!< [0x18] ETB Reload register */
1076     __I hw_mcm_etbcnt_t ETBCNT;            /*!< [0x1C] ETB Counter Value register */
1077     uint8_t _reserved1[16];
1078     __IO hw_mcm_pid_t PID;                 /*!< [0x30] Process ID register */
1079 } hw_mcm_t;
1080 #pragma pack()
1081
1082 /*! @brief Macro to access all MCM registers. */
1083 /*! @param x MCM module instance base address. */
1084 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1085  *     use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
1086 #define HW_MCM(x)      (*(hw_mcm_t *)(x))
1087
1088 #endif /* __HW_MCM_REGISTERS_H__ */
1089 /* EOF */