tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rtc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_RTC_REGISTERS_H__
  81 #define __HW_RTC_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 RTC
  88  *
  89  * Secure Real Time Clock
  90  *
  91  * Registers defined in this header file:
  92  * - HW_RTC_TSR - RTC Time Seconds Register
  93  * - HW_RTC_TPR - RTC Time Prescaler Register
  94  * - HW_RTC_TAR - RTC Time Alarm Register
  95  * - HW_RTC_TCR - RTC Time Compensation Register
  96  * - HW_RTC_CR - RTC Control Register
  97  * - HW_RTC_SR - RTC Status Register
  98  * - HW_RTC_LR - RTC Lock Register
  99  * - HW_RTC_IER - RTC Interrupt Enable Register
 100  * - HW_RTC_WAR - RTC Write Access Register
 101  * - HW_RTC_RAR - RTC Read Access Register
 102  *
 103  * - hw_rtc_t - Struct containing all module registers.
 104  */
 105
 106 #define HW_RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
 107
 108 /*******************************************************************************
 109  * HW_RTC_TSR - RTC Time Seconds Register
 110  ******************************************************************************/
 111
 112 /*!
 113  * @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
 114  *
 115  * Reset value: 0x00000000U
 116  */
 117 typedef union _hw_rtc_tsr
 118 {
 119     uint32_t U;
 120     struct _hw_rtc_tsr_bitfields
 121     {
 122         uint32_t TSR : 32;             /*!< [31:0] Time Seconds Register */
 123     } B;
 124 } hw_rtc_tsr_t;
 125
 126 /*!
 127  * @name Constants and macros for entire RTC_TSR register
 128  */
 129 /*@{*/
 130 #define HW_RTC_TSR_ADDR(x)       ((x) + 0x0U)
 131
 132 #define HW_RTC_TSR(x)            (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR(x))
 133 #define HW_RTC_TSR_RD(x)         (HW_RTC_TSR(x).U)
 134 #define HW_RTC_TSR_WR(x, v)      (HW_RTC_TSR(x).U = (v))
 135 #define HW_RTC_TSR_SET(x, v)     (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) |  (v)))
 136 #define HW_RTC_TSR_CLR(x, v)     (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) & ~(v)))
 137 #define HW_RTC_TSR_TOG(x, v)     (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) ^  (v)))
 138 /*@}*/
 139
 140 /*
 141  * Constants & macros for individual RTC_TSR bitfields
 142  */
 143
 144 /*!
 145  * @name Register RTC_TSR, field TSR[31:0] (RW)
 146  *
 147  * When the time counter is enabled, the TSR is read only and increments once a
 148  * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
 149  * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
 150  * TSR can be read or written. Writing to the TSR when the time counter is
 151  * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
 152  * supported, but not recommended because TSR will read as zero when SR[TIF] or
 153  * SR[TOF] are set (indicating the time is invalid).
 154  */
 155 /*@{*/
 156 #define BP_RTC_TSR_TSR       (0U)          /*!< Bit position for RTC_TSR_TSR. */
 157 #define BM_RTC_TSR_TSR       (0xFFFFFFFFU) /*!< Bit mask for RTC_TSR_TSR. */
 158 #define BS_RTC_TSR_TSR       (32U)         /*!< Bit field size in bits for RTC_TSR_TSR. */
 159
 160 /*! @brief Read current value of the RTC_TSR_TSR field. */
 161 #define BR_RTC_TSR_TSR(x)    (HW_RTC_TSR(x).U)
 162
 163 /*! @brief Format value for bitfield RTC_TSR_TSR. */
 164 #define BF_RTC_TSR_TSR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TSR_TSR) & BM_RTC_TSR_TSR)
 165
 166 /*! @brief Set the TSR field to a new value. */
 167 #define BW_RTC_TSR_TSR(x, v) (HW_RTC_TSR_WR(x, v))
 168 /*@}*/
 169
 170 /*******************************************************************************
 171  * HW_RTC_TPR - RTC Time Prescaler Register
 172  ******************************************************************************/
 173
 174 /*!
 175  * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
 176  *
 177  * Reset value: 0x00000000U
 178  */
 179 typedef union _hw_rtc_tpr
 180 {
 181     uint32_t U;
 182     struct _hw_rtc_tpr_bitfields
 183     {
 184         uint32_t TPR : 16;             /*!< [15:0] Time Prescaler Register */
 185         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 186     } B;
 187 } hw_rtc_tpr_t;
 188
 189 /*!
 190  * @name Constants and macros for entire RTC_TPR register
 191  */
 192 /*@{*/
 193 #define HW_RTC_TPR_ADDR(x)       ((x) + 0x4U)
 194
 195 #define HW_RTC_TPR(x)            (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR(x))
 196 #define HW_RTC_TPR_RD(x)         (HW_RTC_TPR(x).U)
 197 #define HW_RTC_TPR_WR(x, v)      (HW_RTC_TPR(x).U = (v))
 198 #define HW_RTC_TPR_SET(x, v)     (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) |  (v)))
 199 #define HW_RTC_TPR_CLR(x, v)     (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) & ~(v)))
 200 #define HW_RTC_TPR_TOG(x, v)     (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) ^  (v)))
 201 /*@}*/
 202
 203 /*
 204  * Constants & macros for individual RTC_TPR bitfields
 205  */
 206
 207 /*!
 208  * @name Register RTC_TPR, field TPR[15:0] (RW)
 209  *
 210  * When the time counter is enabled, the TPR is read only and increments every
 211  * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
 212  * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
 213  * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
 214  * to a logic zero.
 215  */
 216 /*@{*/
 217 #define BP_RTC_TPR_TPR       (0U)          /*!< Bit position for RTC_TPR_TPR. */
 218 #define BM_RTC_TPR_TPR       (0x0000FFFFU) /*!< Bit mask for RTC_TPR_TPR. */
 219 #define BS_RTC_TPR_TPR       (16U)         /*!< Bit field size in bits for RTC_TPR_TPR. */
 220
 221 /*! @brief Read current value of the RTC_TPR_TPR field. */
 222 #define BR_RTC_TPR_TPR(x)    (HW_RTC_TPR(x).B.TPR)
 223
 224 /*! @brief Format value for bitfield RTC_TPR_TPR. */
 225 #define BF_RTC_TPR_TPR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TPR_TPR) & BM_RTC_TPR_TPR)
 226
 227 /*! @brief Set the TPR field to a new value. */
 228 #define BW_RTC_TPR_TPR(x, v) (HW_RTC_TPR_WR(x, (HW_RTC_TPR_RD(x) & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v)))
 229 /*@}*/
 230
 231 /*******************************************************************************
 232  * HW_RTC_TAR - RTC Time Alarm Register
 233  ******************************************************************************/
 234
 235 /*!
 236  * @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
 237  *
 238  * Reset value: 0x00000000U
 239  */
 240 typedef union _hw_rtc_tar
 241 {
 242     uint32_t U;
 243     struct _hw_rtc_tar_bitfields
 244     {
 245         uint32_t TAR : 32;             /*!< [31:0] Time Alarm Register */
 246     } B;
 247 } hw_rtc_tar_t;
 248
 249 /*!
 250  * @name Constants and macros for entire RTC_TAR register
 251  */
 252 /*@{*/
 253 #define HW_RTC_TAR_ADDR(x)       ((x) + 0x8U)
 254
 255 #define HW_RTC_TAR(x)            (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR(x))
 256 #define HW_RTC_TAR_RD(x)         (HW_RTC_TAR(x).U)
 257 #define HW_RTC_TAR_WR(x, v)      (HW_RTC_TAR(x).U = (v))
 258 #define HW_RTC_TAR_SET(x, v)     (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) |  (v)))
 259 #define HW_RTC_TAR_CLR(x, v)     (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) & ~(v)))
 260 #define HW_RTC_TAR_TOG(x, v)     (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) ^  (v)))
 261 /*@}*/
 262
 263 /*
 264  * Constants & macros for individual RTC_TAR bitfields
 265  */
 266
 267 /*!
 268  * @name Register RTC_TAR, field TAR[31:0] (RW)
 269  *
 270  * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
 271  * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
 272  * SR[TAF].
 273  */
 274 /*@{*/
 275 #define BP_RTC_TAR_TAR       (0U)          /*!< Bit position for RTC_TAR_TAR. */
 276 #define BM_RTC_TAR_TAR       (0xFFFFFFFFU) /*!< Bit mask for RTC_TAR_TAR. */
 277 #define BS_RTC_TAR_TAR       (32U)         /*!< Bit field size in bits for RTC_TAR_TAR. */
 278
 279 /*! @brief Read current value of the RTC_TAR_TAR field. */
 280 #define BR_RTC_TAR_TAR(x)    (HW_RTC_TAR(x).U)
 281
 282 /*! @brief Format value for bitfield RTC_TAR_TAR. */
 283 #define BF_RTC_TAR_TAR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TAR_TAR) & BM_RTC_TAR_TAR)
 284
 285 /*! @brief Set the TAR field to a new value. */
 286 #define BW_RTC_TAR_TAR(x, v) (HW_RTC_TAR_WR(x, v))
 287 /*@}*/
 288
 289 /*******************************************************************************
 290  * HW_RTC_TCR - RTC Time Compensation Register
 291  ******************************************************************************/
 292
 293 /*!
 294  * @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
 295  *
 296  * Reset value: 0x00000000U
 297  */
 298 typedef union _hw_rtc_tcr
 299 {
 300     uint32_t U;
 301     struct _hw_rtc_tcr_bitfields
 302     {
 303         uint32_t TCR : 8;              /*!< [7:0] Time Compensation Register */
 304         uint32_t CIR : 8;              /*!< [15:8] Compensation Interval Register */
 305         uint32_t TCV : 8;              /*!< [23:16] Time Compensation Value */
 306         uint32_t CIC : 8;              /*!< [31:24] Compensation Interval Counter */
 307     } B;
 308 } hw_rtc_tcr_t;
 309
 310 /*!
 311  * @name Constants and macros for entire RTC_TCR register
 312  */
 313 /*@{*/
 314 #define HW_RTC_TCR_ADDR(x)       ((x) + 0xCU)
 315
 316 #define HW_RTC_TCR(x)            (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR(x))
 317 #define HW_RTC_TCR_RD(x)         (HW_RTC_TCR(x).U)
 318 #define HW_RTC_TCR_WR(x, v)      (HW_RTC_TCR(x).U = (v))
 319 #define HW_RTC_TCR_SET(x, v)     (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) |  (v)))
 320 #define HW_RTC_TCR_CLR(x, v)     (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) & ~(v)))
 321 #define HW_RTC_TCR_TOG(x, v)     (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) ^  (v)))
 322 /*@}*/
 323
 324 /*
 325  * Constants & macros for individual RTC_TCR bitfields
 326  */
 327
 328 /*!
 329  * @name Register RTC_TCR, field TCR[7:0] (RW)
 330  *
 331  * Configures the number of 32.768 kHz clock cycles in each second. This
 332  * register is double buffered and writes do not take affect until the end of the
 333  * current compensation interval.
 334  *
 335  * Values:
 336  * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
 337  * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
 338  * - 0 - Time Prescaler Register overflows every 32768 clock cycles.
 339  * - 1 - Time Prescaler Register overflows every 32767 clock cycles.
 340  * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
 341  */
 342 /*@{*/
 343 #define BP_RTC_TCR_TCR       (0U)          /*!< Bit position for RTC_TCR_TCR. */
 344 #define BM_RTC_TCR_TCR       (0x000000FFU) /*!< Bit mask for RTC_TCR_TCR. */
 345 #define BS_RTC_TCR_TCR       (8U)          /*!< Bit field size in bits for RTC_TCR_TCR. */
 346
 347 /*! @brief Read current value of the RTC_TCR_TCR field. */
 348 #define BR_RTC_TCR_TCR(x)    (HW_RTC_TCR(x).B.TCR)
 349
 350 /*! @brief Format value for bitfield RTC_TCR_TCR. */
 351 #define BF_RTC_TCR_TCR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_TCR) & BM_RTC_TCR_TCR)
 352
 353 /*! @brief Set the TCR field to a new value. */
 354 #define BW_RTC_TCR_TCR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v)))
 355 /*@}*/
 356
 357 /*!
 358  * @name Register RTC_TCR, field CIR[15:8] (RW)
 359  *
 360  * Configures the compensation interval in seconds from 1 to 256 to control how
 361  * frequently the TCR should adjust the number of 32.768 kHz cycles in each
 362  * second. The value written should be one less than the number of seconds. For
 363  * example, write zero to configure for a compensation interval of one second. This
 364  * register is double buffered and writes do not take affect until the end of the
 365  * current compensation interval.
 366  */
 367 /*@{*/
 368 #define BP_RTC_TCR_CIR       (8U)          /*!< Bit position for RTC_TCR_CIR. */
 369 #define BM_RTC_TCR_CIR       (0x0000FF00U) /*!< Bit mask for RTC_TCR_CIR. */
 370 #define BS_RTC_TCR_CIR       (8U)          /*!< Bit field size in bits for RTC_TCR_CIR. */
 371
 372 /*! @brief Read current value of the RTC_TCR_CIR field. */
 373 #define BR_RTC_TCR_CIR(x)    (HW_RTC_TCR(x).B.CIR)
 374
 375 /*! @brief Format value for bitfield RTC_TCR_CIR. */
 376 #define BF_RTC_TCR_CIR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_CIR) & BM_RTC_TCR_CIR)
 377
 378 /*! @brief Set the CIR field to a new value. */
 379 #define BW_RTC_TCR_CIR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v)))
 380 /*@}*/
 381
 382 /*!
 383  * @name Register RTC_TCR, field TCV[23:16] (RO)
 384  *
 385  * Current value used by the compensation logic for the present second interval.
 386  * Updated once a second if the CIC equals 0 with the contents of the TCR field.
 387  * If the CIC does not equal zero then it is loaded with zero (compensation is
 388  * not enabled for that second increment).
 389  */
 390 /*@{*/
 391 #define BP_RTC_TCR_TCV       (16U)         /*!< Bit position for RTC_TCR_TCV. */
 392 #define BM_RTC_TCR_TCV       (0x00FF0000U) /*!< Bit mask for RTC_TCR_TCV. */
 393 #define BS_RTC_TCR_TCV       (8U)          /*!< Bit field size in bits for RTC_TCR_TCV. */
 394
 395 /*! @brief Read current value of the RTC_TCR_TCV field. */
 396 #define BR_RTC_TCR_TCV(x)    (HW_RTC_TCR(x).B.TCV)
 397 /*@}*/
 398
 399 /*!
 400  * @name Register RTC_TCR, field CIC[31:24] (RO)
 401  *
 402  * Current value of the compensation interval counter. If the compensation
 403  * interval counter equals zero then it is loaded with the contents of the CIR. If the
 404  * CIC does not equal zero then it is decremented once a second.
 405  */
 406 /*@{*/
 407 #define BP_RTC_TCR_CIC       (24U)         /*!< Bit position for RTC_TCR_CIC. */
 408 #define BM_RTC_TCR_CIC       (0xFF000000U) /*!< Bit mask for RTC_TCR_CIC. */
 409 #define BS_RTC_TCR_CIC       (8U)          /*!< Bit field size in bits for RTC_TCR_CIC. */
 410
 411 /*! @brief Read current value of the RTC_TCR_CIC field. */
 412 #define BR_RTC_TCR_CIC(x)    (HW_RTC_TCR(x).B.CIC)
 413 /*@}*/
 414
 415 /*******************************************************************************
 416  * HW_RTC_CR - RTC Control Register
 417  ******************************************************************************/
 418
 419 /*!
 420  * @brief HW_RTC_CR - RTC Control Register (RW)
 421  *
 422  * Reset value: 0x00000000U
 423  */
 424 typedef union _hw_rtc_cr
 425 {
 426     uint32_t U;
 427     struct _hw_rtc_cr_bitfields
 428     {
 429         uint32_t SWR : 1;              /*!< [0] Software Reset */
 430         uint32_t WPE : 1;              /*!< [1] Wakeup Pin Enable */
 431         uint32_t SUP : 1;              /*!< [2] Supervisor Access */
 432         uint32_t UM : 1;               /*!< [3] Update Mode */
 433         uint32_t WPS : 1;              /*!< [4] Wakeup Pin Select */
 434         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
 435         uint32_t OSCE : 1;             /*!< [8] Oscillator Enable */
 436         uint32_t CLKO : 1;             /*!< [9] Clock Output */
 437         uint32_t SC16P : 1;            /*!< [10] Oscillator 16pF Load Configure */
 438         uint32_t SC8P : 1;             /*!< [11] Oscillator 8pF Load Configure */
 439         uint32_t SC4P : 1;             /*!< [12] Oscillator 4pF Load Configure */
 440         uint32_t SC2P : 1;             /*!< [13] Oscillator 2pF Load Configure */
 441         uint32_t RESERVED1 : 18;       /*!< [31:14]  */
 442     } B;
 443 } hw_rtc_cr_t;
 444
 445 /*!
 446  * @name Constants and macros for entire RTC_CR register
 447  */
 448 /*@{*/
 449 #define HW_RTC_CR_ADDR(x)        ((x) + 0x10U)
 450
 451 #define HW_RTC_CR(x)             (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR(x))
 452 #define HW_RTC_CR_RD(x)          (HW_RTC_CR(x).U)
 453 #define HW_RTC_CR_WR(x, v)       (HW_RTC_CR(x).U = (v))
 454 #define HW_RTC_CR_SET(x, v)      (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) |  (v)))
 455 #define HW_RTC_CR_CLR(x, v)      (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) & ~(v)))
 456 #define HW_RTC_CR_TOG(x, v)      (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) ^  (v)))
 457 /*@}*/
 458
 459 /*
 460  * Constants & macros for individual RTC_CR bitfields
 461  */
 462
 463 /*!
 464  * @name Register RTC_CR, field SWR[0] (RW)
 465  *
 466  * Values:
 467  * - 0 - No effect.
 468  * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
 469  *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
 470  *     explicitly clearing it.
 471  */
 472 /*@{*/
 473 #define BP_RTC_CR_SWR        (0U)          /*!< Bit position for RTC_CR_SWR. */
 474 #define BM_RTC_CR_SWR        (0x00000001U) /*!< Bit mask for RTC_CR_SWR. */
 475 #define BS_RTC_CR_SWR        (1U)          /*!< Bit field size in bits for RTC_CR_SWR. */
 476
 477 /*! @brief Read current value of the RTC_CR_SWR field. */
 478 #define BR_RTC_CR_SWR(x)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR))
 479
 480 /*! @brief Format value for bitfield RTC_CR_SWR. */
 481 #define BF_RTC_CR_SWR(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SWR) & BM_RTC_CR_SWR)
 482
 483 /*! @brief Set the SWR field to a new value. */
 484 #define BW_RTC_CR_SWR(x, v)  (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR) = (v))
 485 /*@}*/
 486
 487 /*!
 488  * @name Register RTC_CR, field WPE[1] (RW)
 489  *
 490  * The wakeup pin is optional and not available on all devices.
 491  *
 492  * Values:
 493  * - 0 - Wakeup pin is disabled.
 494  * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
 495  *     asserts or the wakeup pin is turned on.
 496  */
 497 /*@{*/
 498 #define BP_RTC_CR_WPE        (1U)          /*!< Bit position for RTC_CR_WPE. */
 499 #define BM_RTC_CR_WPE        (0x00000002U) /*!< Bit mask for RTC_CR_WPE. */
 500 #define BS_RTC_CR_WPE        (1U)          /*!< Bit field size in bits for RTC_CR_WPE. */
 501
 502 /*! @brief Read current value of the RTC_CR_WPE field. */
 503 #define BR_RTC_CR_WPE(x)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE))
 504
 505 /*! @brief Format value for bitfield RTC_CR_WPE. */
 506 #define BF_RTC_CR_WPE(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPE) & BM_RTC_CR_WPE)
 507
 508 /*! @brief Set the WPE field to a new value. */
 509 #define BW_RTC_CR_WPE(x, v)  (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE) = (v))
 510 /*@}*/
 511
 512 /*!
 513  * @name Register RTC_CR, field SUP[2] (RW)
 514  *
 515  * Values:
 516  * - 0 - Non-supervisor mode write accesses are not supported and generate a bus
 517  *     error.
 518  * - 1 - Non-supervisor mode write accesses are supported.
 519  */
 520 /*@{*/
 521 #define BP_RTC_CR_SUP        (2U)          /*!< Bit position for RTC_CR_SUP. */
 522 #define BM_RTC_CR_SUP        (0x00000004U) /*!< Bit mask for RTC_CR_SUP. */
 523 #define BS_RTC_CR_SUP        (1U)          /*!< Bit field size in bits for RTC_CR_SUP. */
 524
 525 /*! @brief Read current value of the RTC_CR_SUP field. */
 526 #define BR_RTC_CR_SUP(x)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP))
 527
 528 /*! @brief Format value for bitfield RTC_CR_SUP. */
 529 #define BF_RTC_CR_SUP(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SUP) & BM_RTC_CR_SUP)
 530
 531 /*! @brief Set the SUP field to a new value. */
 532 #define BW_RTC_CR_SUP(x, v)  (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP) = (v))
 533 /*@}*/
 534
 535 /*!
 536  * @name Register RTC_CR, field UM[3] (RW)
 537  *
 538  * Allows SR[TCE] to be written even when the Status Register is locked. When
 539  * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
 540  * the SR[TCE] is clear.
 541  *
 542  * Values:
 543  * - 0 - Registers cannot be written when locked.
 544  * - 1 - Registers can be written when locked under limited conditions.
 545  */
 546 /*@{*/
 547 #define BP_RTC_CR_UM         (3U)          /*!< Bit position for RTC_CR_UM. */
 548 #define BM_RTC_CR_UM         (0x00000008U) /*!< Bit mask for RTC_CR_UM. */
 549 #define BS_RTC_CR_UM         (1U)          /*!< Bit field size in bits for RTC_CR_UM. */
 550
 551 /*! @brief Read current value of the RTC_CR_UM field. */
 552 #define BR_RTC_CR_UM(x)      (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM))
 553
 554 /*! @brief Format value for bitfield RTC_CR_UM. */
 555 #define BF_RTC_CR_UM(v)      ((uint32_t)((uint32_t)(v) << BP_RTC_CR_UM) & BM_RTC_CR_UM)
 556
 557 /*! @brief Set the UM field to a new value. */
 558 #define BW_RTC_CR_UM(x, v)   (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM) = (v))
 559 /*@}*/
 560
 561 /*!
 562  * @name Register RTC_CR, field WPS[4] (RW)
 563  *
 564  * The wakeup pin is optional and not available on all devices.
 565  *
 566  * Values:
 567  * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
 568  *     asserts or the wakeup pin is turned on.
 569  * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
 570  *     is turned on and the 32kHz clock is output to other peripherals.
 571  */
 572 /*@{*/
 573 #define BP_RTC_CR_WPS        (4U)          /*!< Bit position for RTC_CR_WPS. */
 574 #define BM_RTC_CR_WPS        (0x00000010U) /*!< Bit mask for RTC_CR_WPS. */
 575 #define BS_RTC_CR_WPS        (1U)          /*!< Bit field size in bits for RTC_CR_WPS. */
 576
 577 /*! @brief Read current value of the RTC_CR_WPS field. */
 578 #define BR_RTC_CR_WPS(x)     (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS))
 579
 580 /*! @brief Format value for bitfield RTC_CR_WPS. */
 581 #define BF_RTC_CR_WPS(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPS) & BM_RTC_CR_WPS)
 582
 583 /*! @brief Set the WPS field to a new value. */
 584 #define BW_RTC_CR_WPS(x, v)  (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS) = (v))
 585 /*@}*/
 586
 587 /*!
 588  * @name Register RTC_CR, field OSCE[8] (RW)
 589  *
 590  * Values:
 591  * - 0 - 32.768 kHz oscillator is disabled.
 592  * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
 593  *     oscillator startup time before enabling the time counter to allow the 32.768
 594  *     kHz clock time to stabilize.
 595  */
 596 /*@{*/
 597 #define BP_RTC_CR_OSCE       (8U)          /*!< Bit position for RTC_CR_OSCE. */
 598 #define BM_RTC_CR_OSCE       (0x00000100U) /*!< Bit mask for RTC_CR_OSCE. */
 599 #define BS_RTC_CR_OSCE       (1U)          /*!< Bit field size in bits for RTC_CR_OSCE. */
 600
 601 /*! @brief Read current value of the RTC_CR_OSCE field. */
 602 #define BR_RTC_CR_OSCE(x)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE))
 603
 604 /*! @brief Format value for bitfield RTC_CR_OSCE. */
 605 #define BF_RTC_CR_OSCE(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_OSCE) & BM_RTC_CR_OSCE)
 606
 607 /*! @brief Set the OSCE field to a new value. */
 608 #define BW_RTC_CR_OSCE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE) = (v))
 609 /*@}*/
 610
 611 /*!
 612  * @name Register RTC_CR, field CLKO[9] (RW)
 613  *
 614  * Values:
 615  * - 0 - The 32 kHz clock is output to other peripherals.
 616  * - 1 - The 32 kHz clock is not output to other peripherals.
 617  */
 618 /*@{*/
 619 #define BP_RTC_CR_CLKO       (9U)          /*!< Bit position for RTC_CR_CLKO. */
 620 #define BM_RTC_CR_CLKO       (0x00000200U) /*!< Bit mask for RTC_CR_CLKO. */
 621 #define BS_RTC_CR_CLKO       (1U)          /*!< Bit field size in bits for RTC_CR_CLKO. */
 622
 623 /*! @brief Read current value of the RTC_CR_CLKO field. */
 624 #define BR_RTC_CR_CLKO(x)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO))
 625
 626 /*! @brief Format value for bitfield RTC_CR_CLKO. */
 627 #define BF_RTC_CR_CLKO(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_CLKO) & BM_RTC_CR_CLKO)
 628
 629 /*! @brief Set the CLKO field to a new value. */
 630 #define BW_RTC_CR_CLKO(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO) = (v))
 631 /*@}*/
 632
 633 /*!
 634  * @name Register RTC_CR, field SC16P[10] (RW)
 635  *
 636  * Values:
 637  * - 0 - Disable the load.
 638  * - 1 - Enable the additional load.
 639  */
 640 /*@{*/
 641 #define BP_RTC_CR_SC16P      (10U)         /*!< Bit position for RTC_CR_SC16P. */
 642 #define BM_RTC_CR_SC16P      (0x00000400U) /*!< Bit mask for RTC_CR_SC16P. */
 643 #define BS_RTC_CR_SC16P      (1U)          /*!< Bit field size in bits for RTC_CR_SC16P. */
 644
 645 /*! @brief Read current value of the RTC_CR_SC16P field. */
 646 #define BR_RTC_CR_SC16P(x)   (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P))
 647
 648 /*! @brief Format value for bitfield RTC_CR_SC16P. */
 649 #define BF_RTC_CR_SC16P(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC16P) & BM_RTC_CR_SC16P)
 650
 651 /*! @brief Set the SC16P field to a new value. */
 652 #define BW_RTC_CR_SC16P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P) = (v))
 653 /*@}*/
 654
 655 /*!
 656  * @name Register RTC_CR, field SC8P[11] (RW)
 657  *
 658  * Values:
 659  * - 0 - Disable the load.
 660  * - 1 - Enable the additional load.
 661  */
 662 /*@{*/
 663 #define BP_RTC_CR_SC8P       (11U)         /*!< Bit position for RTC_CR_SC8P. */
 664 #define BM_RTC_CR_SC8P       (0x00000800U) /*!< Bit mask for RTC_CR_SC8P. */
 665 #define BS_RTC_CR_SC8P       (1U)          /*!< Bit field size in bits for RTC_CR_SC8P. */
 666
 667 /*! @brief Read current value of the RTC_CR_SC8P field. */
 668 #define BR_RTC_CR_SC8P(x)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P))
 669
 670 /*! @brief Format value for bitfield RTC_CR_SC8P. */
 671 #define BF_RTC_CR_SC8P(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC8P) & BM_RTC_CR_SC8P)
 672
 673 /*! @brief Set the SC8P field to a new value. */
 674 #define BW_RTC_CR_SC8P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P) = (v))
 675 /*@}*/
 676
 677 /*!
 678  * @name Register RTC_CR, field SC4P[12] (RW)
 679  *
 680  * Values:
 681  * - 0 - Disable the load.
 682  * - 1 - Enable the additional load.
 683  */
 684 /*@{*/
 685 #define BP_RTC_CR_SC4P       (12U)         /*!< Bit position for RTC_CR_SC4P. */
 686 #define BM_RTC_CR_SC4P       (0x00001000U) /*!< Bit mask for RTC_CR_SC4P. */
 687 #define BS_RTC_CR_SC4P       (1U)          /*!< Bit field size in bits for RTC_CR_SC4P. */
 688
 689 /*! @brief Read current value of the RTC_CR_SC4P field. */
 690 #define BR_RTC_CR_SC4P(x)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P))
 691
 692 /*! @brief Format value for bitfield RTC_CR_SC4P. */
 693 #define BF_RTC_CR_SC4P(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC4P) & BM_RTC_CR_SC4P)
 694
 695 /*! @brief Set the SC4P field to a new value. */
 696 #define BW_RTC_CR_SC4P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P) = (v))
 697 /*@}*/
 698
 699 /*!
 700  * @name Register RTC_CR, field SC2P[13] (RW)
 701  *
 702  * Values:
 703  * - 0 - Disable the load.
 704  * - 1 - Enable the additional load.
 705  */
 706 /*@{*/
 707 #define BP_RTC_CR_SC2P       (13U)         /*!< Bit position for RTC_CR_SC2P. */
 708 #define BM_RTC_CR_SC2P       (0x00002000U) /*!< Bit mask for RTC_CR_SC2P. */
 709 #define BS_RTC_CR_SC2P       (1U)          /*!< Bit field size in bits for RTC_CR_SC2P. */
 710
 711 /*! @brief Read current value of the RTC_CR_SC2P field. */
 712 #define BR_RTC_CR_SC2P(x)    (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P))
 713
 714 /*! @brief Format value for bitfield RTC_CR_SC2P. */
 715 #define BF_RTC_CR_SC2P(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC2P) & BM_RTC_CR_SC2P)
 716
 717 /*! @brief Set the SC2P field to a new value. */
 718 #define BW_RTC_CR_SC2P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P) = (v))
 719 /*@}*/
 720
 721 /*******************************************************************************
 722  * HW_RTC_SR - RTC Status Register
 723  ******************************************************************************/
 724
 725 /*!
 726  * @brief HW_RTC_SR - RTC Status Register (RW)
 727  *
 728  * Reset value: 0x00000001U
 729  */
 730 typedef union _hw_rtc_sr
 731 {
 732     uint32_t U;
 733     struct _hw_rtc_sr_bitfields
 734     {
 735         uint32_t TIF : 1;              /*!< [0] Time Invalid Flag */
 736         uint32_t TOF : 1;              /*!< [1] Time Overflow Flag */
 737         uint32_t TAF : 1;              /*!< [2] Time Alarm Flag */
 738         uint32_t RESERVED0 : 1;        /*!< [3]  */
 739         uint32_t TCE : 1;              /*!< [4] Time Counter Enable */
 740         uint32_t RESERVED1 : 27;       /*!< [31:5]  */
 741     } B;
 742 } hw_rtc_sr_t;
 743
 744 /*!
 745  * @name Constants and macros for entire RTC_SR register
 746  */
 747 /*@{*/
 748 #define HW_RTC_SR_ADDR(x)        ((x) + 0x14U)
 749
 750 #define HW_RTC_SR(x)             (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR(x))
 751 #define HW_RTC_SR_RD(x)          (HW_RTC_SR(x).U)
 752 #define HW_RTC_SR_WR(x, v)       (HW_RTC_SR(x).U = (v))
 753 #define HW_RTC_SR_SET(x, v)      (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) |  (v)))
 754 #define HW_RTC_SR_CLR(x, v)      (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) & ~(v)))
 755 #define HW_RTC_SR_TOG(x, v)      (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) ^  (v)))
 756 /*@}*/
 757
 758 /*
 759  * Constants & macros for individual RTC_SR bitfields
 760  */
 761
 762 /*!
 763  * @name Register RTC_SR, field TIF[0] (RO)
 764  *
 765  * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
 766  * do not increment and read as zero when this bit is set. This bit is cleared by
 767  * writing the TSR register when the time counter is disabled.
 768  *
 769  * Values:
 770  * - 0 - Time is valid.
 771  * - 1 - Time is invalid and time counter is read as zero.
 772  */
 773 /*@{*/
 774 #define BP_RTC_SR_TIF        (0U)          /*!< Bit position for RTC_SR_TIF. */
 775 #define BM_RTC_SR_TIF        (0x00000001U) /*!< Bit mask for RTC_SR_TIF. */
 776 #define BS_RTC_SR_TIF        (1U)          /*!< Bit field size in bits for RTC_SR_TIF. */
 777
 778 /*! @brief Read current value of the RTC_SR_TIF field. */
 779 #define BR_RTC_SR_TIF(x)     (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TIF))
 780 /*@}*/
 781
 782 /*!
 783  * @name Register RTC_SR, field TOF[1] (RO)
 784  *
 785  * Time overflow flag is set when the time counter is enabled and overflows. The
 786  * TSR and TPR do not increment and read as zero when this bit is set. This bit
 787  * is cleared by writing the TSR register when the time counter is disabled.
 788  *
 789  * Values:
 790  * - 0 - Time overflow has not occurred.
 791  * - 1 - Time overflow has occurred and time counter is read as zero.
 792  */
 793 /*@{*/
 794 #define BP_RTC_SR_TOF        (1U)          /*!< Bit position for RTC_SR_TOF. */
 795 #define BM_RTC_SR_TOF        (0x00000002U) /*!< Bit mask for RTC_SR_TOF. */
 796 #define BS_RTC_SR_TOF        (1U)          /*!< Bit field size in bits for RTC_SR_TOF. */
 797
 798 /*! @brief Read current value of the RTC_SR_TOF field. */
 799 #define BR_RTC_SR_TOF(x)     (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TOF))
 800 /*@}*/
 801
 802 /*!
 803  * @name Register RTC_SR, field TAF[2] (RO)
 804  *
 805  * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
 806  * increments. This bit is cleared by writing the TAR register.
 807  *
 808  * Values:
 809  * - 0 - Time alarm has not occurred.
 810  * - 1 - Time alarm has occurred.
 811  */
 812 /*@{*/
 813 #define BP_RTC_SR_TAF        (2U)          /*!< Bit position for RTC_SR_TAF. */
 814 #define BM_RTC_SR_TAF        (0x00000004U) /*!< Bit mask for RTC_SR_TAF. */
 815 #define BS_RTC_SR_TAF        (1U)          /*!< Bit field size in bits for RTC_SR_TAF. */
 816
 817 /*! @brief Read current value of the RTC_SR_TAF field. */
 818 #define BR_RTC_SR_TAF(x)     (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TAF))
 819 /*@}*/
 820
 821 /*!
 822  * @name Register RTC_SR, field TCE[4] (RW)
 823  *
 824  * When time counter is disabled the TSR register and TPR register are
 825  * writeable, but do not increment. When time counter is enabled the TSR register and TPR
 826  * register are not writeable, but increment.
 827  *
 828  * Values:
 829  * - 0 - Time counter is disabled.
 830  * - 1 - Time counter is enabled.
 831  */
 832 /*@{*/
 833 #define BP_RTC_SR_TCE        (4U)          /*!< Bit position for RTC_SR_TCE. */
 834 #define BM_RTC_SR_TCE        (0x00000010U) /*!< Bit mask for RTC_SR_TCE. */
 835 #define BS_RTC_SR_TCE        (1U)          /*!< Bit field size in bits for RTC_SR_TCE. */
 836
 837 /*! @brief Read current value of the RTC_SR_TCE field. */
 838 #define BR_RTC_SR_TCE(x)     (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE))
 839
 840 /*! @brief Format value for bitfield RTC_SR_TCE. */
 841 #define BF_RTC_SR_TCE(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_SR_TCE) & BM_RTC_SR_TCE)
 842
 843 /*! @brief Set the TCE field to a new value. */
 844 #define BW_RTC_SR_TCE(x, v)  (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE) = (v))
 845 /*@}*/
 846
 847 /*******************************************************************************
 848  * HW_RTC_LR - RTC Lock Register
 849  ******************************************************************************/
 850
 851 /*!
 852  * @brief HW_RTC_LR - RTC Lock Register (RW)
 853  *
 854  * Reset value: 0x000000FFU
 855  */
 856 typedef union _hw_rtc_lr
 857 {
 858     uint32_t U;
 859     struct _hw_rtc_lr_bitfields
 860     {
 861         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
 862         uint32_t TCL : 1;              /*!< [3] Time Compensation Lock */
 863         uint32_t CRL : 1;              /*!< [4] Control Register Lock */
 864         uint32_t SRL : 1;              /*!< [5] Status Register Lock */
 865         uint32_t LRL : 1;              /*!< [6] Lock Register Lock */
 866         uint32_t RESERVED1 : 25;       /*!< [31:7]  */
 867     } B;
 868 } hw_rtc_lr_t;
 869
 870 /*!
 871  * @name Constants and macros for entire RTC_LR register
 872  */
 873 /*@{*/
 874 #define HW_RTC_LR_ADDR(x)        ((x) + 0x18U)
 875
 876 #define HW_RTC_LR(x)             (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR(x))
 877 #define HW_RTC_LR_RD(x)          (HW_RTC_LR(x).U)
 878 #define HW_RTC_LR_WR(x, v)       (HW_RTC_LR(x).U = (v))
 879 #define HW_RTC_LR_SET(x, v)      (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) |  (v)))
 880 #define HW_RTC_LR_CLR(x, v)      (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) & ~(v)))
 881 #define HW_RTC_LR_TOG(x, v)      (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) ^  (v)))
 882 /*@}*/
 883
 884 /*
 885  * Constants & macros for individual RTC_LR bitfields
 886  */
 887
 888 /*!
 889  * @name Register RTC_LR, field TCL[3] (RW)
 890  *
 891  * After being cleared, this bit can be set only by VBAT POR or software reset.
 892  *
 893  * Values:
 894  * - 0 - Time Compensation Register is locked and writes are ignored.
 895  * - 1 - Time Compensation Register is not locked and writes complete as normal.
 896  */
 897 /*@{*/
 898 #define BP_RTC_LR_TCL        (3U)          /*!< Bit position for RTC_LR_TCL. */
 899 #define BM_RTC_LR_TCL        (0x00000008U) /*!< Bit mask for RTC_LR_TCL. */
 900 #define BS_RTC_LR_TCL        (1U)          /*!< Bit field size in bits for RTC_LR_TCL. */
 901
 902 /*! @brief Read current value of the RTC_LR_TCL field. */
 903 #define BR_RTC_LR_TCL(x)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL))
 904
 905 /*! @brief Format value for bitfield RTC_LR_TCL. */
 906 #define BF_RTC_LR_TCL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_TCL) & BM_RTC_LR_TCL)
 907
 908 /*! @brief Set the TCL field to a new value. */
 909 #define BW_RTC_LR_TCL(x, v)  (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL) = (v))
 910 /*@}*/
 911
 912 /*!
 913  * @name Register RTC_LR, field CRL[4] (RW)
 914  *
 915  * After being cleared, this bit can only be set by VBAT POR.
 916  *
 917  * Values:
 918  * - 0 - Control Register is locked and writes are ignored.
 919  * - 1 - Control Register is not locked and writes complete as normal.
 920  */
 921 /*@{*/
 922 #define BP_RTC_LR_CRL        (4U)          /*!< Bit position for RTC_LR_CRL. */
 923 #define BM_RTC_LR_CRL        (0x00000010U) /*!< Bit mask for RTC_LR_CRL. */
 924 #define BS_RTC_LR_CRL        (1U)          /*!< Bit field size in bits for RTC_LR_CRL. */
 925
 926 /*! @brief Read current value of the RTC_LR_CRL field. */
 927 #define BR_RTC_LR_CRL(x)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL))
 928
 929 /*! @brief Format value for bitfield RTC_LR_CRL. */
 930 #define BF_RTC_LR_CRL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_CRL) & BM_RTC_LR_CRL)
 931
 932 /*! @brief Set the CRL field to a new value. */
 933 #define BW_RTC_LR_CRL(x, v)  (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL) = (v))
 934 /*@}*/
 935
 936 /*!
 937  * @name Register RTC_LR, field SRL[5] (RW)
 938  *
 939  * After being cleared, this bit can be set only by VBAT POR or software reset.
 940  *
 941  * Values:
 942  * - 0 - Status Register is locked and writes are ignored.
 943  * - 1 - Status Register is not locked and writes complete as normal.
 944  */
 945 /*@{*/
 946 #define BP_RTC_LR_SRL        (5U)          /*!< Bit position for RTC_LR_SRL. */
 947 #define BM_RTC_LR_SRL        (0x00000020U) /*!< Bit mask for RTC_LR_SRL. */
 948 #define BS_RTC_LR_SRL        (1U)          /*!< Bit field size in bits for RTC_LR_SRL. */
 949
 950 /*! @brief Read current value of the RTC_LR_SRL field. */
 951 #define BR_RTC_LR_SRL(x)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL))
 952
 953 /*! @brief Format value for bitfield RTC_LR_SRL. */
 954 #define BF_RTC_LR_SRL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_SRL) & BM_RTC_LR_SRL)
 955
 956 /*! @brief Set the SRL field to a new value. */
 957 #define BW_RTC_LR_SRL(x, v)  (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL) = (v))
 958 /*@}*/
 959
 960 /*!
 961  * @name Register RTC_LR, field LRL[6] (RW)
 962  *
 963  * After being cleared, this bit can be set only by VBAT POR or software reset.
 964  *
 965  * Values:
 966  * - 0 - Lock Register is locked and writes are ignored.
 967  * - 1 - Lock Register is not locked and writes complete as normal.
 968  */
 969 /*@{*/
 970 #define BP_RTC_LR_LRL        (6U)          /*!< Bit position for RTC_LR_LRL. */
 971 #define BM_RTC_LR_LRL        (0x00000040U) /*!< Bit mask for RTC_LR_LRL. */
 972 #define BS_RTC_LR_LRL        (1U)          /*!< Bit field size in bits for RTC_LR_LRL. */
 973
 974 /*! @brief Read current value of the RTC_LR_LRL field. */
 975 #define BR_RTC_LR_LRL(x)     (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL))
 976
 977 /*! @brief Format value for bitfield RTC_LR_LRL. */
 978 #define BF_RTC_LR_LRL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_LRL) & BM_RTC_LR_LRL)
 979
 980 /*! @brief Set the LRL field to a new value. */
 981 #define BW_RTC_LR_LRL(x, v)  (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL) = (v))
 982 /*@}*/
 983
 984 /*******************************************************************************
 985  * HW_RTC_IER - RTC Interrupt Enable Register
 986  ******************************************************************************/
 987
 988 /*!
 989  * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
 990  *
 991  * Reset value: 0x00000007U
 992  */
 993 typedef union _hw_rtc_ier
 994 {
 995     uint32_t U;
 996     struct _hw_rtc_ier_bitfields
 997     {
 998         uint32_t TIIE : 1;             /*!< [0] Time Invalid Interrupt Enable */
 999         uint32_t TOIE : 1;             /*!< [1] Time Overflow Interrupt Enable */
1000         uint32_t TAIE : 1;             /*!< [2] Time Alarm Interrupt Enable */
1001         uint32_t RESERVED0 : 1;        /*!< [3]  */
1002         uint32_t TSIE : 1;             /*!< [4] Time Seconds Interrupt Enable */
1003         uint32_t RESERVED1 : 2;        /*!< [6:5]  */
1004         uint32_t WPON : 1;             /*!< [7] Wakeup Pin On */
1005         uint32_t RESERVED2 : 24;       /*!< [31:8]  */
1006     } B;
1007 } hw_rtc_ier_t;
1008
1009 /*!
1010  * @name Constants and macros for entire RTC_IER register
1011  */
1012 /*@{*/
1013 #define HW_RTC_IER_ADDR(x)       ((x) + 0x1CU)
1014
1015 #define HW_RTC_IER(x)            (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR(x))
1016 #define HW_RTC_IER_RD(x)         (HW_RTC_IER(x).U)
1017 #define HW_RTC_IER_WR(x, v)      (HW_RTC_IER(x).U = (v))
1018 #define HW_RTC_IER_SET(x, v)     (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) |  (v)))
1019 #define HW_RTC_IER_CLR(x, v)     (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) & ~(v)))
1020 #define HW_RTC_IER_TOG(x, v)     (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) ^  (v)))
1021 /*@}*/
1022
1023 /*
1024  * Constants & macros for individual RTC_IER bitfields
1025  */
1026
1027 /*!
1028  * @name Register RTC_IER, field TIIE[0] (RW)
1029  *
1030  * Values:
1031  * - 0 - Time invalid flag does not generate an interrupt.
1032  * - 1 - Time invalid flag does generate an interrupt.
1033  */
1034 /*@{*/
1035 #define BP_RTC_IER_TIIE      (0U)          /*!< Bit position for RTC_IER_TIIE. */
1036 #define BM_RTC_IER_TIIE      (0x00000001U) /*!< Bit mask for RTC_IER_TIIE. */
1037 #define BS_RTC_IER_TIIE      (1U)          /*!< Bit field size in bits for RTC_IER_TIIE. */
1038
1039 /*! @brief Read current value of the RTC_IER_TIIE field. */
1040 #define BR_RTC_IER_TIIE(x)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE))
1041
1042 /*! @brief Format value for bitfield RTC_IER_TIIE. */
1043 #define BF_RTC_IER_TIIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TIIE) & BM_RTC_IER_TIIE)
1044
1045 /*! @brief Set the TIIE field to a new value. */
1046 #define BW_RTC_IER_TIIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE) = (v))
1047 /*@}*/
1048
1049 /*!
1050  * @name Register RTC_IER, field TOIE[1] (RW)
1051  *
1052  * Values:
1053  * - 0 - Time overflow flag does not generate an interrupt.
1054  * - 1 - Time overflow flag does generate an interrupt.
1055  */
1056 /*@{*/
1057 #define BP_RTC_IER_TOIE      (1U)          /*!< Bit position for RTC_IER_TOIE. */
1058 #define BM_RTC_IER_TOIE      (0x00000002U) /*!< Bit mask for RTC_IER_TOIE. */
1059 #define BS_RTC_IER_TOIE      (1U)          /*!< Bit field size in bits for RTC_IER_TOIE. */
1060
1061 /*! @brief Read current value of the RTC_IER_TOIE field. */
1062 #define BR_RTC_IER_TOIE(x)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE))
1063
1064 /*! @brief Format value for bitfield RTC_IER_TOIE. */
1065 #define BF_RTC_IER_TOIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TOIE) & BM_RTC_IER_TOIE)
1066
1067 /*! @brief Set the TOIE field to a new value. */
1068 #define BW_RTC_IER_TOIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE) = (v))
1069 /*@}*/
1070
1071 /*!
1072  * @name Register RTC_IER, field TAIE[2] (RW)
1073  *
1074  * Values:
1075  * - 0 - Time alarm flag does not generate an interrupt.
1076  * - 1 - Time alarm flag does generate an interrupt.
1077  */
1078 /*@{*/
1079 #define BP_RTC_IER_TAIE      (2U)          /*!< Bit position for RTC_IER_TAIE. */
1080 #define BM_RTC_IER_TAIE      (0x00000004U) /*!< Bit mask for RTC_IER_TAIE. */
1081 #define BS_RTC_IER_TAIE      (1U)          /*!< Bit field size in bits for RTC_IER_TAIE. */
1082
1083 /*! @brief Read current value of the RTC_IER_TAIE field. */
1084 #define BR_RTC_IER_TAIE(x)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE))
1085
1086 /*! @brief Format value for bitfield RTC_IER_TAIE. */
1087 #define BF_RTC_IER_TAIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TAIE) & BM_RTC_IER_TAIE)
1088
1089 /*! @brief Set the TAIE field to a new value. */
1090 #define BW_RTC_IER_TAIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE) = (v))
1091 /*@}*/
1092
1093 /*!
1094  * @name Register RTC_IER, field TSIE[4] (RW)
1095  *
1096  * The seconds interrupt is an edge-sensitive interrupt with a dedicated
1097  * interrupt vector. It is generated once a second and requires no software overhead
1098  * (there is no corresponding status flag to clear).
1099  *
1100  * Values:
1101  * - 0 - Seconds interrupt is disabled.
1102  * - 1 - Seconds interrupt is enabled.
1103  */
1104 /*@{*/
1105 #define BP_RTC_IER_TSIE      (4U)          /*!< Bit position for RTC_IER_TSIE. */
1106 #define BM_RTC_IER_TSIE      (0x00000010U) /*!< Bit mask for RTC_IER_TSIE. */
1107 #define BS_RTC_IER_TSIE      (1U)          /*!< Bit field size in bits for RTC_IER_TSIE. */
1108
1109 /*! @brief Read current value of the RTC_IER_TSIE field. */
1110 #define BR_RTC_IER_TSIE(x)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE))
1111
1112 /*! @brief Format value for bitfield RTC_IER_TSIE. */
1113 #define BF_RTC_IER_TSIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TSIE) & BM_RTC_IER_TSIE)
1114
1115 /*! @brief Set the TSIE field to a new value. */
1116 #define BW_RTC_IER_TSIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE) = (v))
1117 /*@}*/
1118
1119 /*!
1120  * @name Register RTC_IER, field WPON[7] (RW)
1121  *
1122  * The wakeup pin is optional and not available on all devices. Whenever the
1123  * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
1124  *
1125  * Values:
1126  * - 0 - No effect.
1127  * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
1128  */
1129 /*@{*/
1130 #define BP_RTC_IER_WPON      (7U)          /*!< Bit position for RTC_IER_WPON. */
1131 #define BM_RTC_IER_WPON      (0x00000080U) /*!< Bit mask for RTC_IER_WPON. */
1132 #define BS_RTC_IER_WPON      (1U)          /*!< Bit field size in bits for RTC_IER_WPON. */
1133
1134 /*! @brief Read current value of the RTC_IER_WPON field. */
1135 #define BR_RTC_IER_WPON(x)   (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON))
1136
1137 /*! @brief Format value for bitfield RTC_IER_WPON. */
1138 #define BF_RTC_IER_WPON(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_WPON) & BM_RTC_IER_WPON)
1139
1140 /*! @brief Set the WPON field to a new value. */
1141 #define BW_RTC_IER_WPON(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON) = (v))
1142 /*@}*/
1143
1144 /*******************************************************************************
1145  * HW_RTC_WAR - RTC Write Access Register
1146  ******************************************************************************/
1147
1148 /*!
1149  * @brief HW_RTC_WAR - RTC Write Access Register (RW)
1150  *
1151  * Reset value: 0x000000FFU
1152  */
1153 typedef union _hw_rtc_war
1154 {
1155     uint32_t U;
1156     struct _hw_rtc_war_bitfields
1157     {
1158         uint32_t TSRW : 1;             /*!< [0] Time Seconds Register Write */
1159         uint32_t TPRW : 1;             /*!< [1] Time Prescaler Register Write */
1160         uint32_t TARW : 1;             /*!< [2] Time Alarm Register Write */
1161         uint32_t TCRW : 1;             /*!< [3] Time Compensation Register Write */
1162         uint32_t CRW : 1;              /*!< [4] Control Register Write */
1163         uint32_t SRW : 1;              /*!< [5] Status Register Write */
1164         uint32_t LRW : 1;              /*!< [6] Lock Register Write */
1165         uint32_t IERW : 1;             /*!< [7] Interrupt Enable Register Write */
1166         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
1167     } B;
1168 } hw_rtc_war_t;
1169
1170 /*!
1171  * @name Constants and macros for entire RTC_WAR register
1172  */
1173 /*@{*/
1174 #define HW_RTC_WAR_ADDR(x)       ((x) + 0x800U)
1175
1176 #define HW_RTC_WAR(x)            (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR(x))
1177 #define HW_RTC_WAR_RD(x)         (HW_RTC_WAR(x).U)
1178 #define HW_RTC_WAR_WR(x, v)      (HW_RTC_WAR(x).U = (v))
1179 #define HW_RTC_WAR_SET(x, v)     (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) |  (v)))
1180 #define HW_RTC_WAR_CLR(x, v)     (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) & ~(v)))
1181 #define HW_RTC_WAR_TOG(x, v)     (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) ^  (v)))
1182 /*@}*/
1183
1184 /*
1185  * Constants & macros for individual RTC_WAR bitfields
1186  */
1187
1188 /*!
1189  * @name Register RTC_WAR, field TSRW[0] (RW)
1190  *
1191  * After being cleared, this bit is set only by system reset. It is not affected
1192  * by VBAT POR or software reset.
1193  *
1194  * Values:
1195  * - 0 - Writes to the Time Seconds Register are ignored.
1196  * - 1 - Writes to the Time Seconds Register complete as normal.
1197  */
1198 /*@{*/
1199 #define BP_RTC_WAR_TSRW      (0U)          /*!< Bit position for RTC_WAR_TSRW. */
1200 #define BM_RTC_WAR_TSRW      (0x00000001U) /*!< Bit mask for RTC_WAR_TSRW. */
1201 #define BS_RTC_WAR_TSRW      (1U)          /*!< Bit field size in bits for RTC_WAR_TSRW. */
1202
1203 /*! @brief Read current value of the RTC_WAR_TSRW field. */
1204 #define BR_RTC_WAR_TSRW(x)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW))
1205
1206 /*! @brief Format value for bitfield RTC_WAR_TSRW. */
1207 #define BF_RTC_WAR_TSRW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TSRW) & BM_RTC_WAR_TSRW)
1208
1209 /*! @brief Set the TSRW field to a new value. */
1210 #define BW_RTC_WAR_TSRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW) = (v))
1211 /*@}*/
1212
1213 /*!
1214  * @name Register RTC_WAR, field TPRW[1] (RW)
1215  *
1216  * After being cleared, this bit is set only by system reset. It is not affected
1217  * by VBAT POR or software reset.
1218  *
1219  * Values:
1220  * - 0 - Writes to the Time Prescaler Register are ignored.
1221  * - 1 - Writes to the Time Prescaler Register complete as normal.
1222  */
1223 /*@{*/
1224 #define BP_RTC_WAR_TPRW      (1U)          /*!< Bit position for RTC_WAR_TPRW. */
1225 #define BM_RTC_WAR_TPRW      (0x00000002U) /*!< Bit mask for RTC_WAR_TPRW. */
1226 #define BS_RTC_WAR_TPRW      (1U)          /*!< Bit field size in bits for RTC_WAR_TPRW. */
1227
1228 /*! @brief Read current value of the RTC_WAR_TPRW field. */
1229 #define BR_RTC_WAR_TPRW(x)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW))
1230
1231 /*! @brief Format value for bitfield RTC_WAR_TPRW. */
1232 #define BF_RTC_WAR_TPRW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TPRW) & BM_RTC_WAR_TPRW)
1233
1234 /*! @brief Set the TPRW field to a new value. */
1235 #define BW_RTC_WAR_TPRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW) = (v))
1236 /*@}*/
1237
1238 /*!
1239  * @name Register RTC_WAR, field TARW[2] (RW)
1240  *
1241  * After being cleared, this bit is set only by system reset. It is not affected
1242  * by VBAT POR or software reset.
1243  *
1244  * Values:
1245  * - 0 - Writes to the Time Alarm Register are ignored.
1246  * - 1 - Writes to the Time Alarm Register complete as normal.
1247  */
1248 /*@{*/
1249 #define BP_RTC_WAR_TARW      (2U)          /*!< Bit position for RTC_WAR_TARW. */
1250 #define BM_RTC_WAR_TARW      (0x00000004U) /*!< Bit mask for RTC_WAR_TARW. */
1251 #define BS_RTC_WAR_TARW      (1U)          /*!< Bit field size in bits for RTC_WAR_TARW. */
1252
1253 /*! @brief Read current value of the RTC_WAR_TARW field. */
1254 #define BR_RTC_WAR_TARW(x)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW))
1255
1256 /*! @brief Format value for bitfield RTC_WAR_TARW. */
1257 #define BF_RTC_WAR_TARW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TARW) & BM_RTC_WAR_TARW)
1258
1259 /*! @brief Set the TARW field to a new value. */
1260 #define BW_RTC_WAR_TARW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW) = (v))
1261 /*@}*/
1262
1263 /*!
1264  * @name Register RTC_WAR, field TCRW[3] (RW)
1265  *
1266  * After being cleared, this bit is set only by system reset. It is not affected
1267  * by VBAT POR or software reset.
1268  *
1269  * Values:
1270  * - 0 - Writes to the Time Compensation Register are ignored.
1271  * - 1 - Writes to the Time Compensation Register complete as normal.
1272  */
1273 /*@{*/
1274 #define BP_RTC_WAR_TCRW      (3U)          /*!< Bit position for RTC_WAR_TCRW. */
1275 #define BM_RTC_WAR_TCRW      (0x00000008U) /*!< Bit mask for RTC_WAR_TCRW. */
1276 #define BS_RTC_WAR_TCRW      (1U)          /*!< Bit field size in bits for RTC_WAR_TCRW. */
1277
1278 /*! @brief Read current value of the RTC_WAR_TCRW field. */
1279 #define BR_RTC_WAR_TCRW(x)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW))
1280
1281 /*! @brief Format value for bitfield RTC_WAR_TCRW. */
1282 #define BF_RTC_WAR_TCRW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TCRW) & BM_RTC_WAR_TCRW)
1283
1284 /*! @brief Set the TCRW field to a new value. */
1285 #define BW_RTC_WAR_TCRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW) = (v))
1286 /*@}*/
1287
1288 /*!
1289  * @name Register RTC_WAR, field CRW[4] (RW)
1290  *
1291  * After being cleared, this bit is set only by system reset. It is not affected
1292  * by VBAT POR or software reset.
1293  *
1294  * Values:
1295  * - 0 - Writes to the Control Register are ignored.
1296  * - 1 - Writes to the Control Register complete as normal.
1297  */
1298 /*@{*/
1299 #define BP_RTC_WAR_CRW       (4U)          /*!< Bit position for RTC_WAR_CRW. */
1300 #define BM_RTC_WAR_CRW       (0x00000010U) /*!< Bit mask for RTC_WAR_CRW. */
1301 #define BS_RTC_WAR_CRW       (1U)          /*!< Bit field size in bits for RTC_WAR_CRW. */
1302
1303 /*! @brief Read current value of the RTC_WAR_CRW field. */
1304 #define BR_RTC_WAR_CRW(x)    (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW))
1305
1306 /*! @brief Format value for bitfield RTC_WAR_CRW. */
1307 #define BF_RTC_WAR_CRW(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_CRW) & BM_RTC_WAR_CRW)
1308
1309 /*! @brief Set the CRW field to a new value. */
1310 #define BW_RTC_WAR_CRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW) = (v))
1311 /*@}*/
1312
1313 /*!
1314  * @name Register RTC_WAR, field SRW[5] (RW)
1315  *
1316  * After being cleared, this bit is set only by system reset. It is not affected
1317  * by VBAT POR or software reset.
1318  *
1319  * Values:
1320  * - 0 - Writes to the Status Register are ignored.
1321  * - 1 - Writes to the Status Register complete as normal.
1322  */
1323 /*@{*/
1324 #define BP_RTC_WAR_SRW       (5U)          /*!< Bit position for RTC_WAR_SRW. */
1325 #define BM_RTC_WAR_SRW       (0x00000020U) /*!< Bit mask for RTC_WAR_SRW. */
1326 #define BS_RTC_WAR_SRW       (1U)          /*!< Bit field size in bits for RTC_WAR_SRW. */
1327
1328 /*! @brief Read current value of the RTC_WAR_SRW field. */
1329 #define BR_RTC_WAR_SRW(x)    (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW))
1330
1331 /*! @brief Format value for bitfield RTC_WAR_SRW. */
1332 #define BF_RTC_WAR_SRW(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_SRW) & BM_RTC_WAR_SRW)
1333
1334 /*! @brief Set the SRW field to a new value. */
1335 #define BW_RTC_WAR_SRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW) = (v))
1336 /*@}*/
1337
1338 /*!
1339  * @name Register RTC_WAR, field LRW[6] (RW)
1340  *
1341  * After being cleared, this bit is set only by system reset. It is not affected
1342  * by VBAT POR or software reset.
1343  *
1344  * Values:
1345  * - 0 - Writes to the Lock Register are ignored.
1346  * - 1 - Writes to the Lock Register complete as normal.
1347  */
1348 /*@{*/
1349 #define BP_RTC_WAR_LRW       (6U)          /*!< Bit position for RTC_WAR_LRW. */
1350 #define BM_RTC_WAR_LRW       (0x00000040U) /*!< Bit mask for RTC_WAR_LRW. */
1351 #define BS_RTC_WAR_LRW       (1U)          /*!< Bit field size in bits for RTC_WAR_LRW. */
1352
1353 /*! @brief Read current value of the RTC_WAR_LRW field. */
1354 #define BR_RTC_WAR_LRW(x)    (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW))
1355
1356 /*! @brief Format value for bitfield RTC_WAR_LRW. */
1357 #define BF_RTC_WAR_LRW(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_LRW) & BM_RTC_WAR_LRW)
1358
1359 /*! @brief Set the LRW field to a new value. */
1360 #define BW_RTC_WAR_LRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW) = (v))
1361 /*@}*/
1362
1363 /*!
1364  * @name Register RTC_WAR, field IERW[7] (RW)
1365  *
1366  * After being cleared, this bit is set only by system reset. It is not affected
1367  * by VBAT POR or software reset.
1368  *
1369  * Values:
1370  * - 0 - Writes to the Interupt Enable Register are ignored.
1371  * - 1 - Writes to the Interrupt Enable Register complete as normal.
1372  */
1373 /*@{*/
1374 #define BP_RTC_WAR_IERW      (7U)          /*!< Bit position for RTC_WAR_IERW. */
1375 #define BM_RTC_WAR_IERW      (0x00000080U) /*!< Bit mask for RTC_WAR_IERW. */
1376 #define BS_RTC_WAR_IERW      (1U)          /*!< Bit field size in bits for RTC_WAR_IERW. */
1377
1378 /*! @brief Read current value of the RTC_WAR_IERW field. */
1379 #define BR_RTC_WAR_IERW(x)   (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW))
1380
1381 /*! @brief Format value for bitfield RTC_WAR_IERW. */
1382 #define BF_RTC_WAR_IERW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_IERW) & BM_RTC_WAR_IERW)
1383
1384 /*! @brief Set the IERW field to a new value. */
1385 #define BW_RTC_WAR_IERW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW) = (v))
1386 /*@}*/
1387
1388 /*******************************************************************************
1389  * HW_RTC_RAR - RTC Read Access Register
1390  ******************************************************************************/
1391
1392 /*!
1393  * @brief HW_RTC_RAR - RTC Read Access Register (RW)
1394  *
1395  * Reset value: 0x000000FFU
1396  */
1397 typedef union _hw_rtc_rar
1398 {
1399     uint32_t U;
1400     struct _hw_rtc_rar_bitfields
1401     {
1402         uint32_t TSRR : 1;             /*!< [0] Time Seconds Register Read */
1403         uint32_t TPRR : 1;             /*!< [1] Time Prescaler Register Read */
1404         uint32_t TARR : 1;             /*!< [2] Time Alarm Register Read */
1405         uint32_t TCRR : 1;             /*!< [3] Time Compensation Register Read */
1406         uint32_t CRR : 1;              /*!< [4] Control Register Read */
1407         uint32_t SRR : 1;              /*!< [5] Status Register Read */
1408         uint32_t LRR : 1;              /*!< [6] Lock Register Read */
1409         uint32_t IERR : 1;             /*!< [7] Interrupt Enable Register Read */
1410         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
1411     } B;
1412 } hw_rtc_rar_t;
1413
1414 /*!
1415  * @name Constants and macros for entire RTC_RAR register
1416  */
1417 /*@{*/
1418 #define HW_RTC_RAR_ADDR(x)       ((x) + 0x804U)
1419
1420 #define HW_RTC_RAR(x)            (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR(x))
1421 #define HW_RTC_RAR_RD(x)         (HW_RTC_RAR(x).U)
1422 #define HW_RTC_RAR_WR(x, v)      (HW_RTC_RAR(x).U = (v))
1423 #define HW_RTC_RAR_SET(x, v)     (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) |  (v)))
1424 #define HW_RTC_RAR_CLR(x, v)     (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) & ~(v)))
1425 #define HW_RTC_RAR_TOG(x, v)     (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) ^  (v)))
1426 /*@}*/
1427
1428 /*
1429  * Constants & macros for individual RTC_RAR bitfields
1430  */
1431
1432 /*!
1433  * @name Register RTC_RAR, field TSRR[0] (RW)
1434  *
1435  * After being cleared, this bit is set only by system reset. It is not affected
1436  * by VBAT POR or software reset.
1437  *
1438  * Values:
1439  * - 0 - Reads to the Time Seconds Register are ignored.
1440  * - 1 - Reads to the Time Seconds Register complete as normal.
1441  */
1442 /*@{*/
1443 #define BP_RTC_RAR_TSRR      (0U)          /*!< Bit position for RTC_RAR_TSRR. */
1444 #define BM_RTC_RAR_TSRR      (0x00000001U) /*!< Bit mask for RTC_RAR_TSRR. */
1445 #define BS_RTC_RAR_TSRR      (1U)          /*!< Bit field size in bits for RTC_RAR_TSRR. */
1446
1447 /*! @brief Read current value of the RTC_RAR_TSRR field. */
1448 #define BR_RTC_RAR_TSRR(x)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR))
1449
1450 /*! @brief Format value for bitfield RTC_RAR_TSRR. */
1451 #define BF_RTC_RAR_TSRR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TSRR) & BM_RTC_RAR_TSRR)
1452
1453 /*! @brief Set the TSRR field to a new value. */
1454 #define BW_RTC_RAR_TSRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR) = (v))
1455 /*@}*/
1456
1457 /*!
1458  * @name Register RTC_RAR, field TPRR[1] (RW)
1459  *
1460  * After being cleared, this bit is set only by system reset. It is not affected
1461  * by VBAT POR or software reset.
1462  *
1463  * Values:
1464  * - 0 - Reads to the Time Pprescaler Register are ignored.
1465  * - 1 - Reads to the Time Prescaler Register complete as normal.
1466  */
1467 /*@{*/
1468 #define BP_RTC_RAR_TPRR      (1U)          /*!< Bit position for RTC_RAR_TPRR. */
1469 #define BM_RTC_RAR_TPRR      (0x00000002U) /*!< Bit mask for RTC_RAR_TPRR. */
1470 #define BS_RTC_RAR_TPRR      (1U)          /*!< Bit field size in bits for RTC_RAR_TPRR. */
1471
1472 /*! @brief Read current value of the RTC_RAR_TPRR field. */
1473 #define BR_RTC_RAR_TPRR(x)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR))
1474
1475 /*! @brief Format value for bitfield RTC_RAR_TPRR. */
1476 #define BF_RTC_RAR_TPRR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TPRR) & BM_RTC_RAR_TPRR)
1477
1478 /*! @brief Set the TPRR field to a new value. */
1479 #define BW_RTC_RAR_TPRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR) = (v))
1480 /*@}*/
1481
1482 /*!
1483  * @name Register RTC_RAR, field TARR[2] (RW)
1484  *
1485  * After being cleared, this bit is set only by system reset. It is not affected
1486  * by VBAT POR or software reset.
1487  *
1488  * Values:
1489  * - 0 - Reads to the Time Alarm Register are ignored.
1490  * - 1 - Reads to the Time Alarm Register complete as normal.
1491  */
1492 /*@{*/
1493 #define BP_RTC_RAR_TARR      (2U)          /*!< Bit position for RTC_RAR_TARR. */
1494 #define BM_RTC_RAR_TARR      (0x00000004U) /*!< Bit mask for RTC_RAR_TARR. */
1495 #define BS_RTC_RAR_TARR      (1U)          /*!< Bit field size in bits for RTC_RAR_TARR. */
1496
1497 /*! @brief Read current value of the RTC_RAR_TARR field. */
1498 #define BR_RTC_RAR_TARR(x)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR))
1499
1500 /*! @brief Format value for bitfield RTC_RAR_TARR. */
1501 #define BF_RTC_RAR_TARR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TARR) & BM_RTC_RAR_TARR)
1502
1503 /*! @brief Set the TARR field to a new value. */
1504 #define BW_RTC_RAR_TARR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR) = (v))
1505 /*@}*/
1506
1507 /*!
1508  * @name Register RTC_RAR, field TCRR[3] (RW)
1509  *
1510  * After being cleared, this bit is set only by system reset. It is not affected
1511  * by VBAT POR or software reset.
1512  *
1513  * Values:
1514  * - 0 - Reads to the Time Compensation Register are ignored.
1515  * - 1 - Reads to the Time Compensation Register complete as normal.
1516  */
1517 /*@{*/
1518 #define BP_RTC_RAR_TCRR      (3U)          /*!< Bit position for RTC_RAR_TCRR. */
1519 #define BM_RTC_RAR_TCRR      (0x00000008U) /*!< Bit mask for RTC_RAR_TCRR. */
1520 #define BS_RTC_RAR_TCRR      (1U)          /*!< Bit field size in bits for RTC_RAR_TCRR. */
1521
1522 /*! @brief Read current value of the RTC_RAR_TCRR field. */
1523 #define BR_RTC_RAR_TCRR(x)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR))
1524
1525 /*! @brief Format value for bitfield RTC_RAR_TCRR. */
1526 #define BF_RTC_RAR_TCRR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TCRR) & BM_RTC_RAR_TCRR)
1527
1528 /*! @brief Set the TCRR field to a new value. */
1529 #define BW_RTC_RAR_TCRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR) = (v))
1530 /*@}*/
1531
1532 /*!
1533  * @name Register RTC_RAR, field CRR[4] (RW)
1534  *
1535  * After being cleared, this bit is set only by system reset. It is not affected
1536  * by VBAT POR or software reset.
1537  *
1538  * Values:
1539  * - 0 - Reads to the Control Register are ignored.
1540  * - 1 - Reads to the Control Register complete as normal.
1541  */
1542 /*@{*/
1543 #define BP_RTC_RAR_CRR       (4U)          /*!< Bit position for RTC_RAR_CRR. */
1544 #define BM_RTC_RAR_CRR       (0x00000010U) /*!< Bit mask for RTC_RAR_CRR. */
1545 #define BS_RTC_RAR_CRR       (1U)          /*!< Bit field size in bits for RTC_RAR_CRR. */
1546
1547 /*! @brief Read current value of the RTC_RAR_CRR field. */
1548 #define BR_RTC_RAR_CRR(x)    (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR))
1549
1550 /*! @brief Format value for bitfield RTC_RAR_CRR. */
1551 #define BF_RTC_RAR_CRR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_CRR) & BM_RTC_RAR_CRR)
1552
1553 /*! @brief Set the CRR field to a new value. */
1554 #define BW_RTC_RAR_CRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR) = (v))
1555 /*@}*/
1556
1557 /*!
1558  * @name Register RTC_RAR, field SRR[5] (RW)
1559  *
1560  * After being cleared, this bit is set only by system reset. It is not affected
1561  * by VBAT POR or software reset.
1562  *
1563  * Values:
1564  * - 0 - Reads to the Status Register are ignored.
1565  * - 1 - Reads to the Status Register complete as normal.
1566  */
1567 /*@{*/
1568 #define BP_RTC_RAR_SRR       (5U)          /*!< Bit position for RTC_RAR_SRR. */
1569 #define BM_RTC_RAR_SRR       (0x00000020U) /*!< Bit mask for RTC_RAR_SRR. */
1570 #define BS_RTC_RAR_SRR       (1U)          /*!< Bit field size in bits for RTC_RAR_SRR. */
1571
1572 /*! @brief Read current value of the RTC_RAR_SRR field. */
1573 #define BR_RTC_RAR_SRR(x)    (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR))
1574
1575 /*! @brief Format value for bitfield RTC_RAR_SRR. */
1576 #define BF_RTC_RAR_SRR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_SRR) & BM_RTC_RAR_SRR)
1577
1578 /*! @brief Set the SRR field to a new value. */
1579 #define BW_RTC_RAR_SRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR) = (v))
1580 /*@}*/
1581
1582 /*!
1583  * @name Register RTC_RAR, field LRR[6] (RW)
1584  *
1585  * After being cleared, this bit is set only by system reset. It is not affected
1586  * by VBAT POR or software reset.
1587  *
1588  * Values:
1589  * - 0 - Reads to the Lock Register are ignored.
1590  * - 1 - Reads to the Lock Register complete as normal.
1591  */
1592 /*@{*/
1593 #define BP_RTC_RAR_LRR       (6U)          /*!< Bit position for RTC_RAR_LRR. */
1594 #define BM_RTC_RAR_LRR       (0x00000040U) /*!< Bit mask for RTC_RAR_LRR. */
1595 #define BS_RTC_RAR_LRR       (1U)          /*!< Bit field size in bits for RTC_RAR_LRR. */
1596
1597 /*! @brief Read current value of the RTC_RAR_LRR field. */
1598 #define BR_RTC_RAR_LRR(x)    (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR))
1599
1600 /*! @brief Format value for bitfield RTC_RAR_LRR. */
1601 #define BF_RTC_RAR_LRR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_LRR) & BM_RTC_RAR_LRR)
1602
1603 /*! @brief Set the LRR field to a new value. */
1604 #define BW_RTC_RAR_LRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR) = (v))
1605 /*@}*/
1606
1607 /*!
1608  * @name Register RTC_RAR, field IERR[7] (RW)
1609  *
1610  * After being cleared, this bit is set only by system reset. It is not affected
1611  * by VBAT POR or software reset.
1612  *
1613  * Values:
1614  * - 0 - Reads to the Interrupt Enable Register are ignored.
1615  * - 1 - Reads to the Interrupt Enable Register complete as normal.
1616  */
1617 /*@{*/
1618 #define BP_RTC_RAR_IERR      (7U)          /*!< Bit position for RTC_RAR_IERR. */
1619 #define BM_RTC_RAR_IERR      (0x00000080U) /*!< Bit mask for RTC_RAR_IERR. */
1620 #define BS_RTC_RAR_IERR      (1U)          /*!< Bit field size in bits for RTC_RAR_IERR. */
1621
1622 /*! @brief Read current value of the RTC_RAR_IERR field. */
1623 #define BR_RTC_RAR_IERR(x)   (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR))
1624
1625 /*! @brief Format value for bitfield RTC_RAR_IERR. */
1626 #define BF_RTC_RAR_IERR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_IERR) & BM_RTC_RAR_IERR)
1627
1628 /*! @brief Set the IERR field to a new value. */
1629 #define BW_RTC_RAR_IERR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR) = (v))
1630 /*@}*/
1631
1632 /*******************************************************************************
1633  * hw_rtc_t - module struct
1634  ******************************************************************************/
1635 /*!
1636  * @brief All RTC module registers.
1637  */
1638 #pragma pack(1)
1639 typedef struct _hw_rtc
1640 {
1641     __IO hw_rtc_tsr_t TSR;                 /*!< [0x0] RTC Time Seconds Register */
1642     __IO hw_rtc_tpr_t TPR;                 /*!< [0x4] RTC Time Prescaler Register */
1643     __IO hw_rtc_tar_t TAR;                 /*!< [0x8] RTC Time Alarm Register */
1644     __IO hw_rtc_tcr_t TCR;                 /*!< [0xC] RTC Time Compensation Register */
1645     __IO hw_rtc_cr_t CR;                   /*!< [0x10] RTC Control Register */
1646     __IO hw_rtc_sr_t SR;                   /*!< [0x14] RTC Status Register */
1647     __IO hw_rtc_lr_t LR;                   /*!< [0x18] RTC Lock Register */
1648     __IO hw_rtc_ier_t IER;                 /*!< [0x1C] RTC Interrupt Enable Register */
1649     uint8_t _reserved0[2016];
1650     __IO hw_rtc_war_t WAR;                 /*!< [0x800] RTC Write Access Register */
1651     __IO hw_rtc_rar_t RAR;                 /*!< [0x804] RTC Read Access Register */
1652 } hw_rtc_t;
1653 #pragma pack()
1654
1655 /*! @brief Macro to access all RTC registers. */
1656 /*! @param x RTC module instance base address. */
1657 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1658  *     use the '&' operator, like <code>&HW_RTC(RTC_BASE)</code>. */
1659 #define HW_RTC(x)      (*(hw_rtc_t *)(x))
1660
1661 #endif /* __HW_RTC_REGISTERS_H__ */
1662 /* EOF */