2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_SPI_REGISTERS_H__
81 #define __HW_SPI_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Serial Peripheral Interface
91 * Registers defined in this header file:
92 * - HW_SPI_MCR - Module Configuration Register
93 * - HW_SPI_TCR - Transfer Count Register
94 * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
95 * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
96 * - HW_SPI_SR - Status Register
97 * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
98 * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
99 * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
100 * - HW_SPI_POPR - POP RX FIFO Register
101 * - HW_SPI_TXFRn - Transmit FIFO Registers
102 * - HW_SPI_RXFRn - Receive FIFO Registers
104 * - hw_spi_t - Struct containing all module registers.
107 #define HW_SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
108 #define HW_SPI0 (0U) /*!< Instance number for SPI0. */
109 #define HW_SPI1 (1U) /*!< Instance number for SPI1. */
110 #define HW_SPI2 (2U) /*!< Instance number for SPI2. */
112 /*******************************************************************************
113 * HW_SPI_MCR - Module Configuration Register
114 ******************************************************************************/
117 * @brief HW_SPI_MCR - Module Configuration Register (RW)
119 * Reset value: 0x00004001U
121 * Contains bits to configure various attributes associated with the module
122 * operations. The HALT and MDIS bits can be changed at any time, but the effect
123 * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
124 * MCR can be changed, while the module is in the Running state.
126 typedef union _hw_spi_mcr
129 struct _hw_spi_mcr_bitfields
131 uint32_t HALT
: 1; /*!< [0] Halt */
132 uint32_t RESERVED0
: 7; /*!< [7:1] */
133 uint32_t SMPL_PT
: 2; /*!< [9:8] Sample Point */
134 uint32_t CLR_RXF
: 1; /*!< [10] */
135 uint32_t CLR_TXF
: 1; /*!< [11] Clear TX FIFO */
136 uint32_t DIS_RXF
: 1; /*!< [12] Disable Receive FIFO */
137 uint32_t DIS_TXF
: 1; /*!< [13] Disable Transmit FIFO */
138 uint32_t MDIS
: 1; /*!< [14] Module Disable */
139 uint32_t DOZE
: 1; /*!< [15] Doze Enable */
140 uint32_t PCSIS
: 6; /*!< [21:16] Peripheral Chip Select x Inactive
142 uint32_t RESERVED1
: 2; /*!< [23:22] */
143 uint32_t ROOE
: 1; /*!< [24] Receive FIFO Overflow Overwrite Enable */
144 uint32_t PCSSE
: 1; /*!< [25] Peripheral Chip Select Strobe Enable */
145 uint32_t MTFE
: 1; /*!< [26] Modified Timing Format Enable */
146 uint32_t FRZ
: 1; /*!< [27] Freeze */
147 uint32_t DCONF
: 2; /*!< [29:28] SPI Configuration. */
148 uint32_t CONT_SCKE
: 1; /*!< [30] Continuous SCK Enable */
149 uint32_t MSTR
: 1; /*!< [31] Master/Slave Mode Select */
154 * @name Constants and macros for entire SPI_MCR register
157 #define HW_SPI_MCR_ADDR(x) ((x) + 0x0U)
159 #define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
160 #define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
161 #define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
162 #define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v)))
163 #define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
164 #define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
168 * Constants & macros for individual SPI_MCR bitfields
172 * @name Register SPI_MCR, field HALT[0] (RW)
174 * The HALT bit starts and stops frame transfers. See Start and Stop of Module
178 * - 0 - Start transfers.
179 * - 1 - Stop transfers.
182 #define BP_SPI_MCR_HALT (0U) /*!< Bit position for SPI_MCR_HALT. */
183 #define BM_SPI_MCR_HALT (0x00000001U) /*!< Bit mask for SPI_MCR_HALT. */
184 #define BS_SPI_MCR_HALT (1U) /*!< Bit field size in bits for SPI_MCR_HALT. */
186 /*! @brief Read current value of the SPI_MCR_HALT field. */
187 #define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
189 /*! @brief Format value for bitfield SPI_MCR_HALT. */
190 #define BF_SPI_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT)
192 /*! @brief Set the HALT field to a new value. */
193 #define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
197 * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
199 * Controls when the module master samples SIN in Modified Transfer Format. This
200 * field is valid only when CPHA bit in CTARn[CPHA] is 0.
203 * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
204 * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
205 * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
209 #define BP_SPI_MCR_SMPL_PT (8U) /*!< Bit position for SPI_MCR_SMPL_PT. */
210 #define BM_SPI_MCR_SMPL_PT (0x00000300U) /*!< Bit mask for SPI_MCR_SMPL_PT. */
211 #define BS_SPI_MCR_SMPL_PT (2U) /*!< Bit field size in bits for SPI_MCR_SMPL_PT. */
213 /*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
214 #define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
216 /*! @brief Format value for bitfield SPI_MCR_SMPL_PT. */
217 #define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT)
219 /*! @brief Set the SMPL_PT field to a new value. */
220 #define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
224 * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
226 * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
227 * CLR_RXF bit is always read as zero.
230 * - 0 - Do not clear the RX FIFO counter.
231 * - 1 - Clear the RX FIFO counter.
234 #define BP_SPI_MCR_CLR_RXF (10U) /*!< Bit position for SPI_MCR_CLR_RXF. */
235 #define BM_SPI_MCR_CLR_RXF (0x00000400U) /*!< Bit mask for SPI_MCR_CLR_RXF. */
236 #define BS_SPI_MCR_CLR_RXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_RXF. */
238 /*! @brief Format value for bitfield SPI_MCR_CLR_RXF. */
239 #define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF)
241 /*! @brief Set the CLR_RXF field to a new value. */
242 #define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
246 * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
248 * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
249 * CLR_TXF bit is always read as zero.
252 * - 0 - Do not clear the TX FIFO counter.
253 * - 1 - Clear the TX FIFO counter.
256 #define BP_SPI_MCR_CLR_TXF (11U) /*!< Bit position for SPI_MCR_CLR_TXF. */
257 #define BM_SPI_MCR_CLR_TXF (0x00000800U) /*!< Bit mask for SPI_MCR_CLR_TXF. */
258 #define BS_SPI_MCR_CLR_TXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_TXF. */
260 /*! @brief Format value for bitfield SPI_MCR_CLR_TXF. */
261 #define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF)
263 /*! @brief Set the CLR_TXF field to a new value. */
264 #define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
268 * @name Register SPI_MCR, field DIS_RXF[12] (RW)
270 * When the RX FIFO is disabled, the receive part of the module operates as a
271 * simplified double-buffered SPI. This bit can only be written when the MDIS bit
275 * - 0 - RX FIFO is enabled.
276 * - 1 - RX FIFO is disabled.
279 #define BP_SPI_MCR_DIS_RXF (12U) /*!< Bit position for SPI_MCR_DIS_RXF. */
280 #define BM_SPI_MCR_DIS_RXF (0x00001000U) /*!< Bit mask for SPI_MCR_DIS_RXF. */
281 #define BS_SPI_MCR_DIS_RXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_RXF. */
283 /*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
284 #define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
286 /*! @brief Format value for bitfield SPI_MCR_DIS_RXF. */
287 #define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF)
289 /*! @brief Set the DIS_RXF field to a new value. */
290 #define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
294 * @name Register SPI_MCR, field DIS_TXF[13] (RW)
296 * When the TX FIFO is disabled, the transmit part of the module operates as a
297 * simplified double-buffered SPI. This bit can be written only when the MDIS bit
301 * - 0 - TX FIFO is enabled.
302 * - 1 - TX FIFO is disabled.
305 #define BP_SPI_MCR_DIS_TXF (13U) /*!< Bit position for SPI_MCR_DIS_TXF. */
306 #define BM_SPI_MCR_DIS_TXF (0x00002000U) /*!< Bit mask for SPI_MCR_DIS_TXF. */
307 #define BS_SPI_MCR_DIS_TXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_TXF. */
309 /*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
310 #define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
312 /*! @brief Format value for bitfield SPI_MCR_DIS_TXF. */
313 #define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF)
315 /*! @brief Set the DIS_TXF field to a new value. */
316 #define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
320 * @name Register SPI_MCR, field MDIS[14] (RW)
322 * Allows the clock to be stopped to the non-memory mapped logic in the module
323 * effectively putting it in a software-controlled power-saving state. The reset
324 * value of the MDIS bit is parameterized, with a default reset value of 0. When
325 * the module is used in Slave Mode, we recommend leaving this bit 0, because a
326 * slave doesn't have control over master transactions.
329 * - 0 - Enables the module clocks.
330 * - 1 - Allows external logic to disable the module clocks.
333 #define BP_SPI_MCR_MDIS (14U) /*!< Bit position for SPI_MCR_MDIS. */
334 #define BM_SPI_MCR_MDIS (0x00004000U) /*!< Bit mask for SPI_MCR_MDIS. */
335 #define BS_SPI_MCR_MDIS (1U) /*!< Bit field size in bits for SPI_MCR_MDIS. */
337 /*! @brief Read current value of the SPI_MCR_MDIS field. */
338 #define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
340 /*! @brief Format value for bitfield SPI_MCR_MDIS. */
341 #define BF_SPI_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS)
343 /*! @brief Set the MDIS field to a new value. */
344 #define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
348 * @name Register SPI_MCR, field DOZE[15] (RW)
350 * Provides support for an externally controlled Doze mode power-saving
354 * - 0 - Doze mode has no effect on the module.
355 * - 1 - Doze mode disables the module.
358 #define BP_SPI_MCR_DOZE (15U) /*!< Bit position for SPI_MCR_DOZE. */
359 #define BM_SPI_MCR_DOZE (0x00008000U) /*!< Bit mask for SPI_MCR_DOZE. */
360 #define BS_SPI_MCR_DOZE (1U) /*!< Bit field size in bits for SPI_MCR_DOZE. */
362 /*! @brief Read current value of the SPI_MCR_DOZE field. */
363 #define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
365 /*! @brief Format value for bitfield SPI_MCR_DOZE. */
366 #define BF_SPI_MCR_DOZE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE)
368 /*! @brief Set the DOZE field to a new value. */
369 #define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
373 * @name Register SPI_MCR, field PCSIS[21:16] (RW)
375 * Determines the inactive state of PCSx.
378 * - 0 - The inactive state of PCSx is low.
379 * - 1 - The inactive state of PCSx is high.
382 #define BP_SPI_MCR_PCSIS (16U) /*!< Bit position for SPI_MCR_PCSIS. */
383 #define BM_SPI_MCR_PCSIS (0x003F0000U) /*!< Bit mask for SPI_MCR_PCSIS. */
384 #define BS_SPI_MCR_PCSIS (6U) /*!< Bit field size in bits for SPI_MCR_PCSIS. */
386 /*! @brief Read current value of the SPI_MCR_PCSIS field. */
387 #define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
389 /*! @brief Format value for bitfield SPI_MCR_PCSIS. */
390 #define BF_SPI_MCR_PCSIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS)
392 /*! @brief Set the PCSIS field to a new value. */
393 #define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
397 * @name Register SPI_MCR, field ROOE[24] (RW)
399 * In the RX FIFO overflow condition, configures the module to ignore the
400 * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
401 * is received, the data from the transfer, generating the overflow, is ignored
402 * or shifted into the shift register.
405 * - 0 - Incoming data is ignored.
406 * - 1 - Incoming data is shifted into the shift register.
409 #define BP_SPI_MCR_ROOE (24U) /*!< Bit position for SPI_MCR_ROOE. */
410 #define BM_SPI_MCR_ROOE (0x01000000U) /*!< Bit mask for SPI_MCR_ROOE. */
411 #define BS_SPI_MCR_ROOE (1U) /*!< Bit field size in bits for SPI_MCR_ROOE. */
413 /*! @brief Read current value of the SPI_MCR_ROOE field. */
414 #define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
416 /*! @brief Format value for bitfield SPI_MCR_ROOE. */
417 #define BF_SPI_MCR_ROOE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE)
419 /*! @brief Set the ROOE field to a new value. */
420 #define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
424 * @name Register SPI_MCR, field PCSSE[25] (RW)
426 * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
429 * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
430 * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
433 #define BP_SPI_MCR_PCSSE (25U) /*!< Bit position for SPI_MCR_PCSSE. */
434 #define BM_SPI_MCR_PCSSE (0x02000000U) /*!< Bit mask for SPI_MCR_PCSSE. */
435 #define BS_SPI_MCR_PCSSE (1U) /*!< Bit field size in bits for SPI_MCR_PCSSE. */
437 /*! @brief Read current value of the SPI_MCR_PCSSE field. */
438 #define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
440 /*! @brief Format value for bitfield SPI_MCR_PCSSE. */
441 #define BF_SPI_MCR_PCSSE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE)
443 /*! @brief Set the PCSSE field to a new value. */
444 #define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
448 * @name Register SPI_MCR, field MTFE[26] (RW)
450 * Enables a modified transfer format to be used.
453 * - 0 - Modified SPI transfer format disabled.
454 * - 1 - Modified SPI transfer format enabled.
457 #define BP_SPI_MCR_MTFE (26U) /*!< Bit position for SPI_MCR_MTFE. */
458 #define BM_SPI_MCR_MTFE (0x04000000U) /*!< Bit mask for SPI_MCR_MTFE. */
459 #define BS_SPI_MCR_MTFE (1U) /*!< Bit field size in bits for SPI_MCR_MTFE. */
461 /*! @brief Read current value of the SPI_MCR_MTFE field. */
462 #define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
464 /*! @brief Format value for bitfield SPI_MCR_MTFE. */
465 #define BF_SPI_MCR_MTFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE)
467 /*! @brief Set the MTFE field to a new value. */
468 #define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
472 * @name Register SPI_MCR, field FRZ[27] (RW)
474 * Enables transfers to be stopped on the next frame boundary when the device
478 * - 0 - Do not halt serial transfers in Debug mode.
479 * - 1 - Halt serial transfers in Debug mode.
482 #define BP_SPI_MCR_FRZ (27U) /*!< Bit position for SPI_MCR_FRZ. */
483 #define BM_SPI_MCR_FRZ (0x08000000U) /*!< Bit mask for SPI_MCR_FRZ. */
484 #define BS_SPI_MCR_FRZ (1U) /*!< Bit field size in bits for SPI_MCR_FRZ. */
486 /*! @brief Read current value of the SPI_MCR_FRZ field. */
487 #define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
489 /*! @brief Format value for bitfield SPI_MCR_FRZ. */
490 #define BF_SPI_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ)
492 /*! @brief Set the FRZ field to a new value. */
493 #define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
497 * @name Register SPI_MCR, field DCONF[29:28] (RO)
499 * Selects among the different configurations of the module.
508 #define BP_SPI_MCR_DCONF (28U) /*!< Bit position for SPI_MCR_DCONF. */
509 #define BM_SPI_MCR_DCONF (0x30000000U) /*!< Bit mask for SPI_MCR_DCONF. */
510 #define BS_SPI_MCR_DCONF (2U) /*!< Bit field size in bits for SPI_MCR_DCONF. */
512 /*! @brief Read current value of the SPI_MCR_DCONF field. */
513 #define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
517 * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
519 * Enables the Serial Communication Clock (SCK) to run continuously.
522 * - 0 - Continuous SCK disabled.
523 * - 1 - Continuous SCK enabled.
526 #define BP_SPI_MCR_CONT_SCKE (30U) /*!< Bit position for SPI_MCR_CONT_SCKE. */
527 #define BM_SPI_MCR_CONT_SCKE (0x40000000U) /*!< Bit mask for SPI_MCR_CONT_SCKE. */
528 #define BS_SPI_MCR_CONT_SCKE (1U) /*!< Bit field size in bits for SPI_MCR_CONT_SCKE. */
530 /*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
531 #define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
533 /*! @brief Format value for bitfield SPI_MCR_CONT_SCKE. */
534 #define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE)
536 /*! @brief Set the CONT_SCKE field to a new value. */
537 #define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
541 * @name Register SPI_MCR, field MSTR[31] (RW)
543 * Enables either Master mode (if supported) or Slave mode (if supported)
547 * - 0 - Enables Slave mode
548 * - 1 - Enables Master mode
551 #define BP_SPI_MCR_MSTR (31U) /*!< Bit position for SPI_MCR_MSTR. */
552 #define BM_SPI_MCR_MSTR (0x80000000U) /*!< Bit mask for SPI_MCR_MSTR. */
553 #define BS_SPI_MCR_MSTR (1U) /*!< Bit field size in bits for SPI_MCR_MSTR. */
555 /*! @brief Read current value of the SPI_MCR_MSTR field. */
556 #define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
558 /*! @brief Format value for bitfield SPI_MCR_MSTR. */
559 #define BF_SPI_MCR_MSTR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR)
561 /*! @brief Set the MSTR field to a new value. */
562 #define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
565 /*******************************************************************************
566 * HW_SPI_TCR - Transfer Count Register
567 ******************************************************************************/
570 * @brief HW_SPI_TCR - Transfer Count Register (RW)
572 * Reset value: 0x00000000U
574 * TCR contains a counter that indicates the number of SPI transfers made. The
575 * transfer counter is intended to assist in queue management. Do not write the
576 * TCR when the module is in the Running state.
578 typedef union _hw_spi_tcr
581 struct _hw_spi_tcr_bitfields
583 uint32_t RESERVED0
: 16; /*!< [15:0] */
584 uint32_t SPI_TCNT
: 16; /*!< [31:16] SPI Transfer Counter */
589 * @name Constants and macros for entire SPI_TCR register
592 #define HW_SPI_TCR_ADDR(x) ((x) + 0x8U)
594 #define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
595 #define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
596 #define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
597 #define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v)))
598 #define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
599 #define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
603 * Constants & macros for individual SPI_TCR bitfields
607 * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
609 * Counts the number of SPI transfers the module makes. The SPI_TCNT field
610 * increments every time the last bit of an SPI frame is transmitted. A value written
611 * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
612 * the beginning of the frame when the CTCNT field is set in the executing SPI
613 * command. The Transfer Counter wraps around; incrementing the counter past 65535
614 * resets the counter to zero.
617 #define BP_SPI_TCR_SPI_TCNT (16U) /*!< Bit position for SPI_TCR_SPI_TCNT. */
618 #define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) /*!< Bit mask for SPI_TCR_SPI_TCNT. */
619 #define BS_SPI_TCR_SPI_TCNT (16U) /*!< Bit field size in bits for SPI_TCR_SPI_TCNT. */
621 /*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
622 #define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
624 /*! @brief Format value for bitfield SPI_TCR_SPI_TCNT. */
625 #define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT)
627 /*! @brief Set the SPI_TCNT field to a new value. */
628 #define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
631 /*******************************************************************************
632 * HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
633 ******************************************************************************/
636 * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
638 * Reset value: 0x78000000U
640 * CTAR registers are used to define different transfer attributes. Do not write
641 * to the CTAR registers while the module is in the Running state. In Master
642 * mode, the CTAR registers define combinations of transfer attributes such as frame
643 * size, clock phase and polarity, data bit ordering, baud rate, and various
644 * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
645 * slave transfer attributes. When the module is configured as an SPI master, the
646 * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
647 * registers is used. When the module is configured as an SPI bus slave, it uses
648 * the CTAR0 register.
650 typedef union _hw_spi_ctarn
653 struct _hw_spi_ctarn_bitfields
655 uint32_t BR
: 4; /*!< [3:0] Baud Rate Scaler */
656 uint32_t DT
: 4; /*!< [7:4] Delay After Transfer Scaler */
657 uint32_t ASC
: 4; /*!< [11:8] After SCK Delay Scaler */
658 uint32_t CSSCK
: 4; /*!< [15:12] PCS to SCK Delay Scaler */
659 uint32_t PBR
: 2; /*!< [17:16] Baud Rate Prescaler */
660 uint32_t PDT
: 2; /*!< [19:18] Delay after Transfer Prescaler */
661 uint32_t PASC
: 2; /*!< [21:20] After SCK Delay Prescaler */
662 uint32_t PCSSCK
: 2; /*!< [23:22] PCS to SCK Delay Prescaler */
663 uint32_t LSBFE
: 1; /*!< [24] LSB First */
664 uint32_t CPHA
: 1; /*!< [25] Clock Phase */
665 uint32_t CPOL
: 1; /*!< [26] Clock Polarity */
666 uint32_t FMSZ
: 4; /*!< [30:27] Frame Size */
667 uint32_t DBR
: 1; /*!< [31] Double Baud Rate */
672 * @name Constants and macros for entire SPI_CTARn register
675 #define HW_SPI_CTARn_COUNT (2U)
677 #define HW_SPI_CTARn_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
679 #define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
680 #define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
681 #define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
682 #define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v)))
683 #define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
684 #define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
688 * Constants & macros for individual SPI_CTARn bitfields
692 * @name Register SPI_CTARn, field BR[3:0] (RW)
694 * Selects the scaler value for the baud rate. This field is used only in master
695 * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
696 * generate the frequency of the SCK. The baud rate is computed according to the
697 * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
698 * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
699 * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
700 * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
703 #define BP_SPI_CTARn_BR (0U) /*!< Bit position for SPI_CTARn_BR. */
704 #define BM_SPI_CTARn_BR (0x0000000FU) /*!< Bit mask for SPI_CTARn_BR. */
705 #define BS_SPI_CTARn_BR (4U) /*!< Bit field size in bits for SPI_CTARn_BR. */
707 /*! @brief Read current value of the SPI_CTARn_BR field. */
708 #define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
710 /*! @brief Format value for bitfield SPI_CTARn_BR. */
711 #define BF_SPI_CTARn_BR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR)
713 /*! @brief Set the BR field to a new value. */
714 #define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
718 * @name Register SPI_CTARn, field DT[7:4] (RW)
720 * Selects the Delay after Transfer Scaler. This field is used only in master
721 * mode. The Delay after Transfer is the time between the negation of the PCS
722 * signal at the end of a frame and the assertion of PCS at the beginning of the next
723 * frame. In the Continuous Serial Communications Clock operation, the DT value
724 * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
725 * protocol clock period, and it is computed according to the following
726 * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
727 * field description for scaler values.
730 #define BP_SPI_CTARn_DT (4U) /*!< Bit position for SPI_CTARn_DT. */
731 #define BM_SPI_CTARn_DT (0x000000F0U) /*!< Bit mask for SPI_CTARn_DT. */
732 #define BS_SPI_CTARn_DT (4U) /*!< Bit field size in bits for SPI_CTARn_DT. */
734 /*! @brief Read current value of the SPI_CTARn_DT field. */
735 #define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
737 /*! @brief Format value for bitfield SPI_CTARn_DT. */
738 #define BF_SPI_CTARn_DT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT)
740 /*! @brief Set the DT field to a new value. */
741 #define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
745 * @name Register SPI_CTARn, field ASC[11:8] (RW)
747 * Selects the scaler value for the After SCK Delay. This field is used only in
748 * master mode. The After SCK Delay is the delay between the last edge of SCK and
749 * the negation of PCS. The delay is a multiple of the protocol clock period,
750 * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
751 * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
752 * scaler values. Refer After SCK Delay (tASC ) for more details.
755 #define BP_SPI_CTARn_ASC (8U) /*!< Bit position for SPI_CTARn_ASC. */
756 #define BM_SPI_CTARn_ASC (0x00000F00U) /*!< Bit mask for SPI_CTARn_ASC. */
757 #define BS_SPI_CTARn_ASC (4U) /*!< Bit field size in bits for SPI_CTARn_ASC. */
759 /*! @brief Read current value of the SPI_CTARn_ASC field. */
760 #define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
762 /*! @brief Format value for bitfield SPI_CTARn_ASC. */
763 #define BF_SPI_CTARn_ASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC)
765 /*! @brief Set the ASC field to a new value. */
766 #define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
770 * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
772 * Selects the scaler value for the PCS to SCK delay. This field is used only in
773 * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
774 * and the first edge of the SCK. The delay is a multiple of the protocol clock
775 * period, and it is computed according to the following equation: t CSC = (1/fP )
776 * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
777 * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
778 * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
779 * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
783 #define BP_SPI_CTARn_CSSCK (12U) /*!< Bit position for SPI_CTARn_CSSCK. */
784 #define BM_SPI_CTARn_CSSCK (0x0000F000U) /*!< Bit mask for SPI_CTARn_CSSCK. */
785 #define BS_SPI_CTARn_CSSCK (4U) /*!< Bit field size in bits for SPI_CTARn_CSSCK. */
787 /*! @brief Read current value of the SPI_CTARn_CSSCK field. */
788 #define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
790 /*! @brief Format value for bitfield SPI_CTARn_CSSCK. */
791 #define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK)
793 /*! @brief Set the CSSCK field to a new value. */
794 #define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
798 * @name Register SPI_CTARn, field PBR[17:16] (RW)
800 * Selects the prescaler value for the baud rate. This field is used only in
801 * master mode. The baud rate is the frequency of the SCK. The protocol clock is
802 * divided by the prescaler value before the baud rate selection takes place. See
803 * the BR field description for details on how to compute the baud rate.
806 * - 00 - Baud Rate Prescaler value is 2.
807 * - 01 - Baud Rate Prescaler value is 3.
808 * - 10 - Baud Rate Prescaler value is 5.
809 * - 11 - Baud Rate Prescaler value is 7.
812 #define BP_SPI_CTARn_PBR (16U) /*!< Bit position for SPI_CTARn_PBR. */
813 #define BM_SPI_CTARn_PBR (0x00030000U) /*!< Bit mask for SPI_CTARn_PBR. */
814 #define BS_SPI_CTARn_PBR (2U) /*!< Bit field size in bits for SPI_CTARn_PBR. */
816 /*! @brief Read current value of the SPI_CTARn_PBR field. */
817 #define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
819 /*! @brief Format value for bitfield SPI_CTARn_PBR. */
820 #define BF_SPI_CTARn_PBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR)
822 /*! @brief Set the PBR field to a new value. */
823 #define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
827 * @name Register SPI_CTARn, field PDT[19:18] (RW)
829 * Selects the prescaler value for the delay between the negation of the PCS
830 * signal at the end of a frame and the assertion of PCS at the beginning of the
831 * next frame. The PDT field is only used in master mode. See the DT field
832 * description for details on how to compute the Delay after Transfer. Refer Delay after
833 * Transfer (tDT ) for more details.
836 * - 00 - Delay after Transfer Prescaler value is 1.
837 * - 01 - Delay after Transfer Prescaler value is 3.
838 * - 10 - Delay after Transfer Prescaler value is 5.
839 * - 11 - Delay after Transfer Prescaler value is 7.
842 #define BP_SPI_CTARn_PDT (18U) /*!< Bit position for SPI_CTARn_PDT. */
843 #define BM_SPI_CTARn_PDT (0x000C0000U) /*!< Bit mask for SPI_CTARn_PDT. */
844 #define BS_SPI_CTARn_PDT (2U) /*!< Bit field size in bits for SPI_CTARn_PDT. */
846 /*! @brief Read current value of the SPI_CTARn_PDT field. */
847 #define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
849 /*! @brief Format value for bitfield SPI_CTARn_PDT. */
850 #define BF_SPI_CTARn_PDT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT)
852 /*! @brief Set the PDT field to a new value. */
853 #define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
857 * @name Register SPI_CTARn, field PASC[21:20] (RW)
859 * Selects the prescaler value for the delay between the last edge of SCK and
860 * the negation of PCS. See the ASC field description for information on how to
861 * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
864 * - 00 - Delay after Transfer Prescaler value is 1.
865 * - 01 - Delay after Transfer Prescaler value is 3.
866 * - 10 - Delay after Transfer Prescaler value is 5.
867 * - 11 - Delay after Transfer Prescaler value is 7.
870 #define BP_SPI_CTARn_PASC (20U) /*!< Bit position for SPI_CTARn_PASC. */
871 #define BM_SPI_CTARn_PASC (0x00300000U) /*!< Bit mask for SPI_CTARn_PASC. */
872 #define BS_SPI_CTARn_PASC (2U) /*!< Bit field size in bits for SPI_CTARn_PASC. */
874 /*! @brief Read current value of the SPI_CTARn_PASC field. */
875 #define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
877 /*! @brief Format value for bitfield SPI_CTARn_PASC. */
878 #define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC)
880 /*! @brief Set the PASC field to a new value. */
881 #define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
885 * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
887 * Selects the prescaler value for the delay between assertion of PCS and the
888 * first edge of the SCK. See the CSSCK field description for information on how to
889 * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
892 * - 00 - PCS to SCK Prescaler value is 1.
893 * - 01 - PCS to SCK Prescaler value is 3.
894 * - 10 - PCS to SCK Prescaler value is 5.
895 * - 11 - PCS to SCK Prescaler value is 7.
898 #define BP_SPI_CTARn_PCSSCK (22U) /*!< Bit position for SPI_CTARn_PCSSCK. */
899 #define BM_SPI_CTARn_PCSSCK (0x00C00000U) /*!< Bit mask for SPI_CTARn_PCSSCK. */
900 #define BS_SPI_CTARn_PCSSCK (2U) /*!< Bit field size in bits for SPI_CTARn_PCSSCK. */
902 /*! @brief Read current value of the SPI_CTARn_PCSSCK field. */
903 #define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
905 /*! @brief Format value for bitfield SPI_CTARn_PCSSCK. */
906 #define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK)
908 /*! @brief Set the PCSSCK field to a new value. */
909 #define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
913 * @name Register SPI_CTARn, field LSBFE[24] (RW)
915 * Specifies whether the LSB or MSB of the frame is transferred first.
918 * - 0 - Data is transferred MSB first.
919 * - 1 - Data is transferred LSB first.
922 #define BP_SPI_CTARn_LSBFE (24U) /*!< Bit position for SPI_CTARn_LSBFE. */
923 #define BM_SPI_CTARn_LSBFE (0x01000000U) /*!< Bit mask for SPI_CTARn_LSBFE. */
924 #define BS_SPI_CTARn_LSBFE (1U) /*!< Bit field size in bits for SPI_CTARn_LSBFE. */
926 /*! @brief Read current value of the SPI_CTARn_LSBFE field. */
927 #define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
929 /*! @brief Format value for bitfield SPI_CTARn_LSBFE. */
930 #define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE)
932 /*! @brief Set the LSBFE field to a new value. */
933 #define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
937 * @name Register SPI_CTARn, field CPHA[25] (RW)
939 * Selects which edge of SCK causes data to change and which edge causes data to
940 * be captured. This bit is used in both master and slave mode. For successful
941 * communication between serial devices, the devices must have identical clock
942 * phase settings. In Continuous SCK mode, the bit value is ignored and the
943 * transfers are done as if the CPHA bit is set to 1.
946 * - 0 - Data is captured on the leading edge of SCK and changed on the
948 * - 1 - Data is changed on the leading edge of SCK and captured on the
952 #define BP_SPI_CTARn_CPHA (25U) /*!< Bit position for SPI_CTARn_CPHA. */
953 #define BM_SPI_CTARn_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_CPHA. */
954 #define BS_SPI_CTARn_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_CPHA. */
956 /*! @brief Read current value of the SPI_CTARn_CPHA field. */
957 #define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
959 /*! @brief Format value for bitfield SPI_CTARn_CPHA. */
960 #define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA)
962 /*! @brief Set the CPHA field to a new value. */
963 #define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
967 * @name Register SPI_CTARn, field CPOL[26] (RW)
969 * Selects the inactive state of the Serial Communications Clock (SCK). This bit
970 * is used in both master and slave mode. For successful communication between
971 * serial devices, the devices must have identical clock polarities. When the
972 * Continuous Selection Format is selected, switching between clock polarities
973 * without stopping the module can cause errors in the transfer due to the peripheral
974 * device interpreting the switch of clock polarity as a valid clock edge. In case
975 * of continous sck mode, when the module goes in low power mode(disabled),
976 * inactive state of sck is not guaranted.
979 * - 0 - The inactive state value of SCK is low.
980 * - 1 - The inactive state value of SCK is high.
983 #define BP_SPI_CTARn_CPOL (26U) /*!< Bit position for SPI_CTARn_CPOL. */
984 #define BM_SPI_CTARn_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_CPOL. */
985 #define BS_SPI_CTARn_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_CPOL. */
987 /*! @brief Read current value of the SPI_CTARn_CPOL field. */
988 #define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
990 /*! @brief Format value for bitfield SPI_CTARn_CPOL. */
991 #define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL)
993 /*! @brief Set the CPOL field to a new value. */
994 #define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
998 * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
1000 * The number of bits transferred per frame is equal to the FMSZ value plus 1.
1001 * Regardless of the transmission mode, the minimum valid frame size value is 4.
1004 #define BP_SPI_CTARn_FMSZ (27U) /*!< Bit position for SPI_CTARn_FMSZ. */
1005 #define BM_SPI_CTARn_FMSZ (0x78000000U) /*!< Bit mask for SPI_CTARn_FMSZ. */
1006 #define BS_SPI_CTARn_FMSZ (4U) /*!< Bit field size in bits for SPI_CTARn_FMSZ. */
1008 /*! @brief Read current value of the SPI_CTARn_FMSZ field. */
1009 #define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
1011 /*! @brief Format value for bitfield SPI_CTARn_FMSZ. */
1012 #define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ)
1014 /*! @brief Set the FMSZ field to a new value. */
1015 #define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
1019 * @name Register SPI_CTARn, field DBR[31] (RW)
1021 * Doubles the effective baud rate of the Serial Communications Clock (SCK).
1022 * This field is used only in master mode. It effectively halves the Baud Rate
1023 * division ratio, supporting faster frequencies, and odd division ratios for the
1024 * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
1025 * Serial Communications Clock (SCK) depends on the value in the Baud Rate
1026 * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
1027 * description for details on how to compute the baud rate. SPI SCK Duty Cycle
1028 * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
1029 * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
1032 * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
1033 * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
1037 #define BP_SPI_CTARn_DBR (31U) /*!< Bit position for SPI_CTARn_DBR. */
1038 #define BM_SPI_CTARn_DBR (0x80000000U) /*!< Bit mask for SPI_CTARn_DBR. */
1039 #define BS_SPI_CTARn_DBR (1U) /*!< Bit field size in bits for SPI_CTARn_DBR. */
1041 /*! @brief Read current value of the SPI_CTARn_DBR field. */
1042 #define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
1044 /*! @brief Format value for bitfield SPI_CTARn_DBR. */
1045 #define BF_SPI_CTARn_DBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR)
1047 /*! @brief Set the DBR field to a new value. */
1048 #define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
1050 /*******************************************************************************
1051 * HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
1052 ******************************************************************************/
1055 * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
1057 * Reset value: 0x78000000U
1059 * When the module is configured as an SPI bus slave, the CTAR0 register is used.
1061 typedef union _hw_spi_ctarn_slave
1064 struct _hw_spi_ctarn_slave_bitfields
1066 uint32_t RESERVED0
: 25; /*!< [24:0] */
1067 uint32_t CPHA
: 1; /*!< [25] Clock Phase */
1068 uint32_t CPOL
: 1; /*!< [26] Clock Polarity */
1069 uint32_t FMSZ
: 5; /*!< [31:27] Frame Size */
1071 } hw_spi_ctarn_slave_t
;
1074 * @name Constants and macros for entire SPI_CTARn_SLAVE register
1077 #define HW_SPI_CTARn_SLAVE_COUNT (1U)
1079 #define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
1081 #define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
1082 #define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
1083 #define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
1084 #define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v)))
1085 #define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
1086 #define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
1090 * Constants & macros for individual SPI_CTARn_SLAVE bitfields
1094 * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
1096 * Selects which edge of SCK causes data to change and which edge causes data to
1097 * be captured. This bit is used in both master and slave mode. For successful
1098 * communication between serial devices, the devices must have identical clock
1099 * phase settings. In Continuous SCK mode, the bit value is ignored and the
1100 * transfers are done as if the CPHA bit is set to 1.
1103 * - 0 - Data is captured on the leading edge of SCK and changed on the
1105 * - 1 - Data is changed on the leading edge of SCK and captured on the
1109 #define BP_SPI_CTARn_SLAVE_CPHA (25U) /*!< Bit position for SPI_CTARn_SLAVE_CPHA. */
1110 #define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPHA. */
1111 #define BS_SPI_CTARn_SLAVE_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. */
1113 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. */
1114 #define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
1116 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. */
1117 #define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA)
1119 /*! @brief Set the CPHA field to a new value. */
1120 #define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
1124 * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
1126 * Selects the inactive state of the Serial Communications Clock (SCK). In case
1127 * of continous sck mode, when the module goes in low power mode(disabled),
1128 * inactive state of sck is not guaranted.
1131 * - 0 - The inactive state value of SCK is low.
1132 * - 1 - The inactive state value of SCK is high.
1135 #define BP_SPI_CTARn_SLAVE_CPOL (26U) /*!< Bit position for SPI_CTARn_SLAVE_CPOL. */
1136 #define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPOL. */
1137 #define BS_SPI_CTARn_SLAVE_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. */
1139 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. */
1140 #define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
1142 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. */
1143 #define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL)
1145 /*! @brief Set the CPOL field to a new value. */
1146 #define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
1150 * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
1152 * The number of bits transfered per frame is equal to the FMSZ field value plus
1153 * 1. Note that the minimum valid value of frame size is 4.
1156 #define BP_SPI_CTARn_SLAVE_FMSZ (27U) /*!< Bit position for SPI_CTARn_SLAVE_FMSZ. */
1157 #define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /*!< Bit mask for SPI_CTARn_SLAVE_FMSZ. */
1158 #define BS_SPI_CTARn_SLAVE_FMSZ (5U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. */
1160 /*! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. */
1161 #define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
1163 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. */
1164 #define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ)
1166 /*! @brief Set the FMSZ field to a new value. */
1167 #define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
1170 /*******************************************************************************
1171 * HW_SPI_SR - Status Register
1172 ******************************************************************************/
1175 * @brief HW_SPI_SR - Status Register (RW)
1177 * Reset value: 0x02000000U
1179 * SR contains status and flag bits. The bits reflect the status of the module
1180 * and indicate the occurrence of events that can generate interrupt or DMA
1181 * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
1182 * to a flag bit has no effect. This register may not be writable in Module
1183 * Disable mode due to the use of power saving mechanisms.
1185 typedef union _hw_spi_sr
1188 struct _hw_spi_sr_bitfields
1190 uint32_t POPNXTPTR
: 4; /*!< [3:0] Pop Next Pointer */
1191 uint32_t RXCTR
: 4; /*!< [7:4] RX FIFO Counter */
1192 uint32_t TXNXTPTR
: 4; /*!< [11:8] Transmit Next Pointer */
1193 uint32_t TXCTR
: 4; /*!< [15:12] TX FIFO Counter */
1194 uint32_t RESERVED0
: 1; /*!< [16] */
1195 uint32_t RFDF
: 1; /*!< [17] Receive FIFO Drain Flag */
1196 uint32_t RESERVED1
: 1; /*!< [18] */
1197 uint32_t RFOF
: 1; /*!< [19] Receive FIFO Overflow Flag */
1198 uint32_t RESERVED2
: 5; /*!< [24:20] */
1199 uint32_t TFFF
: 1; /*!< [25] Transmit FIFO Fill Flag */
1200 uint32_t RESERVED3
: 1; /*!< [26] */
1201 uint32_t TFUF
: 1; /*!< [27] Transmit FIFO Underflow Flag */
1202 uint32_t EOQF
: 1; /*!< [28] End of Queue Flag */
1203 uint32_t RESERVED4
: 1; /*!< [29] */
1204 uint32_t TXRXS
: 1; /*!< [30] TX and RX Status */
1205 uint32_t TCF
: 1; /*!< [31] Transfer Complete Flag */
1210 * @name Constants and macros for entire SPI_SR register
1213 #define HW_SPI_SR_ADDR(x) ((x) + 0x2CU)
1215 #define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
1216 #define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
1217 #define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
1218 #define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v)))
1219 #define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
1220 #define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
1224 * Constants & macros for individual SPI_SR bitfields
1228 * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
1230 * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
1231 * The POPNXTPTR is updated when the POPR is read.
1234 #define BP_SPI_SR_POPNXTPTR (0U) /*!< Bit position for SPI_SR_POPNXTPTR. */
1235 #define BM_SPI_SR_POPNXTPTR (0x0000000FU) /*!< Bit mask for SPI_SR_POPNXTPTR. */
1236 #define BS_SPI_SR_POPNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_POPNXTPTR. */
1238 /*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
1239 #define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
1243 * @name Register SPI_SR, field RXCTR[7:4] (RO)
1245 * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
1246 * every time the POPR is read. The RXCTR is incremented every time data is
1247 * transferred from the shift register to the RX FIFO.
1250 #define BP_SPI_SR_RXCTR (4U) /*!< Bit position for SPI_SR_RXCTR. */
1251 #define BM_SPI_SR_RXCTR (0x000000F0U) /*!< Bit mask for SPI_SR_RXCTR. */
1252 #define BS_SPI_SR_RXCTR (4U) /*!< Bit field size in bits for SPI_SR_RXCTR. */
1254 /*! @brief Read current value of the SPI_SR_RXCTR field. */
1255 #define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
1259 * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
1261 * Indicates which TX FIFO entry is transmitted during the next transfer. The
1262 * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
1263 * the shift register.
1266 #define BP_SPI_SR_TXNXTPTR (8U) /*!< Bit position for SPI_SR_TXNXTPTR. */
1267 #define BM_SPI_SR_TXNXTPTR (0x00000F00U) /*!< Bit mask for SPI_SR_TXNXTPTR. */
1268 #define BS_SPI_SR_TXNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_TXNXTPTR. */
1270 /*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
1271 #define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
1275 * @name Register SPI_SR, field TXCTR[15:12] (RO)
1277 * Indicates the number of valid entries in the TX FIFO. The TXCTR is
1278 * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
1279 * command is executed and the SPI data is transferred to the shift register.
1282 #define BP_SPI_SR_TXCTR (12U) /*!< Bit position for SPI_SR_TXCTR. */
1283 #define BM_SPI_SR_TXCTR (0x0000F000U) /*!< Bit mask for SPI_SR_TXCTR. */
1284 #define BS_SPI_SR_TXCTR (4U) /*!< Bit field size in bits for SPI_SR_TXCTR. */
1286 /*! @brief Read current value of the SPI_SR_TXCTR field. */
1287 #define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
1291 * @name Register SPI_SR, field RFDF[17] (W1C)
1293 * Provides a method for the module to request that entries be removed from the
1294 * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
1295 * cleared by writing 1 to it or by acknowledgement from the DMA controller when
1296 * the RX FIFO is empty.
1299 * - 0 - RX FIFO is empty.
1300 * - 1 - RX FIFO is not empty.
1303 #define BP_SPI_SR_RFDF (17U) /*!< Bit position for SPI_SR_RFDF. */
1304 #define BM_SPI_SR_RFDF (0x00020000U) /*!< Bit mask for SPI_SR_RFDF. */
1305 #define BS_SPI_SR_RFDF (1U) /*!< Bit field size in bits for SPI_SR_RFDF. */
1307 /*! @brief Read current value of the SPI_SR_RFDF field. */
1308 #define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
1310 /*! @brief Format value for bitfield SPI_SR_RFDF. */
1311 #define BF_SPI_SR_RFDF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF)
1313 /*! @brief Set the RFDF field to a new value. */
1314 #define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
1318 * @name Register SPI_SR, field RFOF[19] (W1C)
1320 * Indicates an overflow condition in the RX FIFO. The field is set when the RX
1321 * FIFO and shift register are full and a transfer is initiated. The bit remains
1322 * set until it is cleared by writing a 1 to it.
1325 * - 0 - No Rx FIFO overflow.
1326 * - 1 - Rx FIFO overflow has occurred.
1329 #define BP_SPI_SR_RFOF (19U) /*!< Bit position for SPI_SR_RFOF. */
1330 #define BM_SPI_SR_RFOF (0x00080000U) /*!< Bit mask for SPI_SR_RFOF. */
1331 #define BS_SPI_SR_RFOF (1U) /*!< Bit field size in bits for SPI_SR_RFOF. */
1333 /*! @brief Read current value of the SPI_SR_RFOF field. */
1334 #define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
1336 /*! @brief Format value for bitfield SPI_SR_RFOF. */
1337 #define BF_SPI_SR_RFOF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF)
1339 /*! @brief Set the RFOF field to a new value. */
1340 #define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
1344 * @name Register SPI_SR, field TFFF[25] (W1C)
1346 * Provides a method for the module to request more entries to be added to the
1347 * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
1348 * cleared by writing 1 to it or by acknowledgement from the DMA controller to
1349 * the TX FIFO full request.
1352 * - 0 - TX FIFO is full.
1353 * - 1 - TX FIFO is not full.
1356 #define BP_SPI_SR_TFFF (25U) /*!< Bit position for SPI_SR_TFFF. */
1357 #define BM_SPI_SR_TFFF (0x02000000U) /*!< Bit mask for SPI_SR_TFFF. */
1358 #define BS_SPI_SR_TFFF (1U) /*!< Bit field size in bits for SPI_SR_TFFF. */
1360 /*! @brief Read current value of the SPI_SR_TFFF field. */
1361 #define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
1363 /*! @brief Format value for bitfield SPI_SR_TFFF. */
1364 #define BF_SPI_SR_TFFF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF)
1366 /*! @brief Set the TFFF field to a new value. */
1367 #define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
1371 * @name Register SPI_SR, field TFUF[27] (W1C)
1373 * Indicates an underflow condition in the TX FIFO. The transmit underflow
1374 * condition is detected only for SPI blocks operating in Slave mode and SPI
1375 * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
1376 * is empty and an external SPI master initiates a transfer. The TFUF bit remains
1377 * set until cleared by writing 1 to it.
1380 * - 0 - No TX FIFO underflow.
1381 * - 1 - TX FIFO underflow has occurred.
1384 #define BP_SPI_SR_TFUF (27U) /*!< Bit position for SPI_SR_TFUF. */
1385 #define BM_SPI_SR_TFUF (0x08000000U) /*!< Bit mask for SPI_SR_TFUF. */
1386 #define BS_SPI_SR_TFUF (1U) /*!< Bit field size in bits for SPI_SR_TFUF. */
1388 /*! @brief Read current value of the SPI_SR_TFUF field. */
1389 #define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
1391 /*! @brief Format value for bitfield SPI_SR_TFUF. */
1392 #define BF_SPI_SR_TFUF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF)
1394 /*! @brief Set the TFUF field to a new value. */
1395 #define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
1399 * @name Register SPI_SR, field EOQF[28] (W1C)
1401 * Indicates that the last entry in a queue has been transmitted when the module
1402 * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
1403 * set in the command halfword and the end of the transfer is reached. The EOQF
1404 * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
1405 * the TXRXS bit is automatically cleared.
1408 * - 0 - EOQ is not set in the executing command.
1409 * - 1 - EOQ is set in the executing SPI command.
1412 #define BP_SPI_SR_EOQF (28U) /*!< Bit position for SPI_SR_EOQF. */
1413 #define BM_SPI_SR_EOQF (0x10000000U) /*!< Bit mask for SPI_SR_EOQF. */
1414 #define BS_SPI_SR_EOQF (1U) /*!< Bit field size in bits for SPI_SR_EOQF. */
1416 /*! @brief Read current value of the SPI_SR_EOQF field. */
1417 #define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
1419 /*! @brief Format value for bitfield SPI_SR_EOQF. */
1420 #define BF_SPI_SR_EOQF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF)
1422 /*! @brief Set the EOQF field to a new value. */
1423 #define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
1427 * @name Register SPI_SR, field TXRXS[30] (W1C)
1429 * Reflects the run status of the module.
1432 * - 0 - Transmit and receive operations are disabled (The module is in Stopped
1434 * - 1 - Transmit and receive operations are enabled (The module is in Running
1438 #define BP_SPI_SR_TXRXS (30U) /*!< Bit position for SPI_SR_TXRXS. */
1439 #define BM_SPI_SR_TXRXS (0x40000000U) /*!< Bit mask for SPI_SR_TXRXS. */
1440 #define BS_SPI_SR_TXRXS (1U) /*!< Bit field size in bits for SPI_SR_TXRXS. */
1442 /*! @brief Read current value of the SPI_SR_TXRXS field. */
1443 #define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
1445 /*! @brief Format value for bitfield SPI_SR_TXRXS. */
1446 #define BF_SPI_SR_TXRXS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS)
1448 /*! @brief Set the TXRXS field to a new value. */
1449 #define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
1453 * @name Register SPI_SR, field TCF[31] (W1C)
1455 * Indicates that all bits in a frame have been shifted out. TCF remains set
1456 * until it is cleared by writing a 1 to it.
1459 * - 0 - Transfer not complete.
1460 * - 1 - Transfer complete.
1463 #define BP_SPI_SR_TCF (31U) /*!< Bit position for SPI_SR_TCF. */
1464 #define BM_SPI_SR_TCF (0x80000000U) /*!< Bit mask for SPI_SR_TCF. */
1465 #define BS_SPI_SR_TCF (1U) /*!< Bit field size in bits for SPI_SR_TCF. */
1467 /*! @brief Read current value of the SPI_SR_TCF field. */
1468 #define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
1470 /*! @brief Format value for bitfield SPI_SR_TCF. */
1471 #define BF_SPI_SR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF)
1473 /*! @brief Set the TCF field to a new value. */
1474 #define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
1477 /*******************************************************************************
1478 * HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
1479 ******************************************************************************/
1482 * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
1484 * Reset value: 0x00000000U
1486 * RSER controls DMA and interrupt requests. Do not write to the RSER while the
1487 * module is in the Running state.
1489 typedef union _hw_spi_rser
1492 struct _hw_spi_rser_bitfields
1494 uint32_t RESERVED0
: 16; /*!< [15:0] */
1495 uint32_t RFDF_DIRS
: 1; /*!< [16] Receive FIFO Drain DMA or Interrupt
1497 uint32_t RFDF_RE
: 1; /*!< [17] Receive FIFO Drain Request Enable */
1498 uint32_t RESERVED1
: 1; /*!< [18] */
1499 uint32_t RFOF_RE
: 1; /*!< [19] Receive FIFO Overflow Request Enable
1501 uint32_t RESERVED2
: 4; /*!< [23:20] */
1502 uint32_t TFFF_DIRS
: 1; /*!< [24] Transmit FIFO Fill DMA or Interrupt
1504 uint32_t TFFF_RE
: 1; /*!< [25] Transmit FIFO Fill Request Enable */
1505 uint32_t RESERVED3
: 1; /*!< [26] */
1506 uint32_t TFUF_RE
: 1; /*!< [27] Transmit FIFO Underflow Request
1508 uint32_t EOQF_RE
: 1; /*!< [28] Finished Request Enable */
1509 uint32_t RESERVED4
: 2; /*!< [30:29] */
1510 uint32_t TCF_RE
: 1; /*!< [31] Transmission Complete Request Enable */
1515 * @name Constants and macros for entire SPI_RSER register
1518 #define HW_SPI_RSER_ADDR(x) ((x) + 0x30U)
1520 #define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
1521 #define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
1522 #define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
1523 #define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v)))
1524 #define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
1525 #define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
1529 * Constants & macros for individual SPI_RSER bitfields
1533 * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
1535 * Selects between generating a DMA request or an interrupt request. When the
1536 * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
1537 * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
1540 * - 0 - Interrupt request.
1541 * - 1 - DMA request.
1544 #define BP_SPI_RSER_RFDF_DIRS (16U) /*!< Bit position for SPI_RSER_RFDF_DIRS. */
1545 #define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /*!< Bit mask for SPI_RSER_RFDF_DIRS. */
1546 #define BS_SPI_RSER_RFDF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_DIRS. */
1548 /*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
1549 #define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
1551 /*! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. */
1552 #define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS)
1554 /*! @brief Set the RFDF_DIRS field to a new value. */
1555 #define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
1559 * @name Register SPI_RSER, field RFDF_RE[17] (RW)
1561 * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
1562 * selects between generating an interrupt request or a DMA request.
1565 * - 0 - RFDF interrupt or DMA requests are disabled.
1566 * - 1 - RFDF interrupt or DMA requests are enabled.
1569 #define BP_SPI_RSER_RFDF_RE (17U) /*!< Bit position for SPI_RSER_RFDF_RE. */
1570 #define BM_SPI_RSER_RFDF_RE (0x00020000U) /*!< Bit mask for SPI_RSER_RFDF_RE. */
1571 #define BS_SPI_RSER_RFDF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_RE. */
1573 /*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
1574 #define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
1576 /*! @brief Format value for bitfield SPI_RSER_RFDF_RE. */
1577 #define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE)
1579 /*! @brief Set the RFDF_RE field to a new value. */
1580 #define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
1584 * @name Register SPI_RSER, field RFOF_RE[19] (RW)
1586 * Enables the RFOF flag in the SR to generate an interrupt request.
1589 * - 0 - RFOF interrupt requests are disabled.
1590 * - 1 - RFOF interrupt requests are enabled.
1593 #define BP_SPI_RSER_RFOF_RE (19U) /*!< Bit position for SPI_RSER_RFOF_RE. */
1594 #define BM_SPI_RSER_RFOF_RE (0x00080000U) /*!< Bit mask for SPI_RSER_RFOF_RE. */
1595 #define BS_SPI_RSER_RFOF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFOF_RE. */
1597 /*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
1598 #define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
1600 /*! @brief Format value for bitfield SPI_RSER_RFOF_RE. */
1601 #define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE)
1603 /*! @brief Set the RFOF_RE field to a new value. */
1604 #define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
1608 * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
1610 * Selects between generating a DMA request or an interrupt request. When
1611 * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
1612 * interrupt request or a DMA request.
1615 * - 0 - TFFF flag generates interrupt requests.
1616 * - 1 - TFFF flag generates DMA requests.
1619 #define BP_SPI_RSER_TFFF_DIRS (24U) /*!< Bit position for SPI_RSER_TFFF_DIRS. */
1620 #define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /*!< Bit mask for SPI_RSER_TFFF_DIRS. */
1621 #define BS_SPI_RSER_TFFF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_DIRS. */
1623 /*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
1624 #define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
1626 /*! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. */
1627 #define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS)
1629 /*! @brief Set the TFFF_DIRS field to a new value. */
1630 #define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
1634 * @name Register SPI_RSER, field TFFF_RE[25] (RW)
1636 * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
1637 * selects between generating an interrupt request or a DMA request.
1640 * - 0 - TFFF interrupts or DMA requests are disabled.
1641 * - 1 - TFFF interrupts or DMA requests are enabled.
1644 #define BP_SPI_RSER_TFFF_RE (25U) /*!< Bit position for SPI_RSER_TFFF_RE. */
1645 #define BM_SPI_RSER_TFFF_RE (0x02000000U) /*!< Bit mask for SPI_RSER_TFFF_RE. */
1646 #define BS_SPI_RSER_TFFF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_RE. */
1648 /*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
1649 #define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
1651 /*! @brief Format value for bitfield SPI_RSER_TFFF_RE. */
1652 #define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE)
1654 /*! @brief Set the TFFF_RE field to a new value. */
1655 #define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
1659 * @name Register SPI_RSER, field TFUF_RE[27] (RW)
1661 * Enables the TFUF flag in the SR to generate an interrupt request.
1664 * - 0 - TFUF interrupt requests are disabled.
1665 * - 1 - TFUF interrupt requests are enabled.
1668 #define BP_SPI_RSER_TFUF_RE (27U) /*!< Bit position for SPI_RSER_TFUF_RE. */
1669 #define BM_SPI_RSER_TFUF_RE (0x08000000U) /*!< Bit mask for SPI_RSER_TFUF_RE. */
1670 #define BS_SPI_RSER_TFUF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFUF_RE. */
1672 /*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
1673 #define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
1675 /*! @brief Format value for bitfield SPI_RSER_TFUF_RE. */
1676 #define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE)
1678 /*! @brief Set the TFUF_RE field to a new value. */
1679 #define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
1683 * @name Register SPI_RSER, field EOQF_RE[28] (RW)
1685 * Enables the EOQF flag in the SR to generate an interrupt request.
1688 * - 0 - EOQF interrupt requests are disabled.
1689 * - 1 - EOQF interrupt requests are enabled.
1692 #define BP_SPI_RSER_EOQF_RE (28U) /*!< Bit position for SPI_RSER_EOQF_RE. */
1693 #define BM_SPI_RSER_EOQF_RE (0x10000000U) /*!< Bit mask for SPI_RSER_EOQF_RE. */
1694 #define BS_SPI_RSER_EOQF_RE (1U) /*!< Bit field size in bits for SPI_RSER_EOQF_RE. */
1696 /*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
1697 #define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
1699 /*! @brief Format value for bitfield SPI_RSER_EOQF_RE. */
1700 #define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE)
1702 /*! @brief Set the EOQF_RE field to a new value. */
1703 #define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
1707 * @name Register SPI_RSER, field TCF_RE[31] (RW)
1709 * Enables TCF flag in the SR to generate an interrupt request.
1712 * - 0 - TCF interrupt requests are disabled.
1713 * - 1 - TCF interrupt requests are enabled.
1716 #define BP_SPI_RSER_TCF_RE (31U) /*!< Bit position for SPI_RSER_TCF_RE. */
1717 #define BM_SPI_RSER_TCF_RE (0x80000000U) /*!< Bit mask for SPI_RSER_TCF_RE. */
1718 #define BS_SPI_RSER_TCF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TCF_RE. */
1720 /*! @brief Read current value of the SPI_RSER_TCF_RE field. */
1721 #define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
1723 /*! @brief Format value for bitfield SPI_RSER_TCF_RE. */
1724 #define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE)
1726 /*! @brief Set the TCF_RE field to a new value. */
1727 #define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
1730 /*******************************************************************************
1731 * HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
1732 ******************************************************************************/
1735 * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
1737 * Reset value: 0x00000000U
1739 * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
1740 * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
1741 * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
1742 * can be used as data, supporting up to 32-bit frame operation. A read access
1743 * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
1744 * writing to this register does not update the FIFO. Therefore, any reads performed
1745 * while the module is disabled return the last PUSHR write performed while the
1746 * module was still enabled.
1748 typedef union _hw_spi_pushr
1751 struct _hw_spi_pushr_bitfields
1753 uint32_t TXDATA
: 16; /*!< [15:0] Transmit Data */
1754 uint32_t PCS
: 6; /*!< [21:16] */
1755 uint32_t RESERVED0
: 4; /*!< [25:22] */
1756 uint32_t CTCNT
: 1; /*!< [26] Clear Transfer Counter */
1757 uint32_t EOQ
: 1; /*!< [27] End Of Queue */
1758 uint32_t CTAS
: 3; /*!< [30:28] Clock and Transfer Attributes Select
1760 uint32_t CONT
: 1; /*!< [31] Continuous Peripheral Chip Select Enable
1766 * @name Constants and macros for entire SPI_PUSHR register
1769 #define HW_SPI_PUSHR_ADDR(x) ((x) + 0x34U)
1771 #define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
1772 #define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
1773 #define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
1774 #define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v)))
1775 #define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
1776 #define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
1780 * Constants & macros for individual SPI_PUSHR bitfields
1784 * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
1786 * Holds SPI data to be transferred according to the associated SPI command.
1789 #define BP_SPI_PUSHR_TXDATA (0U) /*!< Bit position for SPI_PUSHR_TXDATA. */
1790 #define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_PUSHR_TXDATA. */
1791 #define BS_SPI_PUSHR_TXDATA (16U) /*!< Bit field size in bits for SPI_PUSHR_TXDATA. */
1793 /*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
1794 #define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
1796 /*! @brief Format value for bitfield SPI_PUSHR_TXDATA. */
1797 #define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA)
1799 /*! @brief Set the TXDATA field to a new value. */
1800 #define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
1804 * @name Register SPI_PUSHR, field PCS[21:16] (RW)
1806 * Select which PCS signals are to be asserted for the transfer. Refer to the
1807 * chip configuration details for the number of PCS signals used in this MCU.
1810 * - 0 - Negate the PCS[x] signal.
1811 * - 1 - Assert the PCS[x] signal.
1814 #define BP_SPI_PUSHR_PCS (16U) /*!< Bit position for SPI_PUSHR_PCS. */
1815 #define BM_SPI_PUSHR_PCS (0x003F0000U) /*!< Bit mask for SPI_PUSHR_PCS. */
1816 #define BS_SPI_PUSHR_PCS (6U) /*!< Bit field size in bits for SPI_PUSHR_PCS. */
1818 /*! @brief Read current value of the SPI_PUSHR_PCS field. */
1819 #define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
1821 /*! @brief Format value for bitfield SPI_PUSHR_PCS. */
1822 #define BF_SPI_PUSHR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS)
1824 /*! @brief Set the PCS field to a new value. */
1825 #define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
1829 * @name Register SPI_PUSHR, field CTCNT[26] (RW)
1831 * Clears the TCNT field in the TCR register. The TCNT field is cleared before
1832 * the module starts transmitting the current SPI frame.
1835 * - 0 - Do not clear the TCR[TCNT] field.
1836 * - 1 - Clear the TCR[TCNT] field.
1839 #define BP_SPI_PUSHR_CTCNT (26U) /*!< Bit position for SPI_PUSHR_CTCNT. */
1840 #define BM_SPI_PUSHR_CTCNT (0x04000000U) /*!< Bit mask for SPI_PUSHR_CTCNT. */
1841 #define BS_SPI_PUSHR_CTCNT (1U) /*!< Bit field size in bits for SPI_PUSHR_CTCNT. */
1843 /*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
1844 #define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
1846 /*! @brief Format value for bitfield SPI_PUSHR_CTCNT. */
1847 #define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT)
1849 /*! @brief Set the CTCNT field to a new value. */
1850 #define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
1854 * @name Register SPI_PUSHR, field EOQ[27] (RW)
1856 * Host software uses this bit to signal to the module that the current SPI
1857 * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
1861 * - 0 - The SPI data is not the last data to transfer.
1862 * - 1 - The SPI data is the last data to transfer.
1865 #define BP_SPI_PUSHR_EOQ (27U) /*!< Bit position for SPI_PUSHR_EOQ. */
1866 #define BM_SPI_PUSHR_EOQ (0x08000000U) /*!< Bit mask for SPI_PUSHR_EOQ. */
1867 #define BS_SPI_PUSHR_EOQ (1U) /*!< Bit field size in bits for SPI_PUSHR_EOQ. */
1869 /*! @brief Read current value of the SPI_PUSHR_EOQ field. */
1870 #define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
1872 /*! @brief Format value for bitfield SPI_PUSHR_EOQ. */
1873 #define BF_SPI_PUSHR_EOQ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ)
1875 /*! @brief Set the EOQ field to a new value. */
1876 #define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
1880 * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
1882 * Selects which CTAR to use in master mode to specify the transfer attributes
1883 * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
1884 * configuration details to determine how many CTARs this device has. You should
1885 * not program a value in this field for a register that is not present.
1898 #define BP_SPI_PUSHR_CTAS (28U) /*!< Bit position for SPI_PUSHR_CTAS. */
1899 #define BM_SPI_PUSHR_CTAS (0x70000000U) /*!< Bit mask for SPI_PUSHR_CTAS. */
1900 #define BS_SPI_PUSHR_CTAS (3U) /*!< Bit field size in bits for SPI_PUSHR_CTAS. */
1902 /*! @brief Read current value of the SPI_PUSHR_CTAS field. */
1903 #define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
1905 /*! @brief Format value for bitfield SPI_PUSHR_CTAS. */
1906 #define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS)
1908 /*! @brief Set the CTAS field to a new value. */
1909 #define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
1913 * @name Register SPI_PUSHR, field CONT[31] (RW)
1915 * Selects a continuous selection format. The bit is used in SPI Master mode.
1916 * The bit enables the selected PCS signals to remain asserted between transfers.
1919 * - 0 - Return PCSn signals to their inactive state between transfers.
1920 * - 1 - Keep PCSn signals asserted between transfers.
1923 #define BP_SPI_PUSHR_CONT (31U) /*!< Bit position for SPI_PUSHR_CONT. */
1924 #define BM_SPI_PUSHR_CONT (0x80000000U) /*!< Bit mask for SPI_PUSHR_CONT. */
1925 #define BS_SPI_PUSHR_CONT (1U) /*!< Bit field size in bits for SPI_PUSHR_CONT. */
1927 /*! @brief Read current value of the SPI_PUSHR_CONT field. */
1928 #define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
1930 /*! @brief Format value for bitfield SPI_PUSHR_CONT. */
1931 #define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT)
1933 /*! @brief Set the CONT field to a new value. */
1934 #define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
1936 /*******************************************************************************
1937 * HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
1938 ******************************************************************************/
1941 * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
1943 * Reset value: 0x00000000U
1945 * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
1946 * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
1947 * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
1948 * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
1949 * SPI Frame operation.
1951 typedef union _hw_spi_pushr_slave
1954 struct _hw_spi_pushr_slave_bitfields
1956 uint32_t TXDATA
: 32; /*!< [31:0] Transmit Data */
1958 } hw_spi_pushr_slave_t
;
1961 * @name Constants and macros for entire SPI_PUSHR_SLAVE register
1964 #define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U)
1966 #define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
1967 #define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
1968 #define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
1969 #define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v)))
1970 #define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
1971 #define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
1975 * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
1979 * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
1981 * Holds SPI data to be transferred according to the associated SPI command.
1984 #define BP_SPI_PUSHR_SLAVE_TXDATA (0U) /*!< Bit position for SPI_PUSHR_SLAVE_TXDATA. */
1985 #define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. */
1986 #define BS_SPI_PUSHR_SLAVE_TXDATA (32U) /*!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. */
1988 /*! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. */
1989 #define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
1991 /*! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. */
1992 #define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA)
1994 /*! @brief Set the TXDATA field to a new value. */
1995 #define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
1998 /*******************************************************************************
1999 * HW_SPI_POPR - POP RX FIFO Register
2000 ******************************************************************************/
2003 * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
2005 * Reset value: 0x00000000U
2007 * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
2008 * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
2009 * this register will generate a Transfer Error.
2011 typedef union _hw_spi_popr
2014 struct _hw_spi_popr_bitfields
2016 uint32_t RXDATA
: 32; /*!< [31:0] Received Data */
2021 * @name Constants and macros for entire SPI_POPR register
2024 #define HW_SPI_POPR_ADDR(x) ((x) + 0x38U)
2026 #define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
2027 #define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
2031 * Constants & macros for individual SPI_POPR bitfields
2035 * @name Register SPI_POPR, field RXDATA[31:0] (RO)
2037 * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
2041 #define BP_SPI_POPR_RXDATA (0U) /*!< Bit position for SPI_POPR_RXDATA. */
2042 #define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_POPR_RXDATA. */
2043 #define BS_SPI_POPR_RXDATA (32U) /*!< Bit field size in bits for SPI_POPR_RXDATA. */
2045 /*! @brief Read current value of the SPI_POPR_RXDATA field. */
2046 #define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
2049 /*******************************************************************************
2050 * HW_SPI_TXFRn - Transmit FIFO Registers
2051 ******************************************************************************/
2054 * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
2056 * Reset value: 0x00000000U
2058 * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
2059 * Each register is an entry in the TX FIFO. The registers are read-only and
2060 * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
2063 typedef union _hw_spi_txfrn
2066 struct _hw_spi_txfrn_bitfields
2068 uint32_t TXDATA
: 16; /*!< [15:0] Transmit Data */
2069 uint32_t TXCMD_TXDATA
: 16; /*!< [31:16] Transmit Command or Transmit
2075 * @name Constants and macros for entire SPI_TXFRn register
2078 #define HW_SPI_TXFRn_COUNT (4U)
2080 #define HW_SPI_TXFRn_ADDR(x, n) ((x) + 0x3CU + (0x4U * (n)))
2082 #define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
2083 #define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
2087 * Constants & macros for individual SPI_TXFRn bitfields
2091 * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
2093 * Contains the SPI data to be shifted out.
2096 #define BP_SPI_TXFRn_TXDATA (0U) /*!< Bit position for SPI_TXFRn_TXDATA. */
2097 #define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_TXFRn_TXDATA. */
2098 #define BS_SPI_TXFRn_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXDATA. */
2100 /*! @brief Read current value of the SPI_TXFRn_TXDATA field. */
2101 #define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
2105 * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
2107 * In Master mode the TXCMD field contains the command that sets the transfer
2108 * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
2109 * the SPI data to be shifted out.
2112 #define BP_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit position for SPI_TXFRn_TXCMD_TXDATA. */
2113 #define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /*!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. */
2114 #define BS_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. */
2116 /*! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. */
2117 #define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
2120 /*******************************************************************************
2121 * HW_SPI_RXFRn - Receive FIFO Registers
2122 ******************************************************************************/
2125 * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
2127 * Reset value: 0x00000000U
2129 * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
2130 * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
2131 * RXFRx registers does not alter the state of the RX FIFO.
2133 typedef union _hw_spi_rxfrn
2136 struct _hw_spi_rxfrn_bitfields
2138 uint32_t RXDATA
: 32; /*!< [31:0] Receive Data */
2143 * @name Constants and macros for entire SPI_RXFRn register
2146 #define HW_SPI_RXFRn_COUNT (4U)
2148 #define HW_SPI_RXFRn_ADDR(x, n) ((x) + 0x7CU + (0x4U * (n)))
2150 #define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
2151 #define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
2155 * Constants & macros for individual SPI_RXFRn bitfields
2159 * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
2161 * Contains the received SPI data.
2164 #define BP_SPI_RXFRn_RXDATA (0U) /*!< Bit position for SPI_RXFRn_RXDATA. */
2165 #define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_RXFRn_RXDATA. */
2166 #define BS_SPI_RXFRn_RXDATA (32U) /*!< Bit field size in bits for SPI_RXFRn_RXDATA. */
2168 /*! @brief Read current value of the SPI_RXFRn_RXDATA field. */
2169 #define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
2173 ** Start of section using anonymous unions
2176 #if defined(__ARMCC_VERSION)
2179 #elif defined(__CWCC__)
2181 #pragma cpp_extensions on
2182 #elif defined(__GNUC__)
2183 /* anonymous unions are enabled by default */
2184 #elif defined(__IAR_SYSTEMS_ICC__)
2185 #pragma language=extended
2187 #error Not supported compiler type
2190 /*******************************************************************************
2191 * hw_spi_t - module struct
2192 ******************************************************************************/
2194 * @brief All SPI module registers.
2197 typedef struct _hw_spi
2199 __IO hw_spi_mcr_t MCR
; /*!< [0x0] Module Configuration Register */
2200 uint8_t _reserved0
[4];
2201 __IO hw_spi_tcr_t TCR
; /*!< [0x8] Transfer Count Register */
2203 __IO hw_spi_ctarn_t CTARn
[2]; /*!< [0xC] Clock and Transfer Attributes Register (In Master Mode) */
2204 __IO hw_spi_ctarn_slave_t CTARn_SLAVE
[1]; /*!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) */
2206 uint8_t _reserved1
[24];
2207 __IO hw_spi_sr_t SR
; /*!< [0x2C] Status Register */
2208 __IO hw_spi_rser_t RSER
; /*!< [0x30] DMA/Interrupt Request Select and Enable Register */
2210 __IO hw_spi_pushr_t PUSHR
; /*!< [0x34] PUSH TX FIFO Register In Master Mode */
2211 __IO hw_spi_pushr_slave_t PUSHR_SLAVE
; /*!< [0x34] PUSH TX FIFO Register In Slave Mode */
2213 __I hw_spi_popr_t POPR
; /*!< [0x38] POP RX FIFO Register */
2214 __I hw_spi_txfrn_t TXFRn
[4]; /*!< [0x3C] Transmit FIFO Registers */
2215 uint8_t _reserved2
[48];
2216 __I hw_spi_rxfrn_t RXFRn
[4]; /*!< [0x7C] Receive FIFO Registers */
2220 /*! @brief Macro to access all SPI registers. */
2221 /*! @param x SPI module instance base address. */
2222 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
2223 * use the '&' operator, like <code>&HW_SPI(SPI0_BASE)</code>. */
2224 #define HW_SPI(x) (*(hw_spi_t *)(x))
2227 ** End of section using anonymous unions
2230 #if defined(__ARMCC_VERSION)
2232 #elif defined(__CWCC__)
2234 #elif defined(__GNUC__)
2235 /* leave anonymous unions enabled */
2236 #elif defined(__IAR_SYSTEMS_ICC__)
2237 #pragma language=default
2239 #error Not supported compiler type
2242 #endif /* __HW_SPI_REGISTERS_H__ */