tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/can_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16
  17 #include "can_api.h"
  18
  19 #include "cmsis.h"
  20 #include "mbed_error.h"
  21
  22 #include <math.h>
  23 #include <string.h>
  24
  25 /* Handy defines */
  26 #define MSG_OBJ_MAX      32
  27 #define DLC_MAX          8
  28
  29 #define ID_STD_MASK      0x07FF
  30 #define ID_EXT_MASK      0x1FFFFFFF
  31 #define DLC_MASK         0x0F
  32
  33 #define CANIFn_ARB2_DIR         (1UL << 13)
  34 #define CANIFn_ARB2_XTD         (1UL << 14)
  35 #define CANIFn_ARB2_MSGVAL      (1UL << 15)
  36 #define CANIFn_MSK2_MXTD        (1UL << 15)
  37 #define CANIFn_MSK2_MDIR        (1UL << 14)
  38 #define CANIFn_MCTRL_EOB        (1UL << 7)
  39 #define CANIFn_MCTRL_TXRQST     (1UL << 8)
  40 #define CANIFn_MCTRL_RMTEN      (1UL << 9)
  41 #define CANIFn_MCTRL_RXIE       (1UL << 10)
  42 #define CANIFn_MCTRL_TXIE       (1UL << 11)
  43 #define CANIFn_MCTRL_UMASK      (1UL << 12)
  44 #define CANIFn_MCTRL_INTPND     (1UL << 13)
  45 #define CANIFn_MCTRL_MSGLST     (1UL << 14)
  46 #define CANIFn_MCTRL_NEWDAT     (1UL << 15)
  47 #define CANIFn_CMDMSK_DATA_B    (1UL << 0)
  48 #define CANIFn_CMDMSK_DATA_A    (1UL << 1)
  49 #define CANIFn_CMDMSK_TXRQST    (1UL << 2)
  50 #define CANIFn_CMDMSK_NEWDAT    (1UL << 2)
  51 #define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
  52 #define CANIFn_CMDMSK_CTRL      (1UL << 4)
  53 #define CANIFn_CMDMSK_ARB       (1UL << 5)
  54 #define CANIFn_CMDMSK_MASK      (1UL << 6)
  55 #define CANIFn_CMDMSK_WR        (1UL << 7)
  56 #define CANIFn_CMDMSK_RD        (0UL << 7)
  57 #define CANIFn_CMDREQ_BUSY      (1UL << 15)
  58
  59 static uint32_t can_irq_id = 0;
  60 static can_irq_handler irq_handler;
  61
  62 static inline void can_disable(can_t *obj) {
  63     LPC_C_CAN0->CANCNTL |= 0x1;
  64 }
  65
  66 static inline void can_enable(can_t *obj) {
  67     if (LPC_C_CAN0->CANCNTL & 0x1) {
  68         LPC_C_CAN0->CANCNTL &= ~(0x1);
  69     }
  70 }
  71
  72 int can_mode(can_t *obj, CanMode mode) {
  73     return 0; // not implemented
  74 }
  75
  76 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
  77     uint16_t i;
  78
  79     // Find first free message object
  80     if (handle == 0) {
  81         uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
  82
  83         // Find first free messagebox
  84         for (i = 0; i < 32; i++) {
  85             if ((msgval & (1 << i)) == 0) {
  86                 handle = i+1;
  87                 break;
  88             }
  89         }
  90     }
  91
  92     if (handle > 0 && handle < 32) {
  93         if (format == CANExtended) {
  94             // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
  95             LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
  96             LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
  97             LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
  98             LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
  99         } else {
 100             // Mark message valid, Direction = TX, Set Identifier and mask everything
 101             LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
 102             LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
 103         }
 104
 105         // Use mask, single message object and set DLC
 106         LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | CANIFn_MCTRL_RXIE | (DLC_MAX & 0xF);
 107
 108         // Transfer all fields to message object
 109         LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
 110
 111         // Start Transfer to given message number
 112         LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
 113
 114         // Wait until transfer to message ram complete - TODO: maybe not block??
 115         while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
 116     }
 117
 118     return handle;
 119 }
 120
 121 static inline void can_irq() {
 122     irq_handler(can_irq_id, IRQ_RX);
 123 }
 124
 125 // Register CAN object's irq handler
 126 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
 127     irq_handler = handler;
 128     can_irq_id = id;
 129 }
 130
 131 // Unregister CAN object's irq handler
 132 void can_irq_free(can_t *obj) {
 133     LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
 134     can_irq_id = 0;
 135     NVIC_DisableIRQ(C_CAN0_IRQn);
 136 }
 137
 138 // Clear or set a irq
 139 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
 140     // Put CAN in Reset Mode and enable interrupt
 141     can_disable(obj);
 142     if (enable == 0) {
 143         LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2);
 144     } else {
 145         LPC_C_CAN0->CANCNTL |= 1UL << 1 | 1UL << 2;
 146     }
 147     // Take it out of reset...
 148     can_enable(obj);
 149
 150     // Enable NVIC if at least 1 interrupt is active
 151     NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
 152     NVIC_EnableIRQ(C_CAN0_IRQn);
 153 }
 154
 155 // This table has the sampling points as close to 75% as possible. The first
 156 // value is TSEG1, the second TSEG2.
 157 static const int timing_pts[23][2] = {
 158     {0x0, 0x0},      // 2,  50%
 159     {0x1, 0x0},      // 3,  67%
 160     {0x2, 0x0},      // 4,  75%
 161     {0x3, 0x0},      // 5,  80%
 162     {0x3, 0x1},      // 6,  67%
 163     {0x4, 0x1},      // 7,  71%
 164     {0x5, 0x1},      // 8,  75%
 165     {0x6, 0x1},      // 9,  78%
 166     {0x6, 0x2},      // 10, 70%
 167     {0x7, 0x2},      // 11, 73%
 168     {0x8, 0x2},      // 12, 75%
 169     {0x9, 0x2},      // 13, 77%
 170     {0x9, 0x3},      // 14, 71%
 171     {0xA, 0x3},      // 15, 73%
 172     {0xB, 0x3},      // 16, 75%
 173     {0xC, 0x3},      // 17, 76%
 174     {0xD, 0x3},      // 18, 78%
 175     {0xD, 0x4},      // 19, 74%
 176     {0xE, 0x4},      // 20, 75%
 177     {0xF, 0x4},      // 21, 76%
 178     {0xF, 0x5},      // 22, 73%
 179     {0xF, 0x6},      // 23, 70%
 180     {0xF, 0x7},      // 24, 67%
 181 };
 182
 183 static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
 184     uint32_t    btr;
 185     uint32_t    clkdiv = 1;
 186     uint16_t    brp = 0;
 187     uint32_t    calcbit;
 188     uint32_t    bitwidth;
 189     int         hit = 0;
 190     int         bits = 0;
 191
 192     bitwidth = sclk / cclk;
 193
 194     brp = bitwidth / 0x18;
 195     while ((!hit) && (brp < bitwidth / 4)) {
 196         brp++;
 197         for (bits = 22; bits > 0; bits--) {
 198             calcbit = (bits + 3) * (brp + 1);
 199             if (calcbit == bitwidth) {
 200                 hit = 1;
 201                 break;
 202             }
 203         }
 204     }
 205
 206     clkdiv = clkdiv - 1;
 207
 208     if (hit) {
 209         btr = (timing_pts[bits][1] & 0x7) << 12
 210             | (timing_pts[bits][0] & 0xf) << 8
 211             | (psjw & 0x3) << 6
 212             | (brp & 0x3F);
 213         btr = btr | (clkdiv << 16);
 214     } else {
 215         btr = 0;
 216     }
 217
 218     return btr;
 219 }
 220
 221
 222 int can_config_rxmsgobj(can_t *obj) {
 223     uint16_t i = 0;
 224
 225     // Make sure the interface is available
 226     while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
 227
 228     // Mark message valid, Direction = RX, Don't care about anything else
 229     LPC_C_CAN0->CANIF1_ARB1 = 0;
 230     LPC_C_CAN0->CANIF1_ARB2 = 0;
 231     LPC_C_CAN0->CANIF1_MCTRL = 0;
 232
 233     for ( i = 0; i < MSG_OBJ_MAX; i++ ) {
 234         // Transfer arb and control fields to message object
 235         LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST;
 236
 237         // Start Transfer to given message number
 238         LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
 239
 240         // Wait until transfer to message ram complete - TODO: maybe not block??
 241         while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
 242     }
 243
 244     // Accept all messages
 245     can_filter(obj, 0, 0, CANStandard, 1);
 246
 247     return 1;
 248 }
 249
 250
 251 void can_init(can_t *obj, PinName rd, PinName td) {
 252     // Enable power and clock
 253     LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
 254     LPC_SYSCON->PRESETCTRL1    |= (1UL << 7);
 255     LPC_SYSCON->PRESETCTRL1    &= ~(1UL << 7);
 256
 257     // Enable Initialization mode
 258     if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
 259         LPC_C_CAN0->CANCNTL |= (1UL << 0);
 260     }
 261
 262     LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
 263     LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
 264
 265     can_frequency(obj, 100000);
 266
 267     // Resume operation
 268     LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
 269     while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
 270
 271     // Initialize RX message object
 272     can_config_rxmsgobj(obj);
 273 }
 274
 275 void can_free(can_t *obj) {
 276     LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
 277     LPC_SYSCON->PRESETCTRL1    &= ~(1UL << 7);
 278 }
 279
 280 int can_frequency(can_t *obj, int f) {
 281     int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
 282     int clkdiv = (btr >> 16) & 0x0F;
 283     btr = btr & 0xFFFF;
 284
 285     if (btr > 0) {
 286         // Set the bit clock
 287         LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
 288         LPC_C_CAN0->CANCLKDIV = clkdiv;
 289         LPC_C_CAN0->CANBT = btr;
 290         LPC_C_CAN0->CANBRPE = 0x0000;
 291         LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
 292         return 1;
 293     }
 294     return 0;
 295 }
 296
 297 int can_write(can_t *obj, CAN_Message msg, int cc) {
 298     uint16_t msgnum = 0;
 299
 300     // Make sure controller is enabled
 301     can_enable(obj);
 302
 303     // Make sure the interface is available
 304     while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
 305
 306     // Set the direction bit based on the message type
 307     uint32_t direction = 0;
 308     if (msg.type == CANData) {
 309         direction = CANIFn_ARB2_DIR;
 310     }
 311
 312     if (msg.format == CANExtended)    {
 313         // Mark message valid, Extended Frame, Set Identifier and mask everything
 314         LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
 315         LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
 316         LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
 317         LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
 318     } else {
 319         // Mark message valid, Set Identifier and mask everything
 320         LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
 321         LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
 322     }
 323
 324     // Use mask, request transmission, single message object and set DLC
 325     LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
 326
 327     LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
 328     LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
 329     LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
 330     LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
 331
 332     // Transfer all fields to message object
 333     LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
 334
 335     // Start Transfer to given message number
 336     LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
 337
 338     // Wait until transfer to message ram complete - TODO: maybe not block??
 339     while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
 340
 341     // Wait until TXOK is set, then clear it - TODO: maybe not block
 342     //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
 343     LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
 344
 345     return 1;
 346 }
 347
 348 int can_read(can_t *obj, CAN_Message *msg, int handle) {
 349     uint16_t i;
 350
 351     // Make sure controller is enabled
 352     can_enable(obj);
 353
 354     // Find first message object with new data
 355     if (handle == 0) {
 356         uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
 357         // Find first free messagebox
 358         for (i = 0; i < 32; i++) {
 359             if (newdata & (1 << i)) {
 360                 handle = i+1;
 361                 break;
 362             }
 363         }
 364     }
 365
 366     if (handle > 0 && handle < 32) {
 367         // Wait until message interface is free
 368         while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
 369
 370         // Transfer all fields to message object
 371         LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
 372
 373         // Start Transfer from given message number
 374         LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
 375
 376         // Wait until transfer to message ram complete
 377         while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
 378
 379         if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
 380             msg->format = CANExtended;
 381             msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
 382             msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
 383         } else {
 384             msg->format = CANStandard;
 385             msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
 386         }
 387
 388        if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
 389             msg->type   = CANRemote;
 390         }
 391         else {
 392             msg->type   = CANData;
 393         }
 394
 395         msg->len        = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
 396         msg->data[0]    = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
 397         msg->data[1]    = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
 398         msg->data[2]    = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
 399         msg->data[3]    = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
 400         msg->data[4]    = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
 401         msg->data[5]    = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
 402         msg->data[6]    = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
 403         msg->data[7]    = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
 404
 405         LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
 406         return 1;
 407     }
 408     return 0;
 409 }
 410
 411 void can_reset(can_t *obj) {
 412     LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
 413     LPC_C_CAN0->CANSTAT = 0;
 414     can_config_rxmsgobj(obj);
 415 }
 416
 417 unsigned char can_rderror(can_t *obj) {
 418     return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
 419 }
 420
 421 unsigned char can_tderror(can_t *obj) {
 422     return (LPC_C_CAN0->CANEC & 0xFF);
 423 }
 424
 425 void can_monitor(can_t *obj, int silent) {
 426     if (silent) {
 427         LPC_C_CAN0->CANCNTL |= (1UL << 7);
 428         LPC_C_CAN0->CANTEST |= (1UL << 3);
 429     } else {
 430         LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
 431         LPC_C_CAN0->CANTEST &= ~(1UL << 3);
 432     }
 433
 434     if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
 435         LPC_C_CAN0->CANCNTL |= (1UL << 0);
 436     }
 437 }