tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include <stddef.h>
  17 #include "us_ticker_api.h"
  18 #include "PeripheralNames.h"
  19
  20 static int us_ticker_inited = 0;
  21 int MRT_Clock_MHz;
  22 unsigned int ticker_fullcount_us;
  23 unsigned long int ticker_expired_count_us = 0;
  24
  25 #define US_TICKER_TIMER_IRQn     MRT_IRQn
  26
  27 void us_ticker_init(void) {
  28
  29     if (us_ticker_inited)
  30         return;
  31
  32     us_ticker_inited = 1;
  33
  34     // Calculate MRT clock value (MRT has no prescaler)
  35     MRT_Clock_MHz = (SystemCoreClock / 1000000);
  36     // Calculate fullcounter value in us (MRT has 31 bits and clock is 30MHz)
  37     ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz;
  38
  39     // Enable the MRT clock
  40     LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
  41
  42     // Clear peripheral reset the MRT
  43     LPC_SYSCON->PRESETCTRL |= (1 << 7);
  44
  45     // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
  46     LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
  47     // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt
  48     LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0);
  49
  50     // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
  51     LPC_MRT->INTVAL1 = 0x80000000UL;
  52     // Disable ch1 interrupt, Mode 0 is Repeat Interrupt
  53     LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0);
  54
  55     // Set MRT interrupt vector
  56     NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
  57     NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
  58 }
  59
  60 //TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc)
  61 uint32_t us_ticker_read() {
  62
  63     if (!us_ticker_inited)
  64         us_ticker_init();
  65
  66     // Generate ticker value
  67     // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
  68     // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz
  69     return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us;
  70 }
  71
  72 //TIMER1 is used for Timestamped interrupts (Ticker(), Timeout())
  73 void us_ticker_set_interrupt(timestamp_t timestamp) {
  74
  75     // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
  76     // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
  77     // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz.
  78     //       The calculated counter interval until the next timestamp will be truncated and an
  79     //       'early' interrupt will be generated in case the max required count interval exceeds
  80     //       the available 31 bits space. However, the mbed us_ticker interrupt handler will
  81     //       check current time against the next scheduled timestamp and simply re-issue the
  82     //       same interrupt again when needed. The calculated counter interval will now be smaller.
  83     LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL);
  84
  85     // Enable interrupt
  86     LPC_MRT->CTRL1 |= 1;
  87 }
  88
  89 //Disable Timestamped interrupts triggered by TIMER1
  90 void us_ticker_disable_interrupt() {
  91     //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
  92     LPC_MRT->CTRL1 &= ~1;
  93 }
  94
  95 void us_ticker_clear_interrupt() {
  96
  97     //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
  98     if (LPC_MRT->STAT1 & 1)
  99         LPC_MRT->STAT1 = 1;
 100
 101     //Timer0 for us counter (31 bits downcounter @ SystemCoreClock)
 102     if (LPC_MRT->STAT0 & 1) {
 103         LPC_MRT->STAT0 = 1;
 104           ticker_expired_count_us += ticker_fullcount_us;
 105     }
 106 }