tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    15-December-2014
   7   * @brief   Header file of NAND HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F1xx_HAL_NAND_H
  40 #define __STM32F1xx_HAL_NAND_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f1xx_ll_fsmc.h"
  48
  49 /** @addtogroup STM32F1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  54 /** @addtogroup NAND
  55   * @{
  56   */
  57
  58 /** @addtogroup NAND_Private_Constants
  59   * @{
  60   */
  61
  62 #define NAND_DEVICE1               FSMC_BANK2
  63 #define NAND_DEVICE2               FSMC_BANK3
  64 #define NAND_WRITE_TIMEOUT         ((uint32_t)1000)
  65
  66 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
  67 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
  68
  69 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
  70 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
  71 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
  72 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
  73
  74 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
  75 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
  76 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
  77 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
  78 #define NAND_CMD_READID            ((uint8_t)0x90)
  79 #define NAND_CMD_STATUS            ((uint8_t)0x70)
  80 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
  81 #define NAND_CMD_RESET             ((uint8_t)0xFF)
  82
  83 /* NAND memory status */
  84 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
  85 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
  86 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
  87 #define NAND_BUSY                  ((uint32_t)0x00000000)
  88 #define NAND_ERROR                 ((uint32_t)0x00000001)
  89 #define NAND_READY                 ((uint32_t)0x00000040)
  90
  91 /**
  92   * @}
  93   */
  94
  95 /** @addtogroup NAND_Private_Macros
  96   * @{
  97   */
  98
  99 /**
 100   * @brief  NAND memory address computation.
 101   * @param  __ADDRESS__: NAND memory address.
 102   * @param  __HANDLE__ : NAND handle.
 103   * @retval NAND Raw address value
 104   */
 105 #define __ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
 106                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
 107
 108 /**
 109   * @brief  NAND memory address cycling.
 110   * @param  __ADDRESS__: NAND memory address.
 111   * @retval NAND address cycling value.
 112   */
 113 #define __ADDR_1st_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 114 #define __ADDR_2nd_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 115 #define __ADDR_3rd_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 116 #define __ADDR_4th_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 117
 118 /**
 119   * @}
 120   */
 121
 122 /* Exported typedef ----------------------------------------------------------*/
 123 /* Exported types ------------------------------------------------------------*/
 124 /** @defgroup NAND_Exported_Types NAND Exported Types
 125   * @{
 126   */
 127
 128 /**
 129   * @brief  HAL NAND State structures definition
 130   */
 131 typedef enum
 132 {
 133   HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
 134   HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
 135   HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
 136   HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
 137 }HAL_NAND_StateTypeDef;
 138
 139 /**
 140   * @brief  NAND Memory electronic signature Structure definition
 141   */
 142 typedef struct
 143 {
 144   /*<! NAND memory electronic signature maker and device IDs */
 145
 146   uint8_t Maker_Id;
 147
 148   uint8_t Device_Id;
 149
 150   uint8_t Third_Id;
 151
 152   uint8_t Fourth_Id;
 153 }NAND_IDTypeDef;
 154
 155 /**
 156   * @brief  NAND Memory address Structure definition
 157   */
 158 typedef struct
 159 {
 160   uint16_t Page;   /*!< NAND memory Page address  */
 161
 162   uint16_t Zone;   /*!< NAND memory Zone address  */
 163
 164   uint16_t Block;  /*!< NAND memory Block address */
 165
 166 }NAND_AddressTypeDef;
 167
 168 /**
 169   * @brief  NAND Memory info Structure definition
 170   */
 171 typedef struct
 172 {
 173   uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
 174
 175   uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
 176
 177   uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
 178
 179   uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
 180
 181   uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
 182 }NAND_InfoTypeDef;
 183
 184 /**
 185   * @brief  NAND handle Structure definition
 186   */
 187 typedef struct
 188 {
 189   FSMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
 190
 191   FSMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
 192
 193   HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
 194
 195   __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
 196
 197   NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
 198 }NAND_HandleTypeDef;
 199
 200 /**
 201   * @}
 202   */
 203
 204 /* Exported constants --------------------------------------------------------*/
 205 /* Exported macro ------------------------------------------------------------*/
 206 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 207  * @{
 208  */
 209
 210 /** @brief Reset NAND handle state
 211   * @param  __HANDLE__: specifies the NAND handle.
 212   * @retval None
 213   */
 214 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 215
 216 /**
 217   * @}
 218   */
 219
 220 /* Exported functions --------------------------------------------------------*/
 221 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 222   * @{
 223   */
 224
 225 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 226   * @{
 227   */
 228
 229 /* Initialization/de-initialization functions  ********************************/
 230 HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 231 HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 232 void                HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 233 void                HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 234 void                HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 235 void                HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 236
 237 /**
 238   * @}
 239   */
 240
 241 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 242   * @{
 243   */
 244
 245 /* IO operation functions  ****************************************************/
 246 HAL_StatusTypeDef   HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 247 HAL_StatusTypeDef   HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 248 HAL_StatusTypeDef   HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 249 HAL_StatusTypeDef   HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 250 HAL_StatusTypeDef   HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 251 HAL_StatusTypeDef   HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 252 HAL_StatusTypeDef   HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 253 uint32_t            HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 254 uint32_t            HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 255
 256 /**
 257   * @}
 258   */
 259
 260 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 261   * @{
 262   */
 263
 264 /* NAND Control functions  ****************************************************/
 265 HAL_StatusTypeDef   HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 266 HAL_StatusTypeDef   HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 267 HAL_StatusTypeDef   HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 268
 269 /**
 270   * @}
 271   */
 272
 273 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
 274   * @{
 275   */
 276
 277 /* NAND State functions *******************************************************/
 278 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 279 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 280
 281 /**
 282   * @}
 283   */
 284
 285 /**
 286   * @}
 287   */
 288
 289 /**
 290   * @}
 291   */
 292 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 293
 294 /**
 295   * @}
 296   */
 297
 298 #ifdef __cplusplus
 299 }
 300 #endif
 301
 302 #endif /* __STM32F1xx_HAL_NAND_H */
 303
 304 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/