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Merge commit '28203e909e83b1ac6becb45a3eadae23b190df32' into master-core-pull
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L1 / TARGET_NUCLEO_L152RE / stm32l152xe.h
1 /**
2 ******************************************************************************
3 * @file stm32l152xe.h
4 * @author MCD Application Team
5 * @version V2.0.0
6 * @date 5-September-2014
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32L1xx devices.
10 *
11 * This file contains:
12 * - Data structures and the address mapping for all peripherals
13 * - Peripheral's registers declarations and bits definition
14 * - Macros to access peripheral\92s registers hardware
15 *
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46 /** @addtogroup CMSIS
47 * @{
48 */
49
50 /** @addtogroup stm32l152xe
51 * @{
52 */
53
54 #ifndef __STM32L152xE_H
55 #define __STM32L152xE_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61
62 /** @addtogroup Configuration_section_for_CMSIS
63 * @{
64 */
65 /**
66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
67 */
68 #define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
69 #define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */
70 #define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */
71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
72
73 /**
74 * @}
75 */
76
77 /** @addtogroup Peripheral_interrupt_number_definition
78 * @{
79 */
80
81 /**
82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
83 * in @ref Library_configuration_section
84 */
85
86 /*!< Interrupt Number Definition */
87 typedef enum
88 {
89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
92 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
93 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
94 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
96 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
97 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
98
99 /****** STM32L specific Interrupt Numbers ***********************************************************/
100 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
101 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
102 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
103 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
104 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
105 RCC_IRQn = 5, /*!< RCC global Interrupt */
106 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
107 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
108 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
109 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
110 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
111 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
112 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
113 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
114 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
115 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
116 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
117 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
118 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
119 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
120 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
121 DAC_IRQn = 21, /*!< DAC Interrupt */
122 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
123 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
124 LCD_IRQn = 24, /*!< LCD Interrupt */
125 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
126 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
127 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
128 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
129 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
130 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
131 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
132 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
133 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
134 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
135 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
136 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
137 USART1_IRQn = 37, /*!< USART1 global Interrupt */
138 USART2_IRQn = 38, /*!< USART2 global Interrupt */
139 USART3_IRQn = 39, /*!< USART3 global Interrupt */
140 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
141 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
142 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
143 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
144 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
145 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
146 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
147 UART4_IRQn = 48, /*!< UART4 global Interrupt */
148 UART5_IRQn = 49, /*!< UART5 global Interrupt */
149 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
150 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
151 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
152 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
153 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
154 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
155 } IRQn_Type;
156
157 /**
158 * @}
159 */
160
161 #include "core_cm3.h"
162 #include "system_stm32l1xx.h"
163 #include <stdint.h>
164
165 /** @addtogroup Peripheral_registers_structures
166 * @{
167 */
168
169 /**
170 * @brief Analog to Digital Converter
171 */
172
173 typedef struct
174 {
175 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
176 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
177 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
178 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
179 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
180 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
181 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
182 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
183 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
184 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
185 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
186 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
187 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
188 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
189 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
190 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
191 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
192 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
193 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
194 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
195 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
196 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
197 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
198 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
199 } ADC_TypeDef;
200
201 typedef struct
202 {
203 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
204 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
205 } ADC_Common_TypeDef;
206
207 /**
208 * @brief Comparator
209 */
210
211 typedef struct
212 {
213 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
214 } COMP_TypeDef;
215
216 /**
217 * @brief CRC calculation unit
218 */
219
220 typedef struct
221 {
222 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
223 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
224 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
225 } CRC_TypeDef;
226
227 /**
228 * @brief Digital to Analog Converter
229 */
230
231 typedef struct
232 {
233 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
234 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
235 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
236 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
237 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
238 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
239 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
240 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
241 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
242 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
243 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
244 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
245 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
246 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
247 } DAC_TypeDef;
248
249 /**
250 * @brief Debug MCU
251 */
252
253 typedef struct
254 {
255 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
256 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
257 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
258 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
259 }DBGMCU_TypeDef;
260
261 /**
262 * @brief DMA Controller
263 */
264
265 typedef struct
266 {
267 __IO uint32_t CCR; /*!< DMA channel x configuration register */
268 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
269 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
270 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
271 } DMA_Channel_TypeDef;
272
273 typedef struct
274 {
275 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
276 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
277 } DMA_TypeDef;
278
279 /**
280 * @brief External Interrupt/Event Controller
281 */
282
283 typedef struct
284 {
285 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
286 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
287 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
288 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
289 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
290 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
291 } EXTI_TypeDef;
292
293 /**
294 * @brief FLASH Registers
295 */
296 typedef struct
297 {
298 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
299 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
300 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
301 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
302 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
303 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
304 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
305 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
306 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
307 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
308 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
309 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */
310 __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */
311 } FLASH_TypeDef;
312
313 /**
314 * @brief Option Bytes Registers
315 */
316 typedef struct
317 {
318 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
319 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
320 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
321 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
322 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
323 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
324 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
325 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
326 uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */
327 __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */
328 __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */
329 } OB_TypeDef;
330
331 /**
332 * @brief Operational Amplifier (OPAMP)
333 */
334 typedef struct
335 {
336 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
337 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
338 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
339 } OPAMP_TypeDef;
340
341 /**
342 * @brief General Purpose IO
343 */
344
345 typedef struct
346 {
347 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
348 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
349 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
350 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
351 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
352 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
353 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
354 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
355 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
356 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
357 } GPIO_TypeDef;
358
359 /**
360 * @brief SysTem Configuration
361 */
362
363 typedef struct
364 {
365 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
366 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
367 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
368 } SYSCFG_TypeDef;
369
370 /**
371 * @brief Inter-integrated Circuit Interface
372 */
373
374 typedef struct
375 {
376 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
377 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
378 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
379 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
380 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
381 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
382 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
383 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
384 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
385 } I2C_TypeDef;
386
387 /**
388 * @brief Independent WATCHDOG
389 */
390
391 typedef struct
392 {
393 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
394 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
395 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
396 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
397 } IWDG_TypeDef;
398
399 /**
400 * @brief LCD
401 */
402
403 typedef struct
404 {
405 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
406 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
407 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
408 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
409 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
410 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
411 } LCD_TypeDef;
412
413 /**
414 * @brief Power Control
415 */
416
417 typedef struct
418 {
419 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
420 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
421 } PWR_TypeDef;
422
423 /**
424 * @brief Reset and Clock Control
425 */
426
427 typedef struct
428 {
429 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
430 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
431 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
432 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
433 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
434 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
435 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
436 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
437 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
438 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
439 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
440 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
441 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
442 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
443 } RCC_TypeDef;
444
445 /**
446 * @brief Routing Interface
447 */
448
449 typedef struct
450 {
451 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
452 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
453 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
454 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
455 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
456 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
457 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
458 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
459 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
460 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
461 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
462 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
463 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
464 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
465 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
466 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
467 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
468 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
469 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
470 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
471 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
472 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
473 } RI_TypeDef;
474
475 /**
476 * @brief Real-Time Clock
477 */
478 typedef struct
479 {
480 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
481 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
482 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
483 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
484 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
485 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
486 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
487 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
488 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
489 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
490 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
491 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
492 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
493 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
494 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
495 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
496 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
497 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
498 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
499 uint32_t RESERVED7; /*!< Reserved, 0x4C */
500 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
501 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
502 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
503 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
504 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
505 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
506 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
507 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
508 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
509 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
510 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
511 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
512 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
513 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
514 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
515 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
516 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
517 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
518 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
519 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
520 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
521 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
522 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
523 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
524 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
525 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
526 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
527 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
528 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
529 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
530 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
531 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
532 } RTC_TypeDef;
533
534 /**
535 * @brief Serial Peripheral Interface
536 */
537
538 typedef struct
539 {
540 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
541 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
542 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
543 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
544 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
545 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
546 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
547 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
548 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
549 } SPI_TypeDef;
550
551 /**
552 * @brief TIM
553 */
554 typedef struct
555 {
556 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
557 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
558 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
559 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
560 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
561 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
562 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
563 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
564 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
565 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
566 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
567 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
568 uint32_t RESERVED12; /*!< Reserved, 0x30 */
569 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
570 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
571 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
572 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
573 uint32_t RESERVED17; /*!< Reserved, 0x44 */
574 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
575 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
576 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
577 } TIM_TypeDef;
578 /**
579 * @brief Universal Synchronous Asynchronous Receiver Transmitter
580 */
581
582 typedef struct
583 {
584 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
585 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
586 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
587 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
588 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
589 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
590 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
591 } USART_TypeDef;
592
593 /**
594 * @brief Universal Serial Bus Full Speed Device
595 */
596
597 typedef struct
598 {
599 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
600 __IO uint16_t RESERVED0; /*!< Reserved */
601 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
602 __IO uint16_t RESERVED1; /*!< Reserved */
603 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
604 __IO uint16_t RESERVED2; /*!< Reserved */
605 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
606 __IO uint16_t RESERVED3; /*!< Reserved */
607 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
608 __IO uint16_t RESERVED4; /*!< Reserved */
609 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
610 __IO uint16_t RESERVED5; /*!< Reserved */
611 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
612 __IO uint16_t RESERVED6; /*!< Reserved */
613 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
614 __IO uint16_t RESERVED7[17]; /*!< Reserved */
615 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
616 __IO uint16_t RESERVED8; /*!< Reserved */
617 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
618 __IO uint16_t RESERVED9; /*!< Reserved */
619 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
620 __IO uint16_t RESERVEDA; /*!< Reserved */
621 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
622 __IO uint16_t RESERVEDB; /*!< Reserved */
623 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
624 __IO uint16_t RESERVEDC; /*!< Reserved */
625 } USB_TypeDef;
626
627 /**
628 * @brief Window WATCHDOG
629 */
630 typedef struct
631 {
632 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
633 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
634 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
635 } WWDG_TypeDef;
636
637 /**
638 * @brief Universal Serial Bus Full Speed Device
639 */
640 /**
641 * @}
642 */
643
644 /** @addtogroup Peripheral_memory_map
645 * @{
646 */
647
648 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
649 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */
650 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
651 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
652 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
653 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
654 #define FLASH_BANK2_BASE ((uint32_t)0x08040000) /*!< FLASH BANK2 base address in the alias region */
655 #define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH BANK1 address */
656 #define FLASH_BANK2_END ((uint32_t)0x0807FFFF) /*!< Program end FLASH BANK2 address */
657 #define FLASH_EEPROM_END ((uint32_t)0x08083FFF) /*!< FLASH EEPROM end address (16KB) */
658
659 /*!< Peripheral memory map */
660 #define APB1PERIPH_BASE PERIPH_BASE
661 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
662 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
663
664 /*!< APB1 peripherals */
665 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
666 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
667 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
668 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00)
669 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
670 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
671 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400)
672 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
673 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
674 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
675 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
676 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
677 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
678 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
679 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
680 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
681 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
682 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
683
684 /* USB device FS */
685 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
686 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
687
688 /* USB device FS SRAM */
689 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
690 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400)
691 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00)
692 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04)
693 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C)
694
695 /*!< APB2 peripherals */
696 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
697 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
698 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800)
699 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00)
700 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000)
701 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400)
702 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700)
703 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
704 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
705
706 /*!< AHB peripherals */
707 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000)
708 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400)
709 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800)
710 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00)
711 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000)
712 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400)
713 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800)
714 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00)
715 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
716 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800)
717 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
718 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
719 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000)
720 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
721 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
722 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
723 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
724 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
725 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
726 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
727 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400)
728 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
729 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
730 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
731 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
732 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
733 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
734
735 /**
736 * @}
737 */
738
739 /** @addtogroup Peripheral_declaration
740 * @{
741 */
742
743 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
744 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
745 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
746 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
747 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
748 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
749 #define LCD ((LCD_TypeDef *) LCD_BASE)
750 #define RTC ((RTC_TypeDef *) RTC_BASE)
751 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
752 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
753 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
754 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
755 #define USART2 ((USART_TypeDef *) USART2_BASE)
756 #define USART3 ((USART_TypeDef *) USART3_BASE)
757 #define UART4 ((USART_TypeDef *) UART4_BASE)
758 #define UART5 ((USART_TypeDef *) UART5_BASE)
759 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
760 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
761 /* USB device FS */
762 #define USB ((USB_TypeDef *) USB_BASE)
763 /* USB device FS SRAM */
764 #define PWR ((PWR_TypeDef *) PWR_BASE)
765 #define DAC ((DAC_TypeDef *) DAC_BASE)
766 #define COMP ((COMP_TypeDef *) COMP_BASE)
767 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
768 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
769 #define RI ((RI_TypeDef *) RI_BASE)
770 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
771 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
772 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
773 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
774 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
775 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
776 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
777 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
778 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
779 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
780 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
781 #define USART1 ((USART_TypeDef *) USART1_BASE)
782 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
783 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
784 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
785 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
786 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
787 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
788 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
789 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
790 #define CRC ((CRC_TypeDef *) CRC_BASE)
791 #define RCC ((RCC_TypeDef *) RCC_BASE)
792 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
793 #define OB ((OB_TypeDef *) OB_BASE)
794 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
795 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
796 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
797 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
798 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
799 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
800 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
801 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
802 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
803 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
804 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
805 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
806 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
807 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
808 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
809
810 /**
811 * @}
812 */
813
814 /** @addtogroup Exported_constants
815 * @{
816 */
817
818 /** @addtogroup Peripheral_Registers_Bits_Definition
819 * @{
820 */
821
822 /******************************************************************************/
823 /* Peripheral Registers Bits Definition */
824 /******************************************************************************/
825 /******************************************************************************/
826 /* */
827 /* Analog to Digital Converter (ADC) */
828 /* */
829 /******************************************************************************/
830
831 /******************** Bit definition for ADC_SR register ********************/
832 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
833 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
834 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
835 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
836 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
837 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
838 #define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
839 #define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
840 #define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
841
842 /******************* Bit definition for ADC_CR1 register ********************/
843 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
844 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
845 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
846 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
847 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
848 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
849
850 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
851 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
852 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
853 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
854 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
855 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
856 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
857 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
858
859 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
860 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
861 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
862 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
863
864 #define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
865 #define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
866
867 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
868 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
869
870 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
871 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
872 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
873
874 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
875
876 /******************* Bit definition for ADC_CR2 register ********************/
877 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
878 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
879 #define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
880
881 #define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
882 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
883 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
884 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
885
886 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
887 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
888 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
889 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
890
891 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
892 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
893 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
894 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
895 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
896
897 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
898 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
899 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
900
901 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
902
903 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
904 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
905 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
906 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
907 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
908
909 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
910 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
911 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
912
913 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
914
915 /****************** Bit definition for ADC_SMPR1 register *******************/
916 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
917 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
918 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
919 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
920
921 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
922 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
923 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
924 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
925
926 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
927 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
928 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
929 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
930
931 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
932 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
933 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
934 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
935
936 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
937 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
938 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
939 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
940
941 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
942 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
943 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
944 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
945
946 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
947 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
948 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
949 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
950
951 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
952 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
953 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
954 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
955
956 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
957 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
958 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
959 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
960
961 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
962 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
963 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
964 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
965
966 /****************** Bit definition for ADC_SMPR2 register *******************/
967 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
968 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
969 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
970 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
971
972 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
973 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
974 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
975 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
976
977 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
978 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
979 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
980 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
981
982 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
983 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
984 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
985 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
986
987 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
988 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
989 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
990 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
991
992 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
993 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
994 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
995 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
996
997 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
998 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
999 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1000 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1001
1002 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
1003 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
1004 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
1005 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
1006
1007 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
1008 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1009 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1010 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1011
1012 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
1013 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
1014 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
1015 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
1016
1017 /****************** Bit definition for ADC_SMPR3 register *******************/
1018 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
1019 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1020 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1021 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1022
1023 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
1024 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
1025 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
1026 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
1027
1028 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
1029 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1030 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1031 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
1032
1033 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
1034 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
1035 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
1036 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
1037
1038 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
1039 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1040 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1041 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
1042
1043 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
1044 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1045 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1046 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1047
1048 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
1049 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1050 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1051 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1052
1053 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
1054 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
1055 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
1056 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
1057
1058 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
1059 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1060 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1061 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1062
1063 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
1064 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
1065 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
1066 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
1067
1068 /****************** Bit definition for ADC_JOFR1 register *******************/
1069 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
1070
1071 /****************** Bit definition for ADC_JOFR2 register *******************/
1072 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
1073
1074 /****************** Bit definition for ADC_JOFR3 register *******************/
1075 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
1076
1077 /****************** Bit definition for ADC_JOFR4 register *******************/
1078 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
1079
1080 /******************* Bit definition for ADC_HTR register ********************/
1081 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
1082
1083 /******************* Bit definition for ADC_LTR register ********************/
1084 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
1085
1086 /******************* Bit definition for ADC_SQR1 register *******************/
1087 #define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */
1088 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1089 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1090 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1091 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1092 #define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1093
1094 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
1095 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1096 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1097 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1098 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1099 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1100
1101 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
1102 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1103 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1104 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1105 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1106 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1107
1108 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
1109 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1110 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1111 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1112 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1113 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1114
1115 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
1116 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1117 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1118 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1119 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1120 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1121
1122 /******************* Bit definition for ADC_SQR2 register *******************/
1123 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
1124 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1125 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1126 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1127 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1128 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1129
1130 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
1131 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1132 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1133 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1134 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1135 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1136
1137 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
1138 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1139 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1140 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1141 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1142 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1143
1144 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
1145 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1146 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1147 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1148 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1149 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1150
1151 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
1152 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1153 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1154 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1155 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1156 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1157
1158 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
1159 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1160 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1161 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1162 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1163 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1164
1165 /******************* Bit definition for ADC_SQR3 register *******************/
1166 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
1167 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1168 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1169 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1170 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1171 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1172
1173 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
1174 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1175 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1176 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1177 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1178 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1179
1180 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
1181 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1182 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1183 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1184 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1185 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1186
1187 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
1188 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1189 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1190 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1191 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1192 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1193
1194 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
1195 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1196 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1197 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1198 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1199 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1200
1201 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
1202 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1203 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1204 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1205 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1206 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1207
1208 /******************* Bit definition for ADC_SQR4 register *******************/
1209 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
1210 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1211 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1212 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1213 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1214 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1215
1216 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
1217 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1218 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1219 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1220 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1221 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1222
1223 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
1224 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1225 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1226 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1227 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1228 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1229
1230 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
1231 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1232 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1233 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1234 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1235 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1236
1237 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
1238 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1239 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1240 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1241 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1242 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1243
1244 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
1245 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1246 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1247 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1248 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1249 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1250
1251 /******************* Bit definition for ADC_SQR5 register *******************/
1252 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
1253 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1254 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1255 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1256 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1257 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1258
1259 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
1260 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1261 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1262 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1263 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1264 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1265
1266 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
1267 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1268 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1269 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1270 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1271 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1272
1273 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
1274 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1275 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1276 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1277 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1278 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1279
1280 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
1281 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1282 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1283 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
1284 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
1285 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
1286
1287 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
1288 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
1289 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
1290 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
1291 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
1292 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
1293
1294
1295 /******************* Bit definition for ADC_JSQR register *******************/
1296 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
1297 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1298 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1299 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1300 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1301 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
1302
1303 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
1304 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1305 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1306 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1307 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
1308 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
1309
1310 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
1311 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1312 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1313 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1314 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
1315 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
1316
1317 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
1318 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
1319 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
1320 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
1321 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
1322 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
1323
1324 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
1325 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1326 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1327
1328 /******************* Bit definition for ADC_JDR1 register *******************/
1329 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1330
1331 /******************* Bit definition for ADC_JDR2 register *******************/
1332 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1333
1334 /******************* Bit definition for ADC_JDR3 register *******************/
1335 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1336
1337 /******************* Bit definition for ADC_JDR4 register *******************/
1338 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
1339
1340 /******************** Bit definition for ADC_DR register ********************/
1341 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
1342
1343 /****************** Bit definition for ADC_SMPR0 register *******************/
1344 #define ADC_SMPR0_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
1345 #define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1346 #define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1347 #define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1348
1349 #define ADC_SMPR0_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
1350 #define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */
1351 #define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */
1352 #define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */
1353
1354 /******************* Bit definition for ADC_CSR register ********************/
1355 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
1356 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
1357 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
1358 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
1359 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
1360 #define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
1361 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
1362
1363 /******************* Bit definition for ADC_CCR register ********************/
1364 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
1365 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1366 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1367 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
1368
1369 /******************************************************************************/
1370 /* */
1371 /* Analog Comparators (COMP) */
1372 /* */
1373 /******************************************************************************/
1374
1375 /****************** Bit definition for COMP_CSR register ********************/
1376 #define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
1377 #define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
1378 #define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
1379 #define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
1380 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
1381 #define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */
1382 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
1383
1384 #define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
1385 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
1386 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
1387 #define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
1388 #define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
1389 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1390 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1391 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1392 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
1393 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
1394 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
1395 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
1396
1397 #define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
1398 #define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
1399 #define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
1400
1401 #define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
1402 #define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
1403 #define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
1404
1405 /******************************************************************************/
1406 /* */
1407 /* Operational Amplifier (OPAMP) */
1408 /* */
1409 /******************************************************************************/
1410 /******************* Bit definition for OPAMP_CSR register ******************/
1411 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
1412 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
1413 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
1414 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
1415 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
1416 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
1417 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
1418 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
1419 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
1420 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
1421 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
1422 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
1423 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
1424 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
1425 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
1426 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
1427 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
1428 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
1429 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
1430 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
1431 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
1432 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
1433
1434 /******************* Bit definition for OPAMP_OTR register ******************/
1435 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
1436 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
1437 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
1438 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
1439 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
1440
1441 /******************* Bit definition for OPAMP_LPOTR register ****************/
1442 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
1443 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
1444 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
1445 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
1446
1447 /******************************************************************************/
1448 /* */
1449 /* CRC calculation unit (CRC) */
1450 /* */
1451 /******************************************************************************/
1452
1453 /******************* Bit definition for CRC_DR register *********************/
1454 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
1455
1456 /******************* Bit definition for CRC_IDR register ********************/
1457 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
1458
1459 /******************** Bit definition for CRC_CR register ********************/
1460 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
1461
1462 /******************************************************************************/
1463 /* */
1464 /* Digital to Analog Converter (DAC) */
1465 /* */
1466 /******************************************************************************/
1467
1468 /******************** Bit definition for DAC_CR register ********************/
1469 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
1470 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
1471 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
1472
1473 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
1474 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1475 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1476 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1477
1478 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1479 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1480 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1481
1482 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1483 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1484 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1485 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1486 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1487
1488 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
1489 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Interrupt enable */
1490 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
1491 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
1492 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
1493
1494 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1495 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
1496 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
1497 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
1498
1499 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1500 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
1501 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
1502
1503 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1504 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1505 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1506 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1507 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1508
1509 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
1510 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
1511 /***************** Bit definition for DAC_SWTRIGR register ******************/
1512 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
1513 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
1514
1515 /***************** Bit definition for DAC_DHR12R1 register ******************/
1516 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
1517
1518 /***************** Bit definition for DAC_DHR12L1 register ******************/
1519 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
1520
1521 /****************** Bit definition for DAC_DHR8R1 register ******************/
1522 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
1523
1524 /***************** Bit definition for DAC_DHR12R2 register ******************/
1525 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!<DAC channel2 12-bit Right aligned data */
1526
1527 /***************** Bit definition for DAC_DHR12L2 register ******************/
1528 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!<DAC channel2 12-bit Left aligned data */
1529
1530 /****************** Bit definition for DAC_DHR8R2 register ******************/
1531 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!<DAC channel2 8-bit Right aligned data */
1532
1533 /***************** Bit definition for DAC_DHR12RD register ******************/
1534 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
1535 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
1536
1537 /***************** Bit definition for DAC_DHR12LD register ******************/
1538 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
1539 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
1540
1541 /****************** Bit definition for DAC_DHR8RD register ******************/
1542 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
1543 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!<DAC channel2 8-bit Right aligned data */
1544
1545 /******************* Bit definition for DAC_DOR1 register *******************/
1546 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
1547
1548 /******************* Bit definition for DAC_DOR2 register *******************/
1549 #define DAC_DOR2_DACC2DOR ((uint_t)0x00000FFF) /*!<DAC channel2 data output */
1550
1551 /******************** Bit definition for DAC_SR register ********************/
1552 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
1553 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
1554
1555 /******************************************************************************/
1556 /* */
1557 /* Debug MCU (DBGMCU) */
1558 /* */
1559 /******************************************************************************/
1560
1561 /**************** Bit definition for DBGMCU_IDCODE register *****************/
1562 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
1563
1564 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
1565 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1566 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1567 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
1568 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
1569 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
1570 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
1571 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
1572 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
1573 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
1574 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
1575 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
1576 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
1577 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
1578 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
1579 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
1580 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
1581
1582 /****************** Bit definition for DBGMCU_CR register *******************/
1583 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
1584 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
1585 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
1586 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
1587
1588 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
1589 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1590 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1591
1592 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
1593
1594 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
1595 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
1596 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
1597 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
1598 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
1599 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
1600 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
1601 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
1602 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
1603 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
1604 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
1605
1606 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
1607
1608 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
1609 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
1610 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
1611
1612 /******************************************************************************/
1613 /* */
1614 /* DMA Controller (DMA) */
1615 /* */
1616 /******************************************************************************/
1617
1618 /******************* Bit definition for DMA_ISR register ********************/
1619 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
1620 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
1621 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
1622 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
1623 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
1624 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
1625 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
1626 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
1627 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
1628 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
1629 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
1630 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
1631 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
1632 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
1633 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
1634 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
1635 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
1636 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
1637 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
1638 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
1639 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
1640 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
1641 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
1642 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
1643 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
1644 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
1645 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
1646 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
1647
1648 /******************* Bit definition for DMA_IFCR register *******************/
1649 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
1650 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
1651 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
1652 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
1653 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
1654 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
1655 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
1656 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
1657 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
1658 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
1659 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
1660 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
1661 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
1662 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
1663 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
1664 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
1665 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
1666 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
1667 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
1668 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
1669 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
1670 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
1671 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
1672 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
1673 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
1674 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
1675 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
1676 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
1677
1678 /******************* Bit definition for DMA_CCR register *******************/
1679 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable*/
1680 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
1681 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
1682 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
1683 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
1684 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
1685 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
1686 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
1687
1688 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
1689 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1690 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1691
1692 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
1693 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1694 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1695
1696 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
1697 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1698 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1699
1700 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
1701
1702 /****************** Bit definition for DMA_CNDTR1 register ******************/
1703 #define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1704
1705 /****************** Bit definition for DMA_CNDTR2 register ******************/
1706 #define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1707
1708 /****************** Bit definition for DMA_CNDTR3 register ******************/
1709 #define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1710
1711 /****************** Bit definition for DMA_CNDTR4 register ******************/
1712 #define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1713
1714 /****************** Bit definition for DMA_CNDTR5 register ******************/
1715 #define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1716
1717 /****************** Bit definition for DMA_CNDTR6 register ******************/
1718 #define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1719
1720 /****************** Bit definition for DMA_CNDTR7 register ******************/
1721 #define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1722
1723 /****************** Bit definition for DMA_CPAR1 register *******************/
1724 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1725
1726 /****************** Bit definition for DMA_CPAR2 register *******************/
1727 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1728
1729 /****************** Bit definition for DMA_CPAR3 register *******************/
1730 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1731
1732
1733 /****************** Bit definition for DMA_CPAR4 register *******************/
1734 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1735
1736 /****************** Bit definition for DMA_CPAR5 register *******************/
1737 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1738
1739 /****************** Bit definition for DMA_CPAR6 register *******************/
1740 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1741
1742
1743 /****************** Bit definition for DMA_CPAR7 register *******************/
1744 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1745
1746 /****************** Bit definition for DMA_CMAR1 register *******************/
1747 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1748
1749 /****************** Bit definition for DMA_CMAR2 register *******************/
1750 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1751
1752 /****************** Bit definition for DMA_CMAR3 register *******************/
1753 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1754
1755
1756 /****************** Bit definition for DMA_CMAR4 register *******************/
1757 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1758
1759 /****************** Bit definition for DMA_CMAR5 register *******************/
1760 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1761
1762 /****************** Bit definition for DMA_CMAR6 register *******************/
1763 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1764
1765 /****************** Bit definition for DMA_CMAR7 register *******************/
1766 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1767
1768 /******************************************************************************/
1769 /* */
1770 /* External Interrupt/Event Controller (EXTI) */
1771 /* */
1772 /******************************************************************************/
1773
1774 /******************* Bit definition for EXTI_IMR register *******************/
1775 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
1776 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
1777 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
1778 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
1779 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
1780 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
1781 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
1782 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
1783 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
1784 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
1785 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
1786 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
1787 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
1788 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
1789 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
1790 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
1791 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
1792 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
1793 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
1794 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
1795 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
1796 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
1797 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
1798 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
1799
1800 /******************* Bit definition for EXTI_EMR register *******************/
1801 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
1802 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
1803 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
1804 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
1805 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
1806 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
1807 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
1808 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
1809 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
1810 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
1811 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
1812 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
1813 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
1814 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
1815 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
1816 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
1817 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
1818 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
1819 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
1820 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
1821 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
1822 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
1823 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
1824 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
1825
1826 /****************** Bit definition for EXTI_RTSR register *******************/
1827 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
1828 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
1829 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
1830 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
1831 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
1832 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
1833 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
1834 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
1835 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
1836 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
1837 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
1838 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
1839 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
1840 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
1841 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
1842 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
1843 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
1844 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
1845 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
1846 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
1847 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
1848 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
1849 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
1850 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
1851
1852 /****************** Bit definition for EXTI_FTSR register *******************/
1853 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
1854 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
1855 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
1856 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
1857 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
1858 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
1859 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
1860 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
1861 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
1862 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
1863 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
1864 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
1865 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
1866 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
1867 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
1868 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
1869 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
1870 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
1871 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
1872 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
1873 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
1874 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
1875 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
1876 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
1877
1878 /****************** Bit definition for EXTI_SWIER register ******************/
1879 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
1880 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
1881 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
1882 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
1883 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
1884 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
1885 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
1886 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
1887 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
1888 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
1889 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
1890 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
1891 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
1892 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
1893 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
1894 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
1895 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
1896 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
1897 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
1898 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
1899 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
1900 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
1901 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
1902 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
1903
1904 /******************* Bit definition for EXTI_PR register ********************/
1905 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
1906 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
1907 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
1908 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
1909 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
1910 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
1911 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
1912 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
1913 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
1914 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
1915 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
1916 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
1917 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
1918 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
1919 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
1920 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
1921 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
1922 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
1923 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
1924 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
1925 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
1926 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
1927 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
1928 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
1929
1930 /******************************************************************************/
1931 /* */
1932 /* FLASH, DATA EEPROM and Option Bytes Registers */
1933 /* (FLASH, DATA_EEPROM, OB) */
1934 /* */
1935 /******************************************************************************/
1936
1937 /******************* Bit definition for FLASH_ACR register ******************/
1938 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
1939 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
1940 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
1941 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
1942 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
1943
1944 /******************* Bit definition for FLASH_PECR register ******************/
1945 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
1946 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
1947 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
1948 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
1949 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
1950 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
1951 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
1952 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
1953 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
1954 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
1955 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
1956 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
1957
1958 /****************** Bit definition for FLASH_PDKEYR register ******************/
1959 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1960
1961 /****************** Bit definition for FLASH_PEKEYR register ******************/
1962 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1963
1964 /****************** Bit definition for FLASH_PRGKEYR register ******************/
1965 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
1966
1967 /****************** Bit definition for FLASH_OPTKEYR register ******************/
1968 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
1969
1970 /****************** Bit definition for FLASH_SR register *******************/
1971 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
1972 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
1973 #define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */
1974 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
1975
1976 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
1977 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
1978 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
1979 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
1980 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
1981
1982 /****************** Bit definition for FLASH_OBR register *******************/
1983 #define FLASH_OBR_RDPRT ((uint32_t)0x000000FF) /*!< Read Protection */
1984 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
1985 #define FLASH_OBR_USER ((uint32_t)0x00F00000) /*!< User Option Bytes */
1986 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
1987 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
1988 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
1989 #define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) /*!< BFB2 */
1990
1991 /****************** Bit definition for FLASH_WRPR register ******************/
1992 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
1993 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
1994 #define FLASH_WRPR3_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
1995 #define FLASH_WRPR4_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
1996
1997 /******************************************************************************/
1998 /* */
1999 /* General Purpose I/O */
2000 /* */
2001 /******************************************************************************/
2002 /****************** Bits definition for GPIO_MODER register *****************/
2003 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
2004 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
2005 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
2006
2007 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
2008 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
2009 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
2010
2011 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
2012 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
2013 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
2014
2015 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
2016 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
2017 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
2018
2019 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
2020 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
2021 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
2022
2023 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
2024 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
2025 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
2026
2027 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
2028 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
2029 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
2030
2031 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
2032 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
2033 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
2034
2035 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
2036 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
2037 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
2038
2039 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
2040 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
2041 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
2042
2043 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
2044 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
2045 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
2046
2047 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
2048 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
2049 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
2050
2051 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
2052 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
2053 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
2054
2055 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
2056 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
2057 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
2058
2059 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
2060 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
2061 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
2062
2063 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
2064 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
2065 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
2066
2067 /****************** Bits definition for GPIO_OTYPER register ****************/
2068 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
2069 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
2070 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
2071 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
2072 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
2073 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
2074 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
2075 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
2076 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
2077 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
2078 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
2079 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
2080 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
2081 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
2082 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
2083 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
2084
2085 /****************** Bits definition for GPIO_OSPEEDR register ***************/
2086 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
2087 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
2088 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
2089
2090 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
2091 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
2092 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
2093
2094 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
2095 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
2096 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
2097
2098 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
2099 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
2100 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
2101
2102 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
2103 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
2104 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
2105
2106 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
2107 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
2108 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
2109
2110 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
2111 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
2112 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
2113
2114 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
2115 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
2116 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
2117
2118 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
2119 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
2120 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
2121
2122 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
2123 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
2124 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
2125
2126 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
2127 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
2128 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
2129
2130 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
2131 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
2132 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
2133
2134 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
2135 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
2136 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
2137
2138 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
2139 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
2140 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
2141
2142 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
2143 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
2144 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
2145
2146 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
2147 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
2148 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
2149
2150 /****************** Bits definition for GPIO_PUPDR register *****************/
2151 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
2152 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
2153 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
2154
2155 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
2156 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
2157 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
2158
2159 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
2160 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
2161 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
2162
2163 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
2164 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
2165 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
2166
2167 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
2168 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
2169 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
2170
2171 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
2172 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
2173 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
2174
2175 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
2176 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
2177 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
2178
2179 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
2180 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
2181 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
2182
2183 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
2184 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
2185 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
2186
2187 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
2188 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
2189 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
2190
2191 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
2192 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
2193 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
2194
2195 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
2196 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
2197 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
2198
2199 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
2200 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
2201 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
2202
2203 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
2204 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
2205 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
2206
2207 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
2208 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
2209 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
2210 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
2211 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
2212 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
2213
2214 /****************** Bits definition for GPIO_IDR register *******************/
2215 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
2216 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
2217 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
2218 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
2219 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
2220 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
2221 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
2222 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
2223 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
2224 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
2225 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
2226 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
2227 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
2228 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
2229 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
2230 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
2231
2232 /****************** Bits definition for GPIO_ODR register *******************/
2233 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
2234 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
2235 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
2236 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
2237 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
2238 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
2239 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
2240 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
2241 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
2242 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
2243 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
2244 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
2245 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
2246 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
2247 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
2248 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
2249
2250 /****************** Bits definition for GPIO_BSRR register ******************/
2251 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
2252 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
2253 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
2254 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
2255 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
2256 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
2257 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
2258 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
2259 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
2260 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
2261 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
2262 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
2263 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
2264 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
2265 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
2266 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
2267 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
2268 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
2269 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
2270 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
2271 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
2272 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
2273 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
2274 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
2275 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
2276 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
2277 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
2278 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
2279 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
2280 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
2281 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
2282 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
2283
2284 /****************** Bit definition for GPIO_LCKR register ********************/
2285 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
2286 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
2287 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
2288 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
2289 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
2290 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
2291 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
2292 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
2293 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
2294 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
2295 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
2296 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
2297 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
2298 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
2299 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
2300 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
2301 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
2302
2303 /****************** Bit definition for GPIO_AFRL register ********************/
2304 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
2305 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
2306 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
2307 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
2308 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
2309 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
2310 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
2311 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
2312
2313 /****************** Bit definition for GPIO_AFRH register ********************/
2314 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
2315 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
2316 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
2317 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
2318 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
2319 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
2320 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
2321 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
2322
2323 /****************** Bit definition for GPIO_BRR register *********************/
2324 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
2325 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
2326 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
2327 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
2328 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
2329 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
2330 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
2331 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
2332 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
2333 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
2334 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
2335 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
2336 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
2337 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
2338 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
2339 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
2340
2341
2342 /******************************************************************************/
2343 /* */
2344 /* Inter-integrated Circuit Interface (I2C) */
2345 /* */
2346 /******************************************************************************/
2347
2348 /******************* Bit definition for I2C_CR1 register ********************/
2349 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
2350 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
2351 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
2352 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
2353 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
2354 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
2355 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
2356 #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
2357 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
2358 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
2359 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
2360 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
2361 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
2362 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
2363
2364 /******************* Bit definition for I2C_CR2 register ********************/
2365 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
2366 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2367 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2368 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2369 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
2370 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
2371 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
2372
2373 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
2374 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
2375 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
2376 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
2377 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
2378
2379 /******************* Bit definition for I2C_OAR1 register *******************/
2380 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
2381 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
2382
2383 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
2384 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
2385 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
2386 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
2387 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
2388 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
2389 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
2390 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
2391 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
2392 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
2393
2394 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
2395
2396 /******************* Bit definition for I2C_OAR2 register *******************/
2397 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
2398 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
2399
2400 /******************** Bit definition for I2C_DR register ********************/
2401 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!< 8-bit Data Register */
2402
2403 /******************* Bit definition for I2C_SR1 register ********************/
2404 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
2405 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
2406 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
2407 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
2408 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
2409 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
2410 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
2411 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
2412 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
2413 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
2414 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
2415 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
2416 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
2417 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
2418
2419 /******************* Bit definition for I2C_SR2 register ********************/
2420 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
2421 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
2422 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
2423 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
2424 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
2425 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
2426 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
2427 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
2428
2429 /******************* Bit definition for I2C_CCR register ********************/
2430 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
2431 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
2432 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
2433
2434 /****************** Bit definition for I2C_TRISE register *******************/
2435 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
2436
2437 /******************************************************************************/
2438 /* */
2439 /* Independent WATCHDOG (IWDG) */
2440 /* */
2441 /******************************************************************************/
2442
2443 /******************* Bit definition for IWDG_KR register ********************/
2444 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
2445
2446 /******************* Bit definition for IWDG_PR register ********************/
2447 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
2448 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2449 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2450 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2451
2452 /******************* Bit definition for IWDG_RLR register *******************/
2453 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
2454
2455 /******************* Bit definition for IWDG_SR register ********************/
2456 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
2457 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
2458
2459 /******************************************************************************/
2460 /* */
2461 /* LCD Controller (LCD) */
2462 /* */
2463 /******************************************************************************/
2464
2465 /******************* Bit definition for LCD_CR register *********************/
2466 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
2467 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
2468
2469 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
2470 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
2471 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
2472 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
2473
2474 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
2475 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
2476 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
2477
2478 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
2479
2480 /******************* Bit definition for LCD_FCR register ********************/
2481 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
2482 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
2483 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
2484
2485 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
2486 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2487 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2488 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2489
2490 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
2491 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
2492 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
2493 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
2494
2495 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
2496 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2497 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2498 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
2499
2500 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
2501 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
2502 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
2503 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
2504
2505 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
2506 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2507 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2508
2509 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
2510 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
2511
2512 /******************* Bit definition for LCD_SR register *********************/
2513 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
2514 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
2515 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
2516 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
2517 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
2518 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
2519
2520 /******************* Bit definition for LCD_CLR register ********************/
2521 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
2522 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
2523
2524 /******************* Bit definition for LCD_RAM register ********************/
2525 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
2526
2527 /******************************************************************************/
2528 /* */
2529 /* Power Control (PWR) */
2530 /* */
2531 /******************************************************************************/
2532
2533 /******************** Bit definition for PWR_CR register ********************/
2534 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
2535 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
2536 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
2537 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
2538 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
2539
2540 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
2541 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2542 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2543 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
2544
2545 /*!< PVD level configuration */
2546 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
2547 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
2548 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
2549 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
2550 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
2551 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
2552 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
2553 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
2554
2555 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
2556 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
2557 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
2558
2559 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
2560 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2561 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2562 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
2563
2564 /******************* Bit definition for PWR_CSR register ********************/
2565 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
2566 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
2567 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
2568 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
2569 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
2570 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
2571
2572 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
2573 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
2574 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
2575
2576 /******************************************************************************/
2577 /* */
2578 /* Reset and Clock Control (RCC) */
2579 /* */
2580 /******************************************************************************/
2581 /******************** Bit definition for RCC_CR register ********************/
2582 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
2583 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
2584
2585 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
2586 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
2587
2588 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
2589 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
2590 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
2591
2592 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
2593 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
2594 #define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
2595
2596 #define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
2597 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
2598 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
2599
2600 /******************** Bit definition for RCC_ICSCR register *****************/
2601 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
2602 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
2603
2604 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
2605 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
2606 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
2607 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
2608 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
2609 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
2610 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
2611 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
2612 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
2613 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
2614
2615 /******************** Bit definition for RCC_CFGR register ******************/
2616 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
2617 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2618 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2619
2620 /*!< SW configuration */
2621 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
2622 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
2623 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
2624 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
2625
2626 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
2627 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2628 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2629
2630 /*!< SWS configuration */
2631 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
2632 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
2633 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
2634 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
2635
2636 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
2637 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2638 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2639 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2640 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
2641
2642 /*!< HPRE configuration */
2643 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
2644 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
2645 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
2646 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
2647 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
2648 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
2649 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
2650 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
2651 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
2652
2653 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
2654 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2655 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2656 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2657
2658 /*!< PPRE1 configuration */
2659 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2660 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
2661 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
2662 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
2663 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
2664
2665 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
2666 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2667 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2668 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
2669
2670 /*!< PPRE2 configuration */
2671 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2672 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
2673 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
2674 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
2675 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
2676
2677 /*!< PLL entry clock source*/
2678 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
2679
2680 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
2681 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
2682
2683
2684 /*!< PLLMUL configuration */
2685 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
2686 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2687 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2688 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
2689 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
2690
2691 /*!< PLLMUL configuration */
2692 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
2693 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
2694 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
2695 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
2696 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
2697 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
2698 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
2699 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
2700 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
2701
2702 /*!< PLLDIV configuration */
2703 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
2704 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
2705 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
2706
2707
2708 /*!< PLLDIV configuration */
2709 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
2710 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
2711 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
2712 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
2713
2714
2715 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
2716 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2717 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2718 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
2719
2720 /*!< MCO configuration */
2721 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2722 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
2723 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
2724 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
2725 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
2726 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
2727 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
2728 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
2729
2730 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
2731 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
2732 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
2733 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
2734
2735 /*!< MCO Prescaler configuration */
2736 #define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
2737 #define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
2738 #define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
2739 #define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
2740 #define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
2741
2742 /*!<****************** Bit definition for RCC_CIR register ********************/
2743 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
2744 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
2745 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
2746 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
2747 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
2748 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
2749 #define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
2750 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
2751
2752 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
2753 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
2754 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
2755 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
2756 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
2757 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
2758 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
2759
2760 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
2761 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
2762 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
2763 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
2764 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
2765 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
2766 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
2767 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
2768
2769 /***************** Bit definition for RCC_AHBRSTR register ******************/
2770 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
2771 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
2772 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
2773 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
2774 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
2775 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
2776 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /*!< GPIO port F reset */
2777 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /*!< GPIO port G reset */
2778 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
2779 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
2780 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
2781 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
2782
2783 /***************** Bit definition for RCC_APB2RSTR register *****************/
2784 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
2785 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
2786 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
2787 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
2788 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
2789 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
2790 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
2791
2792 /***************** Bit definition for RCC_APB1RSTR register *****************/
2793 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
2794 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
2795 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
2796 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
2797 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
2798 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
2799 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
2800 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
2801 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
2802 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
2803 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
2804 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
2805 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
2806 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
2807 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
2808 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
2809 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
2810 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
2811 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
2812 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
2813
2814 /****************** Bit definition for RCC_AHBENR register ******************/
2815 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
2816 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
2817 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
2818 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
2819 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
2820 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
2821 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /*!< GPIO port F clock enable */
2822 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /*!< GPIO port G clock enable */
2823 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
2824 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
2825 the Flash memory is in power down mode) */
2826 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
2827 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
2828
2829 /****************** Bit definition for RCC_APB2ENR register *****************/
2830 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
2831 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
2832 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
2833 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
2834 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
2835 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
2836 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
2837
2838 /***************** Bit definition for RCC_APB1ENR register ******************/
2839 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
2840 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
2841 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
2842 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
2843 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2844 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
2845 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
2846 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
2847 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
2848 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
2849 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
2850 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
2851 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
2852 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
2853 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
2854 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
2855 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
2856 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
2857 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
2858 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
2859
2860 /****************** Bit definition for RCC_AHBLPENR register ****************/
2861 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
2862 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
2863 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
2864 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
2865 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
2866 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
2867 #define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /*!< GPIO port F clock enabled in sleep mode */
2868 #define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /*!< GPIO port G clock enabled in sleep mode */
2869 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
2870 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
2871 (has effect only when the Flash memory is
2872 in power down mode) */
2873 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
2874 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
2875 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
2876
2877 /****************** Bit definition for RCC_APB2LPENR register ***************/
2878 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
2879 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
2880 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
2881 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
2882 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
2883 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
2884 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
2885
2886 /***************** Bit definition for RCC_APB1LPENR register ****************/
2887 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
2888 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
2889 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
2890 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
2891 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
2892 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
2893 #define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
2894 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
2895 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
2896 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
2897 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
2898 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
2899 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /*!< UART 4 clock enabled in sleep mode */
2900 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /*!< UART 5 clock enabled in sleep mode */
2901 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
2902 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
2903 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
2904 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
2905 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
2906 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
2907
2908 /******************* Bit definition for RCC_CSR register ********************/
2909 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
2910 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
2911
2912 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
2913 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
2914 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
2915
2916 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
2917 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
2918
2919 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
2920 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2921 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2922
2923 /*!< RTC congiguration */
2924 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2925 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
2926 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
2927 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
2928
2929 #define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
2930 #define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
2931
2932 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
2933 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
2934 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
2935 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
2936 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
2937 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
2938 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
2939 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
2940
2941 /******************************************************************************/
2942 /* */
2943 /* Real-Time Clock (RTC) */
2944 /* */
2945 /******************************************************************************/
2946 /******************** Bits definition for RTC_TR register *******************/
2947 #define RTC_TR_PM ((uint32_t)0x00400000)
2948 #define RTC_TR_HT ((uint32_t)0x00300000)
2949 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
2950 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
2951 #define RTC_TR_HU ((uint32_t)0x000F0000)
2952 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
2953 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
2954 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
2955 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
2956 #define RTC_TR_MNT ((uint32_t)0x00007000)
2957 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
2958 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
2959 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
2960 #define RTC_TR_MNU ((uint32_t)0x00000F00)
2961 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
2962 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
2963 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
2964 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
2965 #define RTC_TR_ST ((uint32_t)0x00000070)
2966 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
2967 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
2968 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
2969 #define RTC_TR_SU ((uint32_t)0x0000000F)
2970 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
2971 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
2972 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
2973 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
2974
2975 /******************** Bits definition for RTC_DR register *******************/
2976 #define RTC_DR_YT ((uint32_t)0x00F00000)
2977 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
2978 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
2979 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
2980 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
2981 #define RTC_DR_YU ((uint32_t)0x000F0000)
2982 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
2983 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
2984 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
2985 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
2986 #define RTC_DR_WDU ((uint32_t)0x0000E000)
2987 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
2988 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
2989 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
2990 #define RTC_DR_MT ((uint32_t)0x00001000)
2991 #define RTC_DR_MU ((uint32_t)0x00000F00)
2992 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
2993 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
2994 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
2995 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
2996 #define RTC_DR_DT ((uint32_t)0x00000030)
2997 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
2998 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
2999 #define RTC_DR_DU ((uint32_t)0x0000000F)
3000 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
3001 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
3002 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
3003 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
3004
3005 /******************** Bits definition for RTC_CR register *******************/
3006 #define RTC_CR_COE ((uint32_t)0x00800000)
3007 #define RTC_CR_OSEL ((uint32_t)0x00600000)
3008 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
3009 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
3010 #define RTC_CR_POL ((uint32_t)0x00100000)
3011 #define RTC_CR_COSEL ((uint32_t)0x00080000)
3012 #define RTC_CR_BCK ((uint32_t)0x00040000)
3013 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
3014 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
3015 #define RTC_CR_TSIE ((uint32_t)0x00008000)
3016 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
3017 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
3018 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
3019 #define RTC_CR_TSE ((uint32_t)0x00000800)
3020 #define RTC_CR_WUTE ((uint32_t)0x00000400)
3021 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
3022 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
3023 #define RTC_CR_DCE ((uint32_t)0x00000080)
3024 #define RTC_CR_FMT ((uint32_t)0x00000040)
3025 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
3026 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
3027 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
3028 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
3029 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
3030 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
3031 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
3032
3033 /******************** Bits definition for RTC_ISR register ******************/
3034 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
3035 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
3036 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
3037 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
3038 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
3039 #define RTC_ISR_TSF ((uint32_t)0x00000800)
3040 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
3041 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
3042 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
3043 #define RTC_ISR_INIT ((uint32_t)0x00000080)
3044 #define RTC_ISR_INITF ((uint32_t)0x00000040)
3045 #define RTC_ISR_RSF ((uint32_t)0x00000020)
3046 #define RTC_ISR_INITS ((uint32_t)0x00000010)
3047 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
3048 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
3049 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
3050 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
3051
3052 /******************** Bits definition for RTC_PRER register *****************/
3053 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
3054 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
3055
3056 /******************** Bits definition for RTC_WUTR register *****************/
3057 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
3058
3059 /******************** Bits definition for RTC_CALIBR register ***************/
3060 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
3061 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
3062
3063 /******************** Bits definition for RTC_ALRMAR register ***************/
3064 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
3065 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
3066 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
3067 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
3068 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
3069 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
3070 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
3071 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
3072 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
3073 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
3074 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
3075 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
3076 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
3077 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
3078 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
3079 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
3080 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
3081 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
3082 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
3083 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
3084 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
3085 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
3086 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
3087 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
3088 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
3089 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
3090 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
3091 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
3092 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
3093 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
3094 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
3095 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
3096 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
3097 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
3098 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
3099 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
3100 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
3101 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
3102 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
3103 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
3104
3105 /******************** Bits definition for RTC_ALRMBR register ***************/
3106 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
3107 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
3108 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
3109 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
3110 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
3111 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
3112 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
3113 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
3114 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
3115 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
3116 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
3117 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
3118 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
3119 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
3120 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
3121 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
3122 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
3123 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
3124 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
3125 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
3126 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
3127 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
3128 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
3129 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
3130 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
3131 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
3132 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
3133 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
3134 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
3135 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
3136 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
3137 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
3138 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
3139 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
3140 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
3141 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
3142 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
3143 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
3144 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
3145 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
3146
3147 /******************** Bits definition for RTC_WPR register ******************/
3148 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
3149
3150 /******************** Bits definition for RTC_SSR register ******************/
3151 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
3152
3153 /******************** Bits definition for RTC_SHIFTR register ***************/
3154 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
3155 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
3156
3157 /******************** Bits definition for RTC_TSTR register *****************/
3158 #define RTC_TSTR_PM ((uint32_t)0x00400000)
3159 #define RTC_TSTR_HT ((uint32_t)0x00300000)
3160 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
3161 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
3162 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
3163 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
3164 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
3165 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
3166 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
3167 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
3168 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
3169 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
3170 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
3171 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
3172 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
3173 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
3174 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
3175 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
3176 #define RTC_TSTR_ST ((uint32_t)0x00000070)
3177 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
3178 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
3179 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
3180 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
3181 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
3182 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
3183 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
3184 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
3185
3186 /******************** Bits definition for RTC_TSDR register *****************/
3187 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
3188 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
3189 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
3190 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
3191 #define RTC_TSDR_MT ((uint32_t)0x00001000)
3192 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
3193 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
3194 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
3195 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
3196 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
3197 #define RTC_TSDR_DT ((uint32_t)0x00000030)
3198 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
3199 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
3200 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
3201 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
3202 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
3203 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
3204 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
3205
3206 /******************** Bits definition for RTC_TSSSR register ****************/
3207 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
3208
3209 /******************** Bits definition for RTC_CAL register *****************/
3210 #define RTC_CALR_CALP ((uint32_t)0x00008000)
3211 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
3212 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
3213 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
3214 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
3215 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
3216 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
3217 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
3218 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
3219 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
3220 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
3221 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
3222 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
3223
3224 /******************** Bits definition for RTC_TAFCR register ****************/
3225 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
3226 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
3227 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
3228 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
3229 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
3230 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
3231 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
3232 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
3233 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
3234 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
3235 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
3236 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
3237 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
3238 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
3239 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
3240 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
3241 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
3242 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
3243 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
3244 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
3245
3246 /******************** Bits definition for RTC_ALRMASSR register *************/
3247 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
3248 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
3249 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
3250 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
3251 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
3252 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
3253
3254 /******************** Bits definition for RTC_ALRMBSSR register *************/
3255 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
3256 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
3257 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
3258 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
3259 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
3260 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
3261
3262 /******************** Bits definition for RTC_BKP0R register ****************/
3263 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
3264
3265 /******************** Bits definition for RTC_BKP1R register ****************/
3266 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
3267
3268 /******************** Bits definition for RTC_BKP2R register ****************/
3269 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
3270
3271 /******************** Bits definition for RTC_BKP3R register ****************/
3272 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
3273
3274 /******************** Bits definition for RTC_BKP4R register ****************/
3275 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
3276
3277 /******************** Bits definition for RTC_BKP5R register ****************/
3278 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
3279
3280 /******************** Bits definition for RTC_BKP6R register ****************/
3281 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
3282
3283 /******************** Bits definition for RTC_BKP7R register ****************/
3284 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
3285
3286 /******************** Bits definition for RTC_BKP8R register ****************/
3287 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
3288
3289 /******************** Bits definition for RTC_BKP9R register ****************/
3290 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
3291
3292 /******************** Bits definition for RTC_BKP10R register ***************/
3293 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
3294
3295 /******************** Bits definition for RTC_BKP11R register ***************/
3296 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
3297
3298 /******************** Bits definition for RTC_BKP12R register ***************/
3299 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
3300
3301 /******************** Bits definition for RTC_BKP13R register ***************/
3302 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
3303
3304 /******************** Bits definition for RTC_BKP14R register ***************/
3305 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
3306
3307 /******************** Bits definition for RTC_BKP15R register ***************/
3308 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
3309
3310 /******************** Bits definition for RTC_BKP16R register ***************/
3311 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
3312
3313 /******************** Bits definition for RTC_BKP17R register ***************/
3314 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
3315
3316 /******************** Bits definition for RTC_BKP18R register ***************/
3317 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
3318
3319 /******************** Bits definition for RTC_BKP19R register ***************/
3320 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
3321
3322 /******************** Bits definition for RTC_BKP20R register ***************/
3323 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
3324
3325 /******************** Bits definition for RTC_BKP21R register ***************/
3326 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
3327
3328 /******************** Bits definition for RTC_BKP22R register ***************/
3329 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
3330
3331 /******************** Bits definition for RTC_BKP23R register ***************/
3332 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
3333
3334 /******************** Bits definition for RTC_BKP24R register ***************/
3335 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
3336
3337 /******************** Bits definition for RTC_BKP25R register ***************/
3338 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
3339
3340 /******************** Bits definition for RTC_BKP26R register ***************/
3341 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
3342
3343 /******************** Bits definition for RTC_BKP27R register ***************/
3344 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
3345
3346 /******************** Bits definition for RTC_BKP28R register ***************/
3347 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
3348
3349 /******************** Bits definition for RTC_BKP29R register ***************/
3350 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
3351
3352 /******************** Bits definition for RTC_BKP30R register ***************/
3353 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
3354
3355 /******************** Bits definition for RTC_BKP31R register ***************/
3356 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
3357
3358 /******************** Number of backup registers ******************************/
3359 #define RTC_BKP_NUMBER 32
3360
3361 /******************************************************************************/
3362 /* */
3363 /* Serial Peripheral Interface (SPI) */
3364 /* */
3365 /******************************************************************************/
3366
3367 /******************* Bit definition for SPI_CR1 register ********************/
3368 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
3369 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
3370 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
3371
3372 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
3373 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
3374 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
3375 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
3376
3377 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
3378 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
3379 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
3380 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
3381 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
3382 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
3383 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
3384 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
3385 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
3386 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
3387
3388 /******************* Bit definition for SPI_CR2 register ********************/
3389 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
3390 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
3391 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
3392 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame format */
3393 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
3394 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
3395 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
3396
3397 /******************** Bit definition for SPI_SR register ********************/
3398 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
3399 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
3400 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
3401 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
3402 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
3403 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
3404 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
3405 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
3406 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
3407
3408 /******************** Bit definition for SPI_DR register ********************/
3409 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
3410
3411 /******************* Bit definition for SPI_CRCPR register ******************/
3412 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
3413
3414 /****************** Bit definition for SPI_RXCRCR register ******************/
3415 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
3416
3417 /****************** Bit definition for SPI_TXCRCR register ******************/
3418 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
3419
3420 /****************** Bit definition for SPI_I2SCFGR register *****************/
3421 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
3422
3423 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
3424 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
3425 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
3426
3427 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
3428
3429 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
3430 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3431 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3432
3433 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
3434
3435 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
3436 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3437 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3438
3439 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
3440 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
3441
3442 /****************** Bit definition for SPI_I2SPR register *******************/
3443 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
3444 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
3445 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
3446
3447 /******************************************************************************/
3448 /* */
3449 /* System Configuration (SYSCFG) */
3450 /* */
3451 /******************************************************************************/
3452 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
3453 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
3454 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3455 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3456 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
3457 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3458 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3459
3460 /***************** Bit definition for SYSCFG_PMC register *******************/
3461 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
3462
3463 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
3464 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
3465 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
3466 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
3467 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
3468
3469 /**
3470 * @brief EXTI0 configuration
3471 */
3472 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
3473 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
3474 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
3475 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
3476 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
3477 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
3478 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006) /*!< PF[0] pin */
3479 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007) /*!< PG[0] pin */
3480
3481 /**
3482 * @brief EXTI1 configuration
3483 */
3484 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
3485 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
3486 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
3487 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
3488 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
3489 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
3490 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060) /*!< PF[1] pin */
3491 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070) /*!< PG[1] pin */
3492
3493 /**
3494 * @brief EXTI2 configuration
3495 */
3496 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
3497 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
3498 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
3499 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
3500 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
3501 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500) /*!< PH[2] pin */
3502 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600) /*!< PF[2] pin */
3503 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700) /*!< PG[2] pin */
3504
3505 /**
3506 * @brief EXTI3 configuration
3507 */
3508 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
3509 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
3510 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
3511 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
3512 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
3513 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000) /*!< PF[3] pin */
3514 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000) /*!< PG[3] pin */
3515
3516 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
3517 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
3518 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
3519 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
3520 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
3521
3522 /**
3523 * @brief EXTI4 configuration
3524 */
3525 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
3526 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
3527 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
3528 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
3529 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
3530 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006) /*!< PF[4] pin */
3531 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007) /*!< PG[4] pin */
3532
3533 /**
3534 * @brief EXTI5 configuration
3535 */
3536 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
3537 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
3538 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
3539 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
3540 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
3541 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060) /*!< PF[5] pin */
3542 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070) /*!< PG[5] pin */
3543
3544 /**
3545 * @brief EXTI6 configuration
3546 */
3547 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
3548 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
3549 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
3550 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
3551 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
3552 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600) /*!< PF[6] pin */
3553 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700) /*!< PG[6] pin */
3554
3555 /**
3556 * @brief EXTI7 configuration
3557 */
3558 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
3559 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
3560 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
3561 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
3562 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
3563 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000) /*!< PF[7] pin */
3564 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000) /*!< PG[7] pin */
3565
3566 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
3567 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
3568 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
3569 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
3570 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
3571
3572 /**
3573 * @brief EXTI8 configuration
3574 */
3575 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
3576 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
3577 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
3578 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
3579 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
3580 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006) /*!< PF[8] pin */
3581 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007) /*!< PG[8] pin */
3582
3583 /**
3584 * @brief EXTI9 configuration
3585 */
3586 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
3587 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
3588 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
3589 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
3590 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
3591 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060) /*!< PF[9] pin */
3592 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070) /*!< PG[9] pin */
3593
3594 /**
3595 * @brief EXTI10 configuration
3596 */
3597 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
3598 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
3599 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
3600 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
3601 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
3602 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600) /*!< PF[10] pin */
3603 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700) /*!< PG[10] pin */
3604
3605 /**
3606 * @brief EXTI11 configuration
3607 */
3608 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
3609 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
3610 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
3611 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
3612 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
3613 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000) /*!< PF[11] pin */
3614 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000) /*!< PG[11] pin */
3615
3616 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
3617 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
3618 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
3619 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
3620 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
3621
3622 /**
3623 * @brief EXTI12 configuration
3624 */
3625 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
3626 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
3627 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
3628 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
3629 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
3630 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006) /*!< PF[12] pin */
3631 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007) /*!< PG[12] pin */
3632
3633 /**
3634 * @brief EXTI13 configuration
3635 */
3636 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
3637 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
3638 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
3639 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
3640 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
3641 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060) /*!< PF[13] pin */
3642 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070) /*!< PG[13] pin */
3643
3644 /**
3645 * @brief EXTI14 configuration
3646 */
3647 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
3648 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
3649 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
3650 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
3651 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
3652 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600) /*!< PF[14] pin */
3653 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700) /*!< PG[14] pin */
3654
3655 /**
3656 * @brief EXTI15 configuration
3657 */
3658 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
3659 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
3660 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
3661 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
3662 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
3663 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000) /*!< PF[15] pin */
3664 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000) /*!< PG[15] pin */
3665
3666 /******************************************************************************/
3667 /* */
3668 /* Routing Interface (RI) */
3669 /* */
3670 /******************************************************************************/
3671
3672 /******************** Bit definition for RI_ICR register ********************/
3673 #define RI_ICR_IC1OS ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
3674 #define RI_ICR_IC1OS_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3675 #define RI_ICR_IC1OS_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3676 #define RI_ICR_IC1OS_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3677 #define RI_ICR_IC1OS_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3678
3679 #define RI_ICR_IC2OS ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
3680 #define RI_ICR_IC2OS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
3681 #define RI_ICR_IC2OS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
3682 #define RI_ICR_IC2OS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
3683 #define RI_ICR_IC2OS_3 ((uint32_t)0x00000080) /*!< Bit 3 */
3684
3685 #define RI_ICR_IC3OS ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
3686 #define RI_ICR_IC3OS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3687 #define RI_ICR_IC3OS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3688 #define RI_ICR_IC3OS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
3689 #define RI_ICR_IC3OS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
3690
3691 #define RI_ICR_IC4OS ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
3692 #define RI_ICR_IC4OS_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3693 #define RI_ICR_IC4OS_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3694 #define RI_ICR_IC4OS_2 ((uint32_t)0x00004000) /*!< Bit 2 */
3695 #define RI_ICR_IC4OS_3 ((uint32_t)0x00008000) /*!< Bit 3 */
3696
3697 #define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
3698 #define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3699 #define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3700
3701 #define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
3702 #define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
3703 #define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
3704 #define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
3705
3706 /******************** Bit definition for RI_ASCR1 register ********************/
3707 #define RI_ASCR1_CH ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
3708 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3709 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3710 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3711 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3712 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3713 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3714 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3715 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3716 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3717 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3718 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3719 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3720 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3721 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3722 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3723 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3724 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
3725 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
3726 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
3727 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
3728 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
3729 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
3730 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
3731 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
3732 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
3733 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
3734 #define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
3735 #define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
3736 #define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
3737 #define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
3738 #define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
3739
3740 /******************** Bit definition for RI_ASCR2 register ********************/
3741 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
3742 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
3743 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
3744 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
3745 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
3746 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
3747 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
3748 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
3749 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
3750 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
3751 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
3752 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
3753 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
3754 #define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
3755 #define RI_ASCR2_CH1b ((uint32_t)0x00020000) /*!< CH1b selection bit */
3756 #define RI_ASCR2_CH2b ((uint32_t)0x00040000) /*!< CH2b selection bit */
3757 #define RI_ASCR2_CH3b ((uint32_t)0x00080000) /*!< CH3b selection bit */
3758 #define RI_ASCR2_CH6b ((uint32_t)0x00100000) /*!< CH6b selection bit */
3759 #define RI_ASCR2_CH7b ((uint32_t)0x00200000) /*!< CH7b selection bit */
3760 #define RI_ASCR2_CH8b ((uint32_t)0x00400000) /*!< CH8b selection bit */
3761 #define RI_ASCR2_CH9b ((uint32_t)0x00800000) /*!< CH9b selection bit */
3762 #define RI_ASCR2_CH10b ((uint32_t)0x01000000) /*!< CH10b selection bit */
3763 #define RI_ASCR2_CH11b ((uint32_t)0x02000000) /*!< CH11b selection bit */
3764 #define RI_ASCR2_CH12b ((uint32_t)0x04000000) /*!< CH12b selection bit */
3765 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
3766 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
3767
3768 /******************** Bit definition for RI_HYSCR1 register ********************/
3769 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
3770 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3771 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3772 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3773 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3774 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3775 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3776 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3777 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3778 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3779 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3780 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3781 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3782 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3783 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3784 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3785 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3786
3787 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
3788 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3789 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3790 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3791 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3792 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3793 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
3794 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
3795 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
3796 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
3797 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
3798 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
3799 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
3800 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
3801 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
3802 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
3803 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
3804
3805 /******************** Bit definition for RI_HYSCR2 register ********************/
3806 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
3807 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3808 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3809 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3810 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3811 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3812 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3813 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3814 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3815 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3816 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3817 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3818 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3819 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3820 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3821 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3822 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3823
3824 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
3825 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3826 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3827 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3828 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3829 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3830 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
3831 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
3832 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
3833 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
3834 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
3835 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
3836 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
3837 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
3838 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
3839 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
3840 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
3841
3842 /******************** Bit definition for RI_HYSCR3 register ********************/
3843 #define RI_HYSCR3_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
3844 #define RI_HYSCR3_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3845 #define RI_HYSCR3_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3846 #define RI_HYSCR3_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3847 #define RI_HYSCR3_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3848 #define RI_HYSCR3_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3849 #define RI_HYSCR3_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3850 #define RI_HYSCR3_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3851 #define RI_HYSCR3_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3852 #define RI_HYSCR3_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3853 #define RI_HYSCR3_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3854 #define RI_HYSCR3_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3855 #define RI_HYSCR3_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3856 #define RI_HYSCR3_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3857 #define RI_HYSCR3_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3858 #define RI_HYSCR3_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3859 #define RI_HYSCR3_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3860 #define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
3861 #define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3862 #define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3863 #define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3864 #define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3865 #define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3866 #define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /*!< Bit 5 */
3867 #define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /*!< Bit 6 */
3868 #define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /*!< Bit 7 */
3869 #define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /*!< Bit 8 */
3870 #define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /*!< Bit 9 */
3871 #define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /*!< Bit 10 */
3872 #define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /*!< Bit 11 */
3873 #define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /*!< Bit 12 */
3874 #define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /*!< Bit 13 */
3875 #define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /*!< Bit 14 */
3876 #define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /*!< Bit 15 */
3877
3878 /******************** Bit definition for RI_HYSCR4 register ********************/
3879 #define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
3880 #define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3881 #define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3882 #define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3883 #define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3884 #define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3885 #define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3886 #define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3887 #define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3888 #define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3889 #define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3890 #define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3891 #define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3892 #define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3893 #define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3894 #define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3895 #define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3896
3897 /******************** Bit definition for RI_ASMR1 register ********************/
3898 #define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
3899 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3900 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3901 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3902 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3903 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3904 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3905 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3906 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3907 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3908 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3909 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3910 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3911 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3912 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3913 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3914 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3915
3916 /******************** Bit definition for RI_CMR1 register ********************/
3917 #define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
3918 #define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3919 #define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3920 #define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3921 #define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3922 #define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3923 #define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3924 #define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3925 #define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3926 #define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3927 #define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3928 #define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3929 #define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3930 #define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3931 #define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3932 #define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3933 #define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3934
3935 /******************** Bit definition for RI_CICR1 register ********************/
3936 #define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
3937 #define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3938 #define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3939 #define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3940 #define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3941 #define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3942 #define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3943 #define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3944 #define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3945 #define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3946 #define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3947 #define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3948 #define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3949 #define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3950 #define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3951 #define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3952 #define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3953
3954 /******************** Bit definition for RI_ASMR2 register ********************/
3955 #define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
3956 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3957 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3958 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3959 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3960 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3961 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3962 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3963 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3964 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3965 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3966 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3967 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3968 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3969 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3970 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3971 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3972
3973 /******************** Bit definition for RI_CMR2 register ********************/
3974 #define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
3975 #define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3976 #define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3977 #define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3978 #define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3979 #define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3980 #define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
3981 #define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
3982 #define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
3983 #define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
3984 #define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
3985 #define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
3986 #define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
3987 #define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
3988 #define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
3989 #define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
3990 #define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
3991
3992 /******************** Bit definition for RI_CICR2 register ********************/
3993 #define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
3994 #define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3995 #define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3996 #define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3997 #define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
3998 #define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
3999 #define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4000 #define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4001 #define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4002 #define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4003 #define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4004 #define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4005 #define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4006 #define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4007 #define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4008 #define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4009 #define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4010
4011 /******************** Bit definition for RI_ASMR3 register ********************/
4012 #define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
4013 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4014 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4015 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4016 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4017 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4018 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4019 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4020 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4021 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4022 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4023 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4024 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4025 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4026 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4027 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4028 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4029
4030 /******************** Bit definition for RI_CMR3 register ********************/
4031 #define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
4032 #define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4033 #define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4034 #define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4035 #define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4036 #define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4037 #define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4038 #define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4039 #define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4040 #define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4041 #define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4042 #define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4043 #define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4044 #define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4045 #define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4046 #define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4047 #define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4048
4049 /******************** Bit definition for RI_CICR3 register ********************/
4050 #define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
4051 #define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4052 #define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4053 #define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4054 #define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4055 #define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4056 #define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4057 #define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4058 #define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4059 #define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4060 #define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4061 #define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4062 #define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4063 #define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4064 #define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4065 #define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4066 #define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4067
4068 /******************** Bit definition for RI_ASMR4 register ********************/
4069 #define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
4070 #define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4071 #define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4072 #define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4073 #define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4074 #define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4075 #define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4076 #define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4077 #define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4078 #define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4079 #define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4080 #define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4081 #define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4082 #define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4083 #define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4084 #define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4085 #define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4086
4087 /******************** Bit definition for RI_CMR4 register ********************/
4088 #define RI_CMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
4089 #define RI_CMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4090 #define RI_CMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4091 #define RI_CMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4092 #define RI_CMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4093 #define RI_CMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4094 #define RI_CMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4095 #define RI_CMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4096 #define RI_CMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4097 #define RI_CMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4098 #define RI_CMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4099 #define RI_CMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4100 #define RI_CMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4101 #define RI_CMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4102 #define RI_CMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4103 #define RI_CMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4104 #define RI_CMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4105
4106 /******************** Bit definition for RI_CICR4 register ********************/
4107 #define RI_CICR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
4108 #define RI_CICR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4109 #define RI_CICR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4110 #define RI_CICR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4111 #define RI_CICR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4112 #define RI_CICR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4113 #define RI_CICR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4114 #define RI_CICR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4115 #define RI_CICR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4116 #define RI_CICR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4117 #define RI_CICR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4118 #define RI_CICR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4119 #define RI_CICR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4120 #define RI_CICR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4121 #define RI_CICR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4122 #define RI_CICR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4123 #define RI_CICR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4124
4125 /******************** Bit definition for RI_ASMR5 register ********************/
4126 #define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
4127 #define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4128 #define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4129 #define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4130 #define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4131 #define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4132 #define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4133 #define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4134 #define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4135 #define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4136 #define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4137 #define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4138 #define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4139 #define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4140 #define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4141 #define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4142 #define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4143
4144 /******************** Bit definition for RI_CMR5 register ********************/
4145 #define RI_CMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
4146 #define RI_CMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4147 #define RI_CMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4148 #define RI_CMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4149 #define RI_CMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4150 #define RI_CMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4151 #define RI_CMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4152 #define RI_CMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4153 #define RI_CMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4154 #define RI_CMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4155 #define RI_CMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4156 #define RI_CMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4157 #define RI_CMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4158 #define RI_CMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4159 #define RI_CMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4160 #define RI_CMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4161 #define RI_CMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4162
4163 /******************** Bit definition for RI_CICR5 register ********************/
4164 #define RI_CICR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
4165 #define RI_CICR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4166 #define RI_CICR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4167 #define RI_CICR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4168 #define RI_CICR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4169 #define RI_CICR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4170 #define RI_CICR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4171 #define RI_CICR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4172 #define RI_CICR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4173 #define RI_CICR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
4174 #define RI_CICR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
4175 #define RI_CICR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
4176 #define RI_CICR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
4177 #define RI_CICR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
4178 #define RI_CICR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
4179 #define RI_CICR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
4180 #define RI_CICR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
4181
4182 /******************************************************************************/
4183 /* */
4184 /* Timers (TIM) */
4185 /* */
4186 /******************************************************************************/
4187
4188 /******************* Bit definition for TIM_CR1 register ********************/
4189 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
4190 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
4191 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
4192 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
4193 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
4194
4195 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
4196 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
4197 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
4198
4199 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
4200
4201 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
4202 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4203 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4204
4205 /******************* Bit definition for TIM_CR2 register ********************/
4206 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
4207
4208 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
4209 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4210 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4211 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4212
4213 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
4214
4215 /******************* Bit definition for TIM_SMCR register *******************/
4216 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
4217 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4218 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4219 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4220
4221 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
4222
4223 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
4224 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4225 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4226 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4227
4228 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
4229
4230 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
4231 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4232 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4233 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4234 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4235
4236 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
4237 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4238 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4239
4240 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
4241 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
4242
4243 /******************* Bit definition for TIM_DIER register *******************/
4244 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
4245 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
4246 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
4247 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
4248 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
4249 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
4250 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
4251 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
4252 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
4253 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
4254 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
4255 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
4256 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
4257
4258 /******************** Bit definition for TIM_SR register ********************/
4259 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
4260 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
4261 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
4262 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
4263 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
4264 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
4265 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
4266 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
4267 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
4268 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
4269
4270 /******************* Bit definition for TIM_EGR register ********************/
4271 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
4272 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
4273 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
4274 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
4275 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
4276 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
4277
4278 /****************** Bit definition for TIM_CCMR1 register *******************/
4279 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4280 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4281 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4282
4283 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
4284 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
4285
4286 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4287 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4288 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4289 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4290
4291 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
4292
4293 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4294 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4295 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4296
4297 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
4298 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
4299
4300 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4301 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4302 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4303 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4304
4305 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
4306
4307 /*----------------------------------------------------------------------------*/
4308
4309 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4310 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4311 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4312
4313 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4314 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4315 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4316 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4317 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4318
4319 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4320 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4321 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4322
4323 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4324 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4325 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4326 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4327 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
4328
4329 /****************** Bit definition for TIM_CCMR2 register *******************/
4330 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4331 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4332 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4333
4334 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
4335 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
4336
4337 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4338 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4339 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4340 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4341
4342 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
4343
4344 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4345 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4346 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4347
4348 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
4349 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
4350
4351 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4352 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4353 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4354 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4355
4356 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
4357
4358 /*----------------------------------------------------------------------------*/
4359
4360 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4361 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4362 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4363
4364 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4365 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4366 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4367 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4368 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4369
4370 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4371 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4372 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4373
4374 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4375 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4376 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4377 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4378 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
4379
4380 /******************* Bit definition for TIM_CCER register *******************/
4381 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
4382 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
4383 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
4384 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
4385 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
4386 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
4387 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
4388 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
4389 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
4390 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
4391 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
4392 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
4393
4394 /******************* Bit definition for TIM_CNT register ********************/
4395 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
4396
4397 /******************* Bit definition for TIM_PSC register ********************/
4398 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
4399
4400 /******************* Bit definition for TIM_ARR register ********************/
4401 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
4402
4403 /******************* Bit definition for TIM_CCR1 register *******************/
4404 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
4405
4406 /******************* Bit definition for TIM_CCR2 register *******************/
4407 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
4408
4409 /******************* Bit definition for TIM_CCR3 register *******************/
4410 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
4411
4412 /******************* Bit definition for TIM_CCR4 register *******************/
4413 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
4414
4415 /******************* Bit definition for TIM_DCR register ********************/
4416 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
4417 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4418 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4419 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4420 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4421 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4422
4423 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
4424 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4425 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4426 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4427 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4428 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4429
4430 /******************* Bit definition for TIM_DMAR register *******************/
4431 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
4432
4433 /******************* Bit definition for TIM_OR register *********************/
4434 #define TIM_OR_TI1RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
4435 #define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4436 #define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4437
4438 #define TIM_OR_ETR_RMP ((uint32_t)0x00000004) /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
4439 #define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008) /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
4440
4441 /*----------------------------------------------------------------------------*/
4442 #define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004) /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
4443
4444 /*----------------------------------------------------------------------------*/
4445 #define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001) /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
4446
4447 /*----------------------------------------------------------------------------*/
4448 #define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001) /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
4449
4450 /*----------------------------------------------------------------------------*/
4451
4452
4453 /******************************************************************************/
4454 /* */
4455 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
4456 /* */
4457 /******************************************************************************/
4458
4459 /******************* Bit definition for USART_SR register *******************/
4460 #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
4461 #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
4462 #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
4463 #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
4464 #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
4465 #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
4466 #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
4467 #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
4468 #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
4469 #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
4470
4471 /******************* Bit definition for USART_DR register *******************/
4472 #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
4473
4474 /****************** Bit definition for USART_BRR register *******************/
4475 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
4476 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
4477
4478 /****************** Bit definition for USART_CR1 register *******************/
4479 #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
4480 #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
4481 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
4482 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
4483 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
4484 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
4485 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
4486 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
4487 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
4488 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
4489 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
4490 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
4491 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
4492 #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
4493 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit mode */
4494
4495 /****************** Bit definition for USART_CR2 register *******************/
4496 #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
4497 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
4498 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
4499 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
4500 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
4501 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
4502 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
4503
4504 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
4505 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
4506 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
4507
4508 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
4509
4510 /****************** Bit definition for USART_CR3 register *******************/
4511 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
4512 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
4513 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
4514 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
4515 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
4516 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
4517 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
4518 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
4519 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
4520 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
4521 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
4522 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
4523
4524 /****************** Bit definition for USART_GTPR register ******************/
4525 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
4526 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4527 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4528 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4529 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4530 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
4531 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
4532 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
4533 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
4534
4535 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
4536
4537 /******************************************************************************/
4538 /* */
4539 /* Universal Serial Bus (USB) */
4540 /* */
4541 /******************************************************************************/
4542
4543 /*!<Endpoint-specific registers */
4544
4545 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
4546 #define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
4547 #define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
4548 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
4549 #define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
4550 #define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
4551 #define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
4552 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
4553
4554 /* bit positions */
4555 #define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */
4556 #define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */
4557 #define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */
4558 #define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */
4559 #define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */
4560 #define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */
4561 #define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */
4562 #define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */
4563 #define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */
4564 #define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */
4565
4566 /* EndPoint REGister MASK (no toggle fields) */
4567 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
4568 /*!< EP_TYPE[1:0] EndPoint TYPE */
4569 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */
4570 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
4571 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
4572 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
4573 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
4574 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
4575
4576 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
4577 /*!< STAT_TX[1:0] STATus for TX transfer */
4578 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
4579 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
4580 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
4581 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
4582 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
4583 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
4584 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
4585 /*!< STAT_RX[1:0] STATus for RX transfer */
4586 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
4587 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
4588 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
4589 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
4590 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
4591 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
4592 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
4593
4594 /******************* Bit definition for USB_EP0R register *******************/
4595 #define USB_EP0R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4596
4597 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4598 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4599 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4600
4601 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4602 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4603 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4604
4605 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4606 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4607 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4608
4609 #define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4610
4611 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4612 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4613 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4614
4615 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4616 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4617
4618 /******************* Bit definition for USB_EP1R register *******************/
4619 #define USB_EP1R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4620
4621 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4622 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4623 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4624
4625 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4626 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4627 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4628
4629 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4630 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4631 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4632
4633 #define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4634
4635 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4636 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4637 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4638
4639 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4640 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4641
4642 /******************* Bit definition for USB_EP2R register *******************/
4643 #define USB_EP2R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4644
4645 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4646 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4647 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4648
4649 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4650 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4651 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4652
4653 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4654 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4655 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4656
4657 #define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4658
4659 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4660 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4661 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4662
4663 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4664 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4665
4666 /******************* Bit definition for USB_EP3R register *******************/
4667 #define USB_EP3R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4668
4669 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4670 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4671 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4672
4673 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4674 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4675 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4676
4677 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4678 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4679 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4680
4681 #define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4682
4683 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4684 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4685 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4686
4687 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4688 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4689
4690 /******************* Bit definition for USB_EP4R register *******************/
4691 #define USB_EP4R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4692
4693 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4694 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4695 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4696
4697 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4698 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4699 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4700
4701 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4702 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4703 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4704
4705 #define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4706
4707 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4708 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4709 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4710
4711 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4712 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4713
4714 /******************* Bit definition for USB_EP5R register *******************/
4715 #define USB_EP5R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4716
4717 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4718 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4719 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4720
4721 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4722 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4723 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4724
4725 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4726 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4727 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4728
4729 #define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4730
4731 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4732 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4733 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4734
4735 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4736 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4737
4738 /******************* Bit definition for USB_EP6R register *******************/
4739 #define USB_EP6R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4740
4741 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4742 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4743 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4744
4745 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4746 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4747 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4748
4749 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4750 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4751 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4752
4753 #define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4754
4755 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4756 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4757 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4758
4759 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4760 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4761
4762 /******************* Bit definition for USB_EP7R register *******************/
4763 #define USB_EP7R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
4764
4765 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4766 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4767 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4768
4769 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
4770 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
4771 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
4772
4773 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
4774 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4775 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4776
4777 #define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
4778
4779 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
4780 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4781 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4782
4783 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
4784 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
4785
4786 /*!<Common registers */
4787
4788 #define USB_CNTR (USB_BASE + 0x00000040) /*!< Control register */
4789 #define USB_ISTR (USB_BASE + 0x00000044) /*!< Interrupt status register */
4790 #define USB_FNR (USB_BASE + 0x00000048) /*!< Frame number register */
4791 #define USB_DADDR (USB_BASE + 0x0000004C) /*!< Device address register */
4792 #define USB_BTABLE (USB_BASE + 0x00000050) /*!< Buffer Table address register */
4793
4794
4795
4796 /******************* Bit definition for USB_CNTR register *******************/
4797 #define USB_CNTR_FRES ((uint32_t)0x00000001) /*!<Force USB Reset */
4798 #define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!<Power down */
4799 #define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!<Low-power mode */
4800 #define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!<Force suspend */
4801 #define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!<Resume request */
4802 #define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!<Expected Start Of Frame Interrupt Mask */
4803 #define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!<Start Of Frame Interrupt Mask */
4804 #define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!<RESET Interrupt Mask */
4805 #define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!<Suspend mode Interrupt Mask */
4806 #define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!<Wakeup Interrupt Mask */
4807 #define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!<Error Interrupt Mask */
4808 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
4809 #define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!<Correct Transfer Interrupt Mask */
4810
4811 /******************* Bit definition for USB_ISTR register *******************/
4812 #define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!<Endpoint Identifier */
4813 #define USB_ISTR_DIR ((uint32_t)0x00000010) /*!<Direction of transaction */
4814 #define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!<Expected Start Of Frame */
4815 #define USB_ISTR_SOF ((uint32_t)0x00000200) /*!<Start Of Frame */
4816 #define USB_ISTR_RESET ((uint32_t)0x00000400) /*!<USB RESET request */
4817 #define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!<Suspend mode request */
4818 #define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!<Wake up */
4819 #define USB_ISTR_ERR ((uint32_t)0x00002000) /*!<Error */
4820 #define USB_ISTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun */
4821 #define USB_ISTR_CTR ((uint32_t)0x00008000) /*!<Correct Transfer */
4822
4823 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
4824 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
4825 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
4826 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
4827 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
4828 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
4829 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
4830 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
4831
4832
4833 /******************* Bit definition for USB_FNR register ********************/
4834 #define USB_FNR_FN ((uint32_t)0x000007FF) /*!<Frame Number */
4835 #define USB_FNR_LSOF ((uint32_t)0x00001800) /*!<Lost SOF */
4836 #define USB_FNR_LCK ((uint32_t)0x00002000) /*!<Locked */
4837 #define USB_FNR_RXDM ((uint32_t)0x00004000) /*!<Receive Data - Line Status */
4838 #define USB_FNR_RXDP ((uint32_t)0x00008000) /*!<Receive Data + Line Status */
4839
4840 /****************** Bit definition for USB_DADDR register *******************/
4841 #define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!<ADD[6:0] bits (Device Address) */
4842 #define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
4843 #define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
4844 #define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
4845 #define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
4846 #define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
4847 #define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
4848 #define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
4849
4850 #define USB_DADDR_EF ((uint32_t)0x00000080) /*!<Enable Function */
4851
4852 /****************** Bit definition for USB_BTABLE register ******************/
4853 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!<Buffer Table */
4854
4855 /*!< Buffer descriptor table */
4856 /***************** Bit definition for USB_ADDR0_TX register *****************/
4857 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */
4858
4859 /***************** Bit definition for USB_ADDR1_TX register *****************/
4860 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */
4861
4862 /***************** Bit definition for USB_ADDR2_TX register *****************/
4863 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */
4864
4865 /***************** Bit definition for USB_ADDR3_TX register *****************/
4866 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */
4867
4868 /***************** Bit definition for USB_ADDR4_TX register *****************/
4869 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */
4870
4871 /***************** Bit definition for USB_ADDR5_TX register *****************/
4872 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */
4873
4874 /***************** Bit definition for USB_ADDR6_TX register *****************/
4875 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */
4876
4877 /***************** Bit definition for USB_ADDR7_TX register *****************/
4878 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */
4879
4880 /*----------------------------------------------------------------------------*/
4881
4882 /***************** Bit definition for USB_COUNT0_TX register ****************/
4883 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */
4884
4885 /***************** Bit definition for USB_COUNT1_TX register ****************/
4886 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */
4887
4888 /***************** Bit definition for USB_COUNT2_TX register ****************/
4889 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */
4890
4891 /***************** Bit definition for USB_COUNT3_TX register ****************/
4892 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */
4893
4894 /***************** Bit definition for USB_COUNT4_TX register ****************/
4895 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */
4896
4897 /***************** Bit definition for USB_COUNT5_TX register ****************/
4898 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */
4899
4900 /***************** Bit definition for USB_COUNT6_TX register ****************/
4901 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */
4902
4903 /***************** Bit definition for USB_COUNT7_TX register ****************/
4904 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */
4905
4906 /*----------------------------------------------------------------------------*/
4907
4908 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
4909 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
4910
4911 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
4912 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
4913
4914 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
4915 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
4916
4917 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
4918 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
4919
4920 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
4921 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
4922
4923 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
4924 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
4925
4926 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
4927 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x0000000003FF) /*!< Transmission Byte Count 3 (low) */
4928
4929 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
4930 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FF0000) /*!< Transmission Byte Count 3 (high) */
4931
4932 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
4933 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
4934
4935 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
4936 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
4937
4938 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
4939 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
4940
4941 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
4942 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
4943
4944 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
4945 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
4946
4947 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
4948 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
4949
4950 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
4951 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
4952
4953 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
4954 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
4955
4956 /*----------------------------------------------------------------------------*/
4957
4958 /***************** Bit definition for USB_ADDR0_RX register *****************/
4959 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */
4960
4961 /***************** Bit definition for USB_ADDR1_RX register *****************/
4962 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */
4963
4964 /***************** Bit definition for USB_ADDR2_RX register *****************/
4965 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */
4966
4967 /***************** Bit definition for USB_ADDR3_RX register *****************/
4968 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */
4969
4970 /***************** Bit definition for USB_ADDR4_RX register *****************/
4971 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */
4972
4973 /***************** Bit definition for USB_ADDR5_RX register *****************/
4974 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */
4975
4976 /***************** Bit definition for USB_ADDR6_RX register *****************/
4977 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */
4978
4979 /***************** Bit definition for USB_ADDR7_RX register *****************/
4980 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */
4981
4982 /*----------------------------------------------------------------------------*/
4983
4984 /***************** Bit definition for USB_COUNT0_RX register ****************/
4985 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4986
4987 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
4988 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4989 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4990 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4991 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
4992 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
4993
4994 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
4995
4996 /***************** Bit definition for USB_COUNT1_RX register ****************/
4997 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
4998
4999 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5000 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5001 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5002 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5003 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5004 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5005
5006 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5007
5008 /***************** Bit definition for USB_COUNT2_RX register ****************/
5009 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
5010
5011 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5012 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5013 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5014 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5015 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5016 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5017
5018 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5019
5020 /***************** Bit definition for USB_COUNT3_RX register ****************/
5021 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
5022
5023 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5024 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5025 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5026 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5027 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5028 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5029
5030 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5031
5032 /***************** Bit definition for USB_COUNT4_RX register ****************/
5033 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
5034
5035 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5036 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5037 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5038 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5039 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5040 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5041
5042 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5043
5044 /***************** Bit definition for USB_COUNT5_RX register ****************/
5045 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
5046
5047 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5048 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5049 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5050 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5051 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5052 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5053
5054 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5055
5056 /***************** Bit definition for USB_COUNT6_RX register ****************/
5057 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
5058
5059 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5060 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5061 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5062 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5063 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5064 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5065
5066 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5067
5068 /***************** Bit definition for USB_COUNT7_RX register ****************/
5069 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
5070
5071 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5072 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5073 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5074 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5075 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5076 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5077
5078 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
5079
5080 /*----------------------------------------------------------------------------*/
5081
5082 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
5083 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5084
5085 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5086 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5087 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5088 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5089 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5090 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5091
5092 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5093
5094 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
5095 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5096
5097 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5098 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
5099 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5100 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5101 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5102 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5103
5104 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5105
5106 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
5107 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5108
5109 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5110 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5111 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5112 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5113 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5114 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5115
5116 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5117
5118 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
5119 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5120
5121 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5122 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5123 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5124 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5125 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5126 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5127
5128 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5129
5130 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
5131 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5132
5133 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5134 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5135 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5136 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5137 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5138 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5139
5140 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5141
5142 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
5143 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5144
5145 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5146 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5147 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5148 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5149 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5150 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5151
5152 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5153
5154 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
5155 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5156
5157 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5158 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5159 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5160 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5161 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5162 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5163
5164 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5165
5166 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
5167 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5168
5169 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5170 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5171 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5172 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5173 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5174 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5175
5176 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5177
5178 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
5179 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5180
5181 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5182 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5183 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5184 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5185 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5186 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5187
5188 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5189
5190 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
5191 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5192
5193 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5194 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5195 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5196 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5197 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5198 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5199
5200 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5201
5202 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
5203 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5204
5205 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5206 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5207 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5208 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5209 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5210 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5211
5212 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5213
5214 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
5215 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5216
5217 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5218 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5219 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5220 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5221 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5222 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5223
5224 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5225
5226 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
5227 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5228
5229 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5230 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5231 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5232 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5233 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5234 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5235
5236 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5237
5238 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
5239 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5240
5241 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5242 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5243 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5244 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5245 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5246 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5247
5248 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5249
5250 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
5251 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
5252
5253 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5254 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5255 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5256 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5257 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
5258 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
5259
5260 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
5261
5262 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
5263 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
5264
5265 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5266 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5267 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5268 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
5269 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
5270 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
5271
5272 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
5273
5274 /******************************************************************************/
5275 /* */
5276 /* Window WATCHDOG (WWDG) */
5277 /* */
5278 /******************************************************************************/
5279
5280 /******************* Bit definition for WWDG_CR register ********************/
5281 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
5282 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
5283 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
5284 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
5285 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
5286 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
5287 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
5288 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
5289
5290 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
5291
5292 /******************* Bit definition for WWDG_CFR register *******************/
5293 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
5294 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
5295 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
5296 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
5297 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
5298 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
5299 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
5300 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
5301
5302 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
5303 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
5304 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
5305
5306 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
5307
5308 /******************* Bit definition for WWDG_SR register ********************/
5309 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
5310
5311 /******************************************************************************/
5312 /* */
5313 /* SystemTick (SysTick) */
5314 /* */
5315 /******************************************************************************/
5316
5317 /***************** Bit definition for SysTick_CTRL register *****************/
5318 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
5319 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
5320 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
5321 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
5322
5323 /***************** Bit definition for SysTick_LOAD register *****************/
5324 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
5325
5326 /***************** Bit definition for SysTick_VAL register ******************/
5327 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
5328
5329 /***************** Bit definition for SysTick_CALIB register ****************/
5330 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
5331 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
5332 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
5333
5334 /******************************************************************************/
5335 /* */
5336 /* Nested Vectored Interrupt Controller (NVIC) */
5337 /* */
5338 /******************************************************************************/
5339
5340 /****************** Bit definition for NVIC_ISER register *******************/
5341 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
5342 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
5343 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
5344 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
5345 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
5346 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
5347 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
5348 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
5349 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
5350 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
5351 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
5352 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
5353 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
5354 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
5355 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
5356 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
5357 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
5358 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
5359 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
5360 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
5361 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
5362 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
5363 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
5364 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
5365 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
5366 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
5367 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
5368 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
5369 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
5370 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
5371 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
5372 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
5373 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
5374
5375 /****************** Bit definition for NVIC_ICER register *******************/
5376 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
5377 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
5378 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
5379 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
5380 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
5381 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
5382 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
5383 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
5384 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
5385 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
5386 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
5387 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
5388 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
5389 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
5390 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
5391 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
5392 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
5393 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
5394 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
5395 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
5396 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
5397 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
5398 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
5399 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
5400 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
5401 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
5402 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
5403 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
5404 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
5405 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
5406 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
5407 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
5408 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
5409
5410 /****************** Bit definition for NVIC_ISPR register *******************/
5411 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
5412 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
5413 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
5414 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
5415 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
5416 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
5417 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
5418 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
5419 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
5420 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
5421 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
5422 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
5423 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
5424 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
5425 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
5426 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
5427 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
5428 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
5429 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
5430 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
5431 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
5432 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
5433 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
5434 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
5435 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
5436 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
5437 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
5438 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
5439 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
5440 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
5441 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
5442 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
5443 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
5444
5445 /****************** Bit definition for NVIC_ICPR register *******************/
5446 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
5447 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
5448 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
5449 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
5450 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
5451 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
5452 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
5453 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
5454 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
5455 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
5456 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
5457 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
5458 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
5459 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
5460 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
5461 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
5462 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
5463 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
5464 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
5465 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
5466 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
5467 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
5468 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
5469 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
5470 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
5471 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
5472 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
5473 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
5474 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
5475 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
5476 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
5477 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
5478 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
5479
5480 /****************** Bit definition for NVIC_IABR register *******************/
5481 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
5482 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
5483 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
5484 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
5485 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
5486 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
5487 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
5488 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
5489 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
5490 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
5491 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
5492 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
5493 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
5494 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
5495 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
5496 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
5497 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
5498 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
5499 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
5500 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
5501 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
5502 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
5503 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
5504 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
5505 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
5506 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
5507 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
5508 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
5509 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
5510 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
5511 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
5512 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
5513 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
5514
5515 /****************** Bit definition for NVIC_PRI0 register *******************/
5516 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
5517 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
5518 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
5519 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
5520
5521 /****************** Bit definition for NVIC_PRI1 register *******************/
5522 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
5523 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
5524 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
5525 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
5526
5527 /****************** Bit definition for NVIC_PRI2 register *******************/
5528 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
5529 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
5530 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
5531 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
5532
5533 /****************** Bit definition for NVIC_PRI3 register *******************/
5534 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
5535 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
5536 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
5537 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
5538
5539 /****************** Bit definition for NVIC_PRI4 register *******************/
5540 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
5541 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
5542 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
5543 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
5544
5545 /****************** Bit definition for NVIC_PRI5 register *******************/
5546 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
5547 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
5548 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
5549 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
5550
5551 /****************** Bit definition for NVIC_PRI6 register *******************/
5552 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
5553 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
5554 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
5555 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
5556
5557 /****************** Bit definition for NVIC_PRI7 register *******************/
5558 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
5559 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
5560 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
5561 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
5562
5563 /****************** Bit definition for SCB_CPUID register *******************/
5564 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
5565 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
5566 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
5567 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
5568 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
5569
5570 /******************* Bit definition for SCB_ICSR register *******************/
5571 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
5572 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
5573 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
5574 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
5575 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
5576 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
5577 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
5578 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
5579 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
5580 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
5581
5582 /******************* Bit definition for SCB_VTOR register *******************/
5583 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
5584 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
5585
5586 /*!<***************** Bit definition for SCB_AIRCR register *******************/
5587 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
5588 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
5589 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
5590
5591 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
5592 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5593 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5594 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5595
5596 /* prority group configuration */
5597 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
5598 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
5599 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
5600 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
5601 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
5602 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
5603 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
5604 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
5605
5606 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
5607 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
5608
5609 /******************* Bit definition for SCB_SCR register ********************/
5610 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
5611 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
5612 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
5613
5614 /******************** Bit definition for SCB_CCR register *******************/
5615 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
5616 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
5617 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
5618 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
5619 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
5620 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
5621
5622 /******************* Bit definition for SCB_SHPR register ********************/
5623 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
5624 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
5625 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
5626 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
5627
5628 /****************** Bit definition for SCB_SHCSR register *******************/
5629 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
5630 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
5631 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
5632 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
5633 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
5634 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
5635 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
5636 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
5637 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
5638 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
5639 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
5640 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
5641 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
5642 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
5643
5644 /******************* Bit definition for SCB_CFSR register *******************/
5645 /*!< MFSR */
5646 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
5647 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
5648 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
5649 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
5650 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
5651 /*!< BFSR */
5652 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
5653 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
5654 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
5655 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
5656 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
5657 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
5658 /*!< UFSR */
5659 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
5660 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
5661 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
5662 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
5663 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
5664 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
5665
5666 /******************* Bit definition for SCB_HFSR register *******************/
5667 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
5668 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
5669 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
5670
5671 /******************* Bit definition for SCB_DFSR register *******************/
5672 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
5673 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
5674 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
5675 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
5676 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
5677
5678 /******************* Bit definition for SCB_MMFAR register ******************/
5679 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
5680
5681 /******************* Bit definition for SCB_BFAR register *******************/
5682 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
5683
5684 /******************* Bit definition for SCB_afsr register *******************/
5685 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
5686 /**
5687 * @}
5688 */
5689
5690 /**
5691 * @}
5692 */
5693 /** @addtogroup Exported_macro
5694 * @{
5695 */
5696
5697 /****************************** ADC Instances *********************************/
5698 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
5699
5700 /******************************** COMP Instances ******************************/
5701 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
5702 ((INSTANCE) == COMP2))
5703
5704 /****************************** CRC Instances *********************************/
5705 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5706
5707 /****************************** DAC Instances *********************************/
5708 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
5709
5710 /****************************** DMA Instances *********************************/
5711 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
5712 ((INSTANCE) == DMA1_Channel2) || \
5713 ((INSTANCE) == DMA1_Channel3) || \
5714 ((INSTANCE) == DMA1_Channel4) || \
5715 ((INSTANCE) == DMA1_Channel5) || \
5716 ((INSTANCE) == DMA1_Channel6) || \
5717 ((INSTANCE) == DMA1_Channel7) || \
5718 ((INSTANCE) == DMA2_Channel1) || \
5719 ((INSTANCE) == DMA2_Channel2) || \
5720 ((INSTANCE) == DMA2_Channel3) || \
5721 ((INSTANCE) == DMA2_Channel4) || \
5722 ((INSTANCE) == DMA2_Channel5))
5723
5724 /******************************* GPIO Instances *******************************/
5725 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5726 ((INSTANCE) == GPIOB) || \
5727 ((INSTANCE) == GPIOC) || \
5728 ((INSTANCE) == GPIOD) || \
5729 ((INSTANCE) == GPIOE) || \
5730 ((INSTANCE) == GPIOF) || \
5731 ((INSTANCE) == GPIOG) || \
5732 ((INSTANCE) == GPIOH))
5733
5734 /**************************** GPIO Lock Instances *****************************/
5735 /* On L1, all GPIO Bank support the Lock mechanism */
5736 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
5737
5738 /******************************** I2C Instances *******************************/
5739 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
5740 ((INSTANCE) == I2C2))
5741
5742 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5743 ((INSTANCE) == SPI2) || \
5744 ((INSTANCE) == SPI3))
5745 /****************************** IWDG Instances ********************************/
5746 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
5747
5748 /****************************** OPAMP Instances *******************************/
5749 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
5750 ((INSTANCE) == OPAMP2))
5751
5752 /****************************** RTC Instances *********************************/
5753 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
5754
5755 /******************************** SPI Instances *******************************/
5756 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5757 ((INSTANCE) == SPI2) || \
5758 ((INSTANCE) == SPI3))
5759
5760 /****************************** TIM Instances *********************************/
5761 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5762 ((INSTANCE) == TIM3) || \
5763 ((INSTANCE) == TIM4) || \
5764 ((INSTANCE) == TIM5) || \
5765 ((INSTANCE) == TIM6) || \
5766 ((INSTANCE) == TIM7) || \
5767 ((INSTANCE) == TIM9) || \
5768 ((INSTANCE) == TIM10) || \
5769 ((INSTANCE) == TIM11))
5770
5771 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5772 ((INSTANCE) == TIM3) || \
5773 ((INSTANCE) == TIM4) || \
5774 ((INSTANCE) == TIM5) || \
5775 ((INSTANCE) == TIM9) || \
5776 ((INSTANCE) == TIM10) || \
5777 ((INSTANCE) == TIM11))
5778
5779 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5780 ((INSTANCE) == TIM3) || \
5781 ((INSTANCE) == TIM4) || \
5782 ((INSTANCE) == TIM5) || \
5783 ((INSTANCE) == TIM9))
5784
5785 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5786 ((INSTANCE) == TIM3) || \
5787 ((INSTANCE) == TIM4) || \
5788 ((INSTANCE) == TIM5))
5789
5790 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5791 ((INSTANCE) == TIM3) || \
5792 ((INSTANCE) == TIM4) || \
5793 ((INSTANCE) == TIM5))
5794
5795 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5796 ((INSTANCE) == TIM3) || \
5797 ((INSTANCE) == TIM4) || \
5798 ((INSTANCE) == TIM5) || \
5799 ((INSTANCE) == TIM9))
5800
5801 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5802 ((INSTANCE) == TIM3) || \
5803 ((INSTANCE) == TIM4) || \
5804 ((INSTANCE) == TIM5) || \
5805 ((INSTANCE) == TIM9) || \
5806 ((INSTANCE) == TIM10) || \
5807 ((INSTANCE) == TIM11))
5808
5809 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5810 ((INSTANCE) == TIM3) || \
5811 ((INSTANCE) == TIM4) || \
5812 ((INSTANCE) == TIM5) || \
5813 ((INSTANCE) == TIM9))
5814
5815 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5816 ((INSTANCE) == TIM3) || \
5817 ((INSTANCE) == TIM4) || \
5818 ((INSTANCE) == TIM5) || \
5819 ((INSTANCE) == TIM9))
5820
5821 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5822 ((INSTANCE) == TIM3) || \
5823 ((INSTANCE) == TIM4))
5824
5825 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5826 ((INSTANCE) == TIM3) || \
5827 ((INSTANCE) == TIM4) || \
5828 ((INSTANCE) == TIM5))
5829
5830 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5831 ((INSTANCE) == TIM3) || \
5832 ((INSTANCE) == TIM4) || \
5833 ((INSTANCE) == TIM5) || \
5834 ((INSTANCE) == TIM6) || \
5835 ((INSTANCE) == TIM7) || \
5836 ((INSTANCE) == TIM9))
5837
5838 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5839 ((INSTANCE) == TIM3) || \
5840 ((INSTANCE) == TIM4) || \
5841 ((INSTANCE) == TIM5) || \
5842 ((INSTANCE) == TIM9))
5843
5844 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
5845
5846 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5847 ((INSTANCE) == TIM3) || \
5848 ((INSTANCE) == TIM4) || \
5849 ((INSTANCE) == TIM5))
5850
5851 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
5852 ((((INSTANCE) == TIM2) && \
5853 (((CHANNEL) == TIM_CHANNEL_1) || \
5854 ((CHANNEL) == TIM_CHANNEL_2) || \
5855 ((CHANNEL) == TIM_CHANNEL_3) || \
5856 ((CHANNEL) == TIM_CHANNEL_4))) \
5857 || \
5858 (((INSTANCE) == TIM3) && \
5859 (((CHANNEL) == TIM_CHANNEL_1) || \
5860 ((CHANNEL) == TIM_CHANNEL_2) || \
5861 ((CHANNEL) == TIM_CHANNEL_3) || \
5862 ((CHANNEL) == TIM_CHANNEL_4))) \
5863 || \
5864 (((INSTANCE) == TIM4) && \
5865 (((CHANNEL) == TIM_CHANNEL_1) || \
5866 ((CHANNEL) == TIM_CHANNEL_2) || \
5867 ((CHANNEL) == TIM_CHANNEL_3) || \
5868 ((CHANNEL) == TIM_CHANNEL_4))) \
5869 || \
5870 (((INSTANCE) == TIM5) && \
5871 (((CHANNEL) == TIM_CHANNEL_1) || \
5872 ((CHANNEL) == TIM_CHANNEL_2) || \
5873 ((CHANNEL) == TIM_CHANNEL_3) || \
5874 ((CHANNEL) == TIM_CHANNEL_4))) \
5875 || \
5876 (((INSTANCE) == TIM9) && \
5877 (((CHANNEL) == TIM_CHANNEL_1) || \
5878 ((CHANNEL) == TIM_CHANNEL_2))) \
5879 || \
5880 (((INSTANCE) == TIM10) && \
5881 (((CHANNEL) == TIM_CHANNEL_1))) \
5882 || \
5883 (((INSTANCE) == TIM11) && \
5884 (((CHANNEL) == TIM_CHANNEL_1))))
5885
5886 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5887 ((INSTANCE) == TIM3) || \
5888 ((INSTANCE) == TIM4) || \
5889 ((INSTANCE) == TIM5) || \
5890 ((INSTANCE) == TIM9) || \
5891 ((INSTANCE) == TIM10) || \
5892 ((INSTANCE) == TIM11))
5893
5894 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5895 ((INSTANCE) == TIM3) || \
5896 ((INSTANCE) == TIM4) || \
5897 ((INSTANCE) == TIM5) || \
5898 ((INSTANCE) == TIM6) || \
5899 ((INSTANCE) == TIM7))
5900
5901 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5902 ((INSTANCE) == TIM3) || \
5903 ((INSTANCE) == TIM4) || \
5904 ((INSTANCE) == TIM5))
5905
5906 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5907 ((INSTANCE) == TIM3) || \
5908 ((INSTANCE) == TIM4) || \
5909 ((INSTANCE) == TIM5) || \
5910 ((INSTANCE) == TIM9))
5911
5912 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5913 ((INSTANCE) == TIM3) || \
5914 ((INSTANCE) == TIM4) || \
5915 ((INSTANCE) == TIM5) || \
5916 ((INSTANCE) == TIM9))
5917
5918 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5919 ((INSTANCE) == TIM3) || \
5920 ((INSTANCE) == TIM9) || \
5921 ((INSTANCE) == TIM10) || \
5922 ((INSTANCE) == TIM11))
5923
5924 /******************** USART Instances : Synchronous mode **********************/
5925 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5926 ((INSTANCE) == USART2) || \
5927 ((INSTANCE) == USART3))
5928
5929 /******************** UART Instances : Asynchronous mode **********************/
5930 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5931 ((INSTANCE) == USART2) || \
5932 ((INSTANCE) == USART3) || \
5933 ((INSTANCE) == UART4) || \
5934 ((INSTANCE) == UART5))
5935
5936 /******************** UART Instances : Half-Duplex mode **********************/
5937 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5938 ((INSTANCE) == USART2) || \
5939 ((INSTANCE) == USART3) || \
5940 ((INSTANCE) == UART4) || \
5941 ((INSTANCE) == UART5))
5942
5943 /******************** UART Instances : LIN mode **********************/
5944 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5945 ((INSTANCE) == USART2) || \
5946 ((INSTANCE) == USART3) || \
5947 ((INSTANCE) == UART4) || \
5948 ((INSTANCE) == UART5))
5949
5950 /****************** UART Instances : Hardware Flow control ********************/
5951 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5952 ((INSTANCE) == USART2) || \
5953 ((INSTANCE) == USART3))
5954
5955 /********************* UART Instances : Smard card mode ***********************/
5956 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5957 ((INSTANCE) == USART2) || \
5958 ((INSTANCE) == USART3))
5959
5960 /*********************** UART Instances : IRDA mode ***************************/
5961 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5962 ((INSTANCE) == USART2) || \
5963 ((INSTANCE) == USART3) || \
5964 ((INSTANCE) == UART4) || \
5965 ((INSTANCE) == UART5))
5966
5967 /***************** UART Instances : Multi-Processor mode **********************/
5968 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5969 ((INSTANCE) == USART2) || \
5970 ((INSTANCE) == USART3) || \
5971 ((INSTANCE) == UART4) || \
5972 ((INSTANCE) == UART5))
5973
5974 /****************************** WWDG Instances ********************************/
5975 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
5976
5977
5978 /****************************** LCD Instances ********************************/
5979 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
5980
5981 /****************************** USB Instances ********************************/
5982 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
5983
5984 /**
5985 * @}
5986 */
5987
5988 /******************************************************************************/
5989 /* For a painless codes migration between the STM32L1xx device product */
5990 /* lines, the aliases defined below are put in place to overcome the */
5991 /* differences in the interrupt handlers and IRQn definitions. */
5992 /* No need to update developed interrupt code when moving across */
5993 /* product lines within the same STM32L1 Family */
5994 /******************************************************************************/
5995
5996 /* Aliases for __IRQn */
5997
5998 /* Aliases for __IRQHandler */
5999
6000 /**
6001 * @}
6002 */
6003
6004 /**
6005 * @}
6006 */
6007
6008 #ifdef __cplusplus
6009 }
6010 #endif /* __cplusplus */
6011
6012 #endif /* __STM32L152xE_H */
6013
6014
6015
6016 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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