tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_SMC_REGISTERS_H__
  78 #define __HW_SMC_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 SMC
  85  *
  86  * System Mode Controller
  87  *
  88  * Registers defined in this header file:
  89  * - HW_SMC_PMPROT - Power Mode Protection register
  90  * - HW_SMC_PMCTRL - Power Mode Control register
  91  * - HW_SMC_STOPCTRL - Stop Control Register
  92  * - HW_SMC_PMSTAT - Power Mode Status register
  93  *
  94  * - hw_smc_t - Struct containing all module registers.
  95  */
  96
  97 #define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
  98
  99 /*******************************************************************************
 100  * HW_SMC_PMPROT - Power Mode Protection register
 101  ******************************************************************************/
 102
 103 /*!
 104  * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
 105  *
 106  * Reset value: 0x00U
 107  *
 108  * This register provides protection for entry into any low-power run or stop
 109  * mode. The enabling of the low-power run or stop mode occurs by configuring the
 110  * Power Mode Control register (PMCTRL). The PMPROT register can be written only
 111  * once after any system reset. If the MCU is configured for a disallowed or
 112  * reserved power mode, the MCU remains in its current power mode. For example, if the
 113  * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
 114  * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
 115  * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
 116  * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
 117  * that do not trigger Chip Reset not VLLS. See the Reset section details for more
 118  * information.
 119  */
 120 typedef union _hw_smc_pmprot
 121 {
 122     uint8_t U;
 123     struct _hw_smc_pmprot_bitfields
 124     {
 125         uint8_t RESERVED0 : 1;         /*!< [0]  */
 126         uint8_t AVLLS : 1;             /*!< [1] Allow Very-Low-Leakage Stop Mode */
 127         uint8_t RESERVED1 : 1;         /*!< [2]  */
 128         uint8_t ALLS : 1;              /*!< [3] Allow Low-Leakage Stop Mode */
 129         uint8_t RESERVED2 : 1;         /*!< [4]  */
 130         uint8_t AVLP : 1;              /*!< [5] Allow Very-Low-Power Modes */
 131         uint8_t RESERVED3 : 1;         /*!< [6]  */
 132         uint8_t AHSRUN : 1;            /*!< [7] Allow High Speed Run mode */
 133     } B;
 134 } hw_smc_pmprot_t;
 135
 136 /*!
 137  * @name Constants and macros for entire SMC_PMPROT register
 138  */
 139 /*@{*/
 140 #define HW_SMC_PMPROT_ADDR(x)    ((x) + 0x0U)
 141
 142 #define HW_SMC_PMPROT(x)         (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x))
 143 #define HW_SMC_PMPROT_RD(x)      (HW_SMC_PMPROT(x).U)
 144 #define HW_SMC_PMPROT_WR(x, v)   (HW_SMC_PMPROT(x).U = (v))
 145 #define HW_SMC_PMPROT_SET(x, v)  (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) |  (v)))
 146 #define HW_SMC_PMPROT_CLR(x, v)  (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v)))
 147 #define HW_SMC_PMPROT_TOG(x, v)  (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^  (v)))
 148 /*@}*/
 149
 150 /*
 151  * Constants & macros for individual SMC_PMPROT bitfields
 152  */
 153
 154 /*!
 155  * @name Register SMC_PMPROT, field AVLLS[1] (RW)
 156  *
 157  * Provided the appropriate control bits are set up in PMCTRL, this write once
 158  * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
 159  *
 160  * Values:
 161  * - 0 - Any VLLSx mode is not allowed
 162  * - 1 - Any VLLSx mode is allowed
 163  */
 164 /*@{*/
 165 #define BP_SMC_PMPROT_AVLLS  (1U)          /*!< Bit position for SMC_PMPROT_AVLLS. */
 166 #define BM_SMC_PMPROT_AVLLS  (0x02U)       /*!< Bit mask for SMC_PMPROT_AVLLS. */
 167 #define BS_SMC_PMPROT_AVLLS  (1U)          /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */
 168
 169 /*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
 170 #define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS))
 171
 172 /*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */
 173 #define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS)
 174
 175 /*! @brief Set the AVLLS field to a new value. */
 176 #define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v))
 177 /*@}*/
 178
 179 /*!
 180  * @name Register SMC_PMPROT, field ALLS[3] (RW)
 181  *
 182  * Provided the appropriate control bits are set up in PMCTRL, this write-once
 183  * field allows the MCU to enter any low-leakage stop mode (LLS).
 184  *
 185  * Values:
 186  * - 0 - Any LLSx mode is not allowed
 187  * - 1 - Any LLSx mode is allowed
 188  */
 189 /*@{*/
 190 #define BP_SMC_PMPROT_ALLS   (3U)          /*!< Bit position for SMC_PMPROT_ALLS. */
 191 #define BM_SMC_PMPROT_ALLS   (0x08U)       /*!< Bit mask for SMC_PMPROT_ALLS. */
 192 #define BS_SMC_PMPROT_ALLS   (1U)          /*!< Bit field size in bits for SMC_PMPROT_ALLS. */
 193
 194 /*! @brief Read current value of the SMC_PMPROT_ALLS field. */
 195 #define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS))
 196
 197 /*! @brief Format value for bitfield SMC_PMPROT_ALLS. */
 198 #define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS)
 199
 200 /*! @brief Set the ALLS field to a new value. */
 201 #define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v))
 202 /*@}*/
 203
 204 /*!
 205  * @name Register SMC_PMPROT, field AVLP[5] (RW)
 206  *
 207  * Provided the appropriate control bits are set up in PMCTRL, this write-once
 208  * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
 209  *
 210  * Values:
 211  * - 0 - VLPR, VLPW, and VLPS are not allowed.
 212  * - 1 - VLPR, VLPW, and VLPS are allowed.
 213  */
 214 /*@{*/
 215 #define BP_SMC_PMPROT_AVLP   (5U)          /*!< Bit position for SMC_PMPROT_AVLP. */
 216 #define BM_SMC_PMPROT_AVLP   (0x20U)       /*!< Bit mask for SMC_PMPROT_AVLP. */
 217 #define BS_SMC_PMPROT_AVLP   (1U)          /*!< Bit field size in bits for SMC_PMPROT_AVLP. */
 218
 219 /*! @brief Read current value of the SMC_PMPROT_AVLP field. */
 220 #define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP))
 221
 222 /*! @brief Format value for bitfield SMC_PMPROT_AVLP. */
 223 #define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP)
 224
 225 /*! @brief Set the AVLP field to a new value. */
 226 #define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v))
 227 /*@}*/
 228
 229 /*!
 230  * @name Register SMC_PMPROT, field AHSRUN[7] (RW)
 231  *
 232  * Provided the appropriate control bits are set up in PMCTRL, this write-once
 233  * field allows the MCU to enter High Speed Run mode (HSRUN).
 234  *
 235  * Values:
 236  * - 0 - HSRUN is not allowed
 237  * - 1 - HSRUN is allowed
 238  */
 239 /*@{*/
 240 #define BP_SMC_PMPROT_AHSRUN (7U)          /*!< Bit position for SMC_PMPROT_AHSRUN. */
 241 #define BM_SMC_PMPROT_AHSRUN (0x80U)       /*!< Bit mask for SMC_PMPROT_AHSRUN. */
 242 #define BS_SMC_PMPROT_AHSRUN (1U)          /*!< Bit field size in bits for SMC_PMPROT_AHSRUN. */
 243
 244 /*! @brief Read current value of the SMC_PMPROT_AHSRUN field. */
 245 #define BR_SMC_PMPROT_AHSRUN(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN))
 246
 247 /*! @brief Format value for bitfield SMC_PMPROT_AHSRUN. */
 248 #define BF_SMC_PMPROT_AHSRUN(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AHSRUN) & BM_SMC_PMPROT_AHSRUN)
 249
 250 /*! @brief Set the AHSRUN field to a new value. */
 251 #define BW_SMC_PMPROT_AHSRUN(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN) = (v))
 252 /*@}*/
 253
 254 /*******************************************************************************
 255  * HW_SMC_PMCTRL - Power Mode Control register
 256  ******************************************************************************/
 257
 258 /*!
 259  * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
 260  *
 261  * Reset value: 0x00U
 262  *
 263  * The PMCTRL register controls entry into low-power Run and Stop modes,
 264  * provided that the selected power mode is allowed via an appropriate setting of the
 265  * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
 266  * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
 267  * that do not trigger Chip POR not VLLS. See the Reset section details for more
 268  * information.
 269  */
 270 typedef union _hw_smc_pmctrl
 271 {
 272     uint8_t U;
 273     struct _hw_smc_pmctrl_bitfields
 274     {
 275         uint8_t STOPM : 3;             /*!< [2:0] Stop Mode Control */
 276         uint8_t STOPA : 1;             /*!< [3] Stop Aborted */
 277         uint8_t RESERVED0 : 1;         /*!< [4]  */
 278         uint8_t RUNM : 2;              /*!< [6:5] Run Mode Control */
 279         uint8_t RESERVED1 : 1;         /*!< [7]  */
 280     } B;
 281 } hw_smc_pmctrl_t;
 282
 283 /*!
 284  * @name Constants and macros for entire SMC_PMCTRL register
 285  */
 286 /*@{*/
 287 #define HW_SMC_PMCTRL_ADDR(x)    ((x) + 0x1U)
 288
 289 #define HW_SMC_PMCTRL(x)         (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x))
 290 #define HW_SMC_PMCTRL_RD(x)      (HW_SMC_PMCTRL(x).U)
 291 #define HW_SMC_PMCTRL_WR(x, v)   (HW_SMC_PMCTRL(x).U = (v))
 292 #define HW_SMC_PMCTRL_SET(x, v)  (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) |  (v)))
 293 #define HW_SMC_PMCTRL_CLR(x, v)  (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v)))
 294 #define HW_SMC_PMCTRL_TOG(x, v)  (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^  (v)))
 295 /*@}*/
 296
 297 /*
 298  * Constants & macros for individual SMC_PMCTRL bitfields
 299  */
 300
 301 /*!
 302  * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
 303  *
 304  * When written, controls entry into the selected stop mode when Sleep-Now or
 305  * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
 306  * blocked if the protection level has not been enabled using the PMPROT register.
 307  * After any system reset, this field is cleared by hardware on any successful write
 308  * to the PMPROT register. When set to VLLSxor LLSx, the LLSM in the STOPCTRL
 309  * register is used to further select the particular VLLSor LLS submode which will
 310  * be entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be
 311  * used to select a Partial Stop mode if desired.
 312  *
 313  * Values:
 314  * - 000 - Normal Stop (STOP)
 315  * - 001 - Reserved
 316  * - 010 - Very-Low-Power Stop (VLPS)
 317  * - 011 - Low-Leakage Stop (LLSx)
 318  * - 100 - Very-Low-Leakage Stop (VLLSx)
 319  * - 101 - Reserved
 320  * - 110 - Reseved
 321  * - 111 - Reserved
 322  */
 323 /*@{*/
 324 #define BP_SMC_PMCTRL_STOPM  (0U)          /*!< Bit position for SMC_PMCTRL_STOPM. */
 325 #define BM_SMC_PMCTRL_STOPM  (0x07U)       /*!< Bit mask for SMC_PMCTRL_STOPM. */
 326 #define BS_SMC_PMCTRL_STOPM  (3U)          /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */
 327
 328 /*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
 329 #define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM)
 330
 331 /*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */
 332 #define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM)
 333
 334 /*! @brief Set the STOPM field to a new value. */
 335 #define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
 336 /*@}*/
 337
 338 /*!
 339  * @name Register SMC_PMCTRL, field STOPA[3] (RO)
 340  *
 341  * When set, this read-only status bit indicates an interrupt occured during the
 342  * previous stop mode entry sequence, preventing the system from entering that
 343  * mode. This field is cleared by reset or by hardware at the beginning of any
 344  * stop mode entry sequence and is set if the sequence was aborted.
 345  *
 346  * Values:
 347  * - 0 - The previous stop mode entry was successsful.
 348  * - 1 - The previous stop mode entry was aborted.
 349  */
 350 /*@{*/
 351 #define BP_SMC_PMCTRL_STOPA  (3U)          /*!< Bit position for SMC_PMCTRL_STOPA. */
 352 #define BM_SMC_PMCTRL_STOPA  (0x08U)       /*!< Bit mask for SMC_PMCTRL_STOPA. */
 353 #define BS_SMC_PMCTRL_STOPA  (1U)          /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */
 354
 355 /*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
 356 #define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA))
 357 /*@}*/
 358
 359 /*!
 360  * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
 361  *
 362  * When written, causes entry into the selected run mode. Writes to this field
 363  * are blocked if the protection level has not been enabled using the PMPROT
 364  * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
 365  * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. RUNM may be set to
 366  * HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not
 367  * be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not
 368  * be attempted while RUNM=HSRUN or PMSTAT=HSRUN.
 369  *
 370  * Values:
 371  * - 00 - Normal Run mode (RUN)
 372  * - 01 - Reserved
 373  * - 10 - Very-Low-Power Run mode (VLPR)
 374  * - 11 - High Speed Run mode (HSRUN)
 375  */
 376 /*@{*/
 377 #define BP_SMC_PMCTRL_RUNM   (5U)          /*!< Bit position for SMC_PMCTRL_RUNM. */
 378 #define BM_SMC_PMCTRL_RUNM   (0x60U)       /*!< Bit mask for SMC_PMCTRL_RUNM. */
 379 #define BS_SMC_PMCTRL_RUNM   (2U)          /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */
 380
 381 /*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
 382 #define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM)
 383
 384 /*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */
 385 #define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM)
 386
 387 /*! @brief Set the RUNM field to a new value. */
 388 #define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
 389 /*@}*/
 390
 391 /*******************************************************************************
 392  * HW_SMC_STOPCTRL - Stop Control Register
 393  ******************************************************************************/
 394
 395 /*!
 396  * @brief HW_SMC_STOPCTRL - Stop Control Register (RW)
 397  *
 398  * Reset value: 0x03U
 399  *
 400  * The STOPCTRL register provides various control bits allowing the user to fine
 401  * tune power consumption during the stop mode selected by the STOPM field. This
 402  * register is reset on Chip POR not VLLS and by reset types that trigger Chip
 403  * POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not
 404  * VLLS. See the Reset section details for more information.
 405  */
 406 typedef union _hw_smc_stopctrl
 407 {
 408     uint8_t U;
 409     struct _hw_smc_stopctrl_bitfields
 410     {
 411         uint8_t LLSM : 3;              /*!< [2:0] LLS or VLLS Mode Control */
 412         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
 413         uint8_t PORPO : 1;             /*!< [5] POR Power Option */
 414         uint8_t PSTOPO : 2;            /*!< [7:6] Partial Stop Option */
 415     } B;
 416 } hw_smc_stopctrl_t;
 417
 418 /*!
 419  * @name Constants and macros for entire SMC_STOPCTRL register
 420  */
 421 /*@{*/
 422 #define HW_SMC_STOPCTRL_ADDR(x)  ((x) + 0x2U)
 423
 424 #define HW_SMC_STOPCTRL(x)       (*(__IO hw_smc_stopctrl_t *) HW_SMC_STOPCTRL_ADDR(x))
 425 #define HW_SMC_STOPCTRL_RD(x)    (HW_SMC_STOPCTRL(x).U)
 426 #define HW_SMC_STOPCTRL_WR(x, v) (HW_SMC_STOPCTRL(x).U = (v))
 427 #define HW_SMC_STOPCTRL_SET(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) |  (v)))
 428 #define HW_SMC_STOPCTRL_CLR(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) & ~(v)))
 429 #define HW_SMC_STOPCTRL_TOG(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) ^  (v)))
 430 /*@}*/
 431
 432 /*
 433  * Constants & macros for individual SMC_STOPCTRL bitfields
 434  */
 435
 436 /*!
 437  * @name Register SMC_STOPCTRL, field LLSM[2:0] (RW)
 438  *
 439  * This field controls which LLS or VLLS sub-mode to enter if STOPM=LLSx or
 440  * VLLSx.
 441  *
 442  * Values:
 443  * - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
 444  * - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
 445  * - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
 446  * - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
 447  * - 100 - Reserved
 448  * - 101 - Reserved
 449  * - 110 - Reserved
 450  * - 111 - Reserved
 451  */
 452 /*@{*/
 453 #define BP_SMC_STOPCTRL_LLSM (0U)          /*!< Bit position for SMC_STOPCTRL_LLSM. */
 454 #define BM_SMC_STOPCTRL_LLSM (0x07U)       /*!< Bit mask for SMC_STOPCTRL_LLSM. */
 455 #define BS_SMC_STOPCTRL_LLSM (3U)          /*!< Bit field size in bits for SMC_STOPCTRL_LLSM. */
 456
 457 /*! @brief Read current value of the SMC_STOPCTRL_LLSM field. */
 458 #define BR_SMC_STOPCTRL_LLSM(x) (HW_SMC_STOPCTRL(x).B.LLSM)
 459
 460 /*! @brief Format value for bitfield SMC_STOPCTRL_LLSM. */
 461 #define BF_SMC_STOPCTRL_LLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_LLSM) & BM_SMC_STOPCTRL_LLSM)
 462
 463 /*! @brief Set the LLSM field to a new value. */
 464 #define BW_SMC_STOPCTRL_LLSM(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_LLSM) | BF_SMC_STOPCTRL_LLSM(v)))
 465 /*@}*/
 466
 467 /*!
 468  * @name Register SMC_STOPCTRL, field PORPO[5] (RW)
 469  *
 470  * This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
 471  *
 472  * Values:
 473  * - 0 - POR detect circuit is enabled in VLLS0
 474  * - 1 - POR detect circuit is disabled in VLLS0
 475  */
 476 /*@{*/
 477 #define BP_SMC_STOPCTRL_PORPO (5U)         /*!< Bit position for SMC_STOPCTRL_PORPO. */
 478 #define BM_SMC_STOPCTRL_PORPO (0x20U)      /*!< Bit mask for SMC_STOPCTRL_PORPO. */
 479 #define BS_SMC_STOPCTRL_PORPO (1U)         /*!< Bit field size in bits for SMC_STOPCTRL_PORPO. */
 480
 481 /*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */
 482 #define BR_SMC_STOPCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO))
 483
 484 /*! @brief Format value for bitfield SMC_STOPCTRL_PORPO. */
 485 #define BF_SMC_STOPCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PORPO) & BM_SMC_STOPCTRL_PORPO)
 486
 487 /*! @brief Set the PORPO field to a new value. */
 488 #define BW_SMC_STOPCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO) = (v))
 489 /*@}*/
 490
 491 /*!
 492  * @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW)
 493  *
 494  * These bits control whether a Partial Stop mode is entered when STOPM=STOP.
 495  * When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain
 496  * fully powered, allowing the device to wakeup almost instantaneously at the
 497  * expense of higher power consumption. In PSTOP2, only system clocks are gated
 498  * allowing peripherals running on bus clock to remain fully functional. In PSTOP1,
 499  * both system and bus clocks are gated.
 500  *
 501  * Values:
 502  * - 00 - STOP - Normal Stop mode
 503  * - 01 - PSTOP1 - Partial Stop with both system and bus clocks disabled
 504  * - 10 - PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
 505  * - 11 - Reserved
 506  */
 507 /*@{*/
 508 #define BP_SMC_STOPCTRL_PSTOPO (6U)        /*!< Bit position for SMC_STOPCTRL_PSTOPO. */
 509 #define BM_SMC_STOPCTRL_PSTOPO (0xC0U)     /*!< Bit mask for SMC_STOPCTRL_PSTOPO. */
 510 #define BS_SMC_STOPCTRL_PSTOPO (2U)        /*!< Bit field size in bits for SMC_STOPCTRL_PSTOPO. */
 511
 512 /*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */
 513 #define BR_SMC_STOPCTRL_PSTOPO(x) (HW_SMC_STOPCTRL(x).B.PSTOPO)
 514
 515 /*! @brief Format value for bitfield SMC_STOPCTRL_PSTOPO. */
 516 #define BF_SMC_STOPCTRL_PSTOPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PSTOPO) & BM_SMC_STOPCTRL_PSTOPO)
 517
 518 /*! @brief Set the PSTOPO field to a new value. */
 519 #define BW_SMC_STOPCTRL_PSTOPO(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_PSTOPO) | BF_SMC_STOPCTRL_PSTOPO(v)))
 520 /*@}*/
 521
 522 /*******************************************************************************
 523  * HW_SMC_PMSTAT - Power Mode Status register
 524  ******************************************************************************/
 525
 526 /*!
 527  * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
 528  *
 529  * Reset value: 0x01U
 530  *
 531  * PMSTAT is a read-only, one-hot register which indicates the current power
 532  * mode of the system. This register is reset on Chip POR not VLLS and by reset
 533  * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
 534  * trigger Chip POR not VLLS. See the Reset section details for more information.
 535  */
 536 typedef union _hw_smc_pmstat
 537 {
 538     uint8_t U;
 539     struct _hw_smc_pmstat_bitfields
 540     {
 541         uint8_t PMSTAT : 8;            /*!< [7:0]  */
 542     } B;
 543 } hw_smc_pmstat_t;
 544
 545 /*!
 546  * @name Constants and macros for entire SMC_PMSTAT register
 547  */
 548 /*@{*/
 549 #define HW_SMC_PMSTAT_ADDR(x)    ((x) + 0x3U)
 550
 551 #define HW_SMC_PMSTAT(x)         (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x))
 552 #define HW_SMC_PMSTAT_RD(x)      (HW_SMC_PMSTAT(x).U)
 553 /*@}*/
 554
 555 /*
 556  * Constants & macros for individual SMC_PMSTAT bitfields
 557  */
 558
 559 /*!
 560  * @name Register SMC_PMSTAT, field PMSTAT[7:0] (RO)
 561  *
 562  * When debug is enabled, the PMSTAT will not update to STOP or VLPS When a
 563  * PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS
 564  */
 565 /*@{*/
 566 #define BP_SMC_PMSTAT_PMSTAT (0U)          /*!< Bit position for SMC_PMSTAT_PMSTAT. */
 567 #define BM_SMC_PMSTAT_PMSTAT (0xFFU)       /*!< Bit mask for SMC_PMSTAT_PMSTAT. */
 568 #define BS_SMC_PMSTAT_PMSTAT (8U)          /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */
 569
 570 /*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
 571 #define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).U)
 572 /*@}*/
 573
 574 /*******************************************************************************
 575  * hw_smc_t - module struct
 576  ******************************************************************************/
 577 /*!
 578  * @brief All SMC module registers.
 579  */
 580 #pragma pack(1)
 581 typedef struct _hw_smc
 582 {
 583     __IO hw_smc_pmprot_t PMPROT;           /*!< [0x0] Power Mode Protection register */
 584     __IO hw_smc_pmctrl_t PMCTRL;           /*!< [0x1] Power Mode Control register */
 585     __IO hw_smc_stopctrl_t STOPCTRL;       /*!< [0x2] Stop Control Register */
 586     __I hw_smc_pmstat_t PMSTAT;            /*!< [0x3] Power Mode Status register */
 587 } hw_smc_t;
 588 #pragma pack()
 589
 590 /*! @brief Macro to access all SMC registers. */
 591 /*! @param x SMC module instance base address. */
 592 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 593  *     use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */
 594 #define HW_SMC(x)      (*(hw_smc_t *)(x))
 595
 596 #endif /* __HW_SMC_REGISTERS_H__ */
 597 /* EOF */