keyboard/infinity/tool/k20dx32_flash.cfg

   1 # FreeScale Kinetis K20 devices with 32kB Flash and 8kB Local On-Chip SRAM,
   2 # Nemuisan's Special for MK20DN32VFT5,MK20DX32VFT5,MK10DN32VFT5,MK10DX32VFT5
   3
   4
   5 source [find target/swj-dp.tcl]
   6
   7 if { [info exists CHIPNAME] } {
   8     set _CHIPNAME $CHIPNAME
   9 } else {
  10     set _CHIPNAME k20
  11 }
  12
  13 if { [info exists ENDIAN] } {
  14     set _ENDIAN $ENDIAN
  15 } else {
  16     set _ENDIAN little
  17 }
  18
  19 if { [info exists CPUTAPID] } {
  20    set _CPUTAPID $CPUTAPID
  21 } else {
  22    if { [using_jtag] } {
  23       set _CPUTAPID 0x4BA00477
  24    } {
  25       # this is the SW-DP tap id not the jtag tap id
  26       set _CPUTAPID 0x2BA01477
  27    }
  28 }
  29
  30 # Work-area is a space in RAM used for flash programming
  31 # By default use 8kB
  32 if { [info exists WORKAREASIZE] == 0 } {
  33    set _WORKAREASIZE 0x2000
  34 }
  35
  36 # Select "srst_only", Nemuisan said so!
  37 echo "Kinetis MUST need Hardware SRST Control to Recover Secure-State!"
  38 adapter_nsrst_delay 200
  39 reset_config srst_only
  40
  41 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  42 set _TARGETNAME $_CHIPNAME.cpu
  43 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
  44
  45 # It is important that "kinetis mdm check_security" is called for
  46 # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
  47 # causes "kinetis mdm check_security" to fail the first time openocd
  48 # calls it when it tries to connect after the CPU has been power-cycled.
  49 $_CHIPNAME.cpu configure -event examine-end {
  50         kinetis mdm check_security
  51 # Uncomment when gone into s*ck'n secured state!
  52 #       kinetis mdm mass_erase
  53 }
  54
  55 # K20 has minimun 8kB of SRAM and starts at 1FFFF000.
  56 $_TARGETNAME configure -work-area-phys 0x1FFFF000 -work-area-size $_WORKAREASIZE -work-area-backup 0 -rtos auto
  57
  58 # MK20DN32VFT5,MK20DX32VFT5,MK10DN32VFT5,MK10DX32VFT5 has 32kB of flash memory.
  59 flash bank $_CHIPNAME.pflash kinetis 0x00000000 0x8000 0 4 $_TARGETNAME
  60
  61
  62 proc mt_flash {IMGFILE} {
  63         flash write_image erase $IMGFILE
  64         reset run
  65         halt
  66         verify_image $IMGFILE
  67         reset run
  68         shutdown
  69 }
  70
  71 proc mt_flash_bin {IMGFILE OFFSET} {
  72         flash write_image erase $IMGFILE $OFFSET bin
  73         reset run
  74         halt
  75         verify_image $IMGFILE $OFFSET bin
  76         reset run
  77         shutdown
  78 }
  79
  80 proc mt_flash_hex {IMGFILE} {
  81         flash write_image erase $IMGFILE 0 ihex
  82         reset run
  83         halt
  84         verify_image $IMGFILE 0 ihex
  85         reset run
  86         shutdown
  87 }
  88
  89 proc mt_flash_srec {IMGFILE} {
  90         flash write_image erase $IMGFILE 0 s19
  91         reset run
  92         halt
  93         verify_image $IMGFILE 0 s19
  94         reset run
  95         shutdown
  96 }
  97
  98 proc mass_erase {} {
  99         kinetis mdm mass_erase
 100 }
 101
 102 proc eraser {} {
 103 # Verbose procedure confirmed erase routine
 104         flash info 0
 105 # CAUTION! "flash erase_sector 0 0 last" goes into secure state!!!
 106 # USE "mass_erase" command instead of
 107 #       flash erase_sector 0 0 last
 108         mass_erase
 109         shutdown
 110 }
 111
 112
 113 #debug_level 3
 114 # HLA doesn't have cortex_m commands
 115 if {![using_hla]} {
 116    # if srst is not fitted use SYSRESETREQ to
 117    # perform a soft reset
 118    cortex_m reset_config sysresetreq
 119 }
 120 adapter_khz 1000
 121 reset_config srst_only srst_nogate connect_assert_srst
 122 gdb_target_description disable
 123 init
 124 reset init