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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_K20XX / TARGET_TEENSY3_1 / MK20DX256.h
1 /*
2 ** ###################################################################
3 ** Processors: MK20DX64VLH7
4 ** MK20DX128VLH7
5 ** MK20DX256VLH7
6 ** MK20DX64VLK7
7 ** MK20DX128VLK7
8 ** MK20DX256VLK7
9 ** MK20DX128VLL7
10 ** MK20DX256VLL7
11 ** MK20DX64VMB7
12 ** MK20DX128VMB7
13 ** MK20DX256VMB7
14 ** MK20DX128VML7
15 ** MK20DX256VML7
16 **
17 ** Compilers: ARM Compiler
18 ** Freescale C/C++ for Embedded ARM
19 ** GNU C Compiler
20 ** IAR ANSI C/C++ Compiler for ARM
21 **
22 ** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011
23 ** Version: rev. 1.0, 2012-01-15
24 **
25 ** Abstract:
26 ** Provides a system configuration function and a global variable that
27 ** contains the system frequency. It configures the device and initializes
28 ** the oscillator (PLL) that is part of the microcontroller device.
29 **
30 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
31 **
32 ** http: www.freescale.com
33 ** mail: support@freescale.com
34 **
35 ** Revisions:
36 ** - rev. 1.0 (2012-01-15)
37 ** Initial public version.
38 **
39 ** ###################################################################
40 */
41
42 /**
43 * @file MK20DX256.h
44 * @version 2.0
45 * @date 2012-03-19
46 * @brief CMSIS Peripheral Access Layer for MK20DX256
47 *
48 * CMSIS Peripheral Access Layer for MK20DX256
49 */
50
51 #if !defined(MK20DX256_H_)
52 #define MK20DX256_H_ /**< Symbol preventing repeated inclusion */
53 #define MCU_MK20DX256
54 /** Memory map major version (memory maps with equal major version number are
55 * compatible) */
56 #define MCU_MEM_MAP_VERSION 0x0200u
57 /** Memory map minor version */
58 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
59
60 /**
61 * @brief Macro to access a single bit of a peripheral register (bit band region
62 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
63 * @param Reg Register to access.
64 * @param Bit Bit number to access.
65 * @return Value of the targeted bit in the bit band region.
66 */
67 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
68
69 /* ----------------------------------------------------------------------------
70 -- Interrupt vector numbers
71 ---------------------------------------------------------------------------- */
72
73 /**
74 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
75 * @{
76 */
77
78 /** Interrupt Number Definitions */
79 typedef enum IRQn {
80 /* Core interrupts */
81 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
82 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
83 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
84 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
85 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
86 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
87 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
88 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
89
90 /* Device specific interrupts */
91
92 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
93 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
94 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
95 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
96 DMA4_IRQn = 4,
97 DMA5_IRQn = 5,
98 DMA6_IRQn = 6,
99 DMA7_IRQn = 7,
100 DMA8_IRQn = 8,
101 DMA9_IRQn = 9,
102 DMA10_IRQn = 10,
103 DMA11_IRQn = 11,
104 DMA12_IRQn = 12,
105 DMA13_IRQn = 13,
106 DMA14_IRQn = 14,
107 DMA15_IRQn = 15,
108 DMA_Error_IRQn = 16, /**< DMA error interrupt */
109 Reserved33_IRQn = 17,
110 FTFL_IRQn = 18, /**< FTFL interrupt */
111 Read_Collision_IRQn = 19, /**< Read collision interrupt */
112 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
113 LLW_IRQn = 21, /**< Low Leakage Wakeup */
114 Watchdog_IRQn = 22, /**< WDOG interrupt */
115 Reserved39_IRQn = 23,
116 I2C0_IRQn = 24, /**< I2C0 interrupt */
117 I2C1_IRQn = 25,
118 SPI0_IRQn = 26, /**< SPI0 interrupt */
119 SPI1_IRQn = 27,
120 Reserved44_IRQn = 28,
121 CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */
122 CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */
123 CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */
124 CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */
125 CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */
126 CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */
127 I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */
128 I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */
129 Reserved53_IRQn = 37,
130 Reserved54_IRQn = 38,
131 Reserved55_IRQn = 39,
132 Reserved56_IRQn = 40,
133 Reserved57_IRQn = 41,
134 Reserved58_IRQn = 42,
135 Reserved59_IRQn = 43,
136 UART0_LON_IRQn = 44, /**< UART0 LON interrupt */
137 UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */
138 UART0_ERR_IRQn = 46, /**< UART0 error interrupt */
139 UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */
140 UART1_ERR_IRQn = 48, /**< UART1 error interrupt */
141 UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */
142 UART2_ERR_IRQn = 50, /**< UART2 error interrupt */
143 Reserved67_IRQn = 51,
144 Reserved68_IRQn = 52,
145 Reserved69_IRQn = 53,
146 Reserved70_IRQn = 54,
147 Reserved71_IRQn = 55,
148 Reserved72_IRQn = 56,
149 ADC0_IRQn = 57, /**< ADC0 interrupt */
150 ADC1_IRQn = 58,
151 CMP0_IRQn = 59, /**< CMP0 interrupt */
152 CMP1_IRQn = 60, /**< CMP1 interrupt */
153 CMP2_IRQn = 61,
154 FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
155 FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
156 FTM2_IRQn = 64,
157 CMT_IRQn = 65, /**< CMT interrupt */
158 RTC_IRQn = 66, /**< RTC interrupt */
159 RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */
160 PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
161 PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
162 PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
163 PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
164 PDB0_IRQn = 72, /**< PDB0 interrupt */
165 USB0_IRQn = 73, /**< USB0 interrupt */
166 USBDCD_IRQn = 74, /**< USBDCD interrupt */
167 Reserved91_IRQn = 75,
168 Reserved92_IRQn = 76,
169 Reserved93_IRQn = 77,
170 Reserved94_IRQn = 78,
171 Reserved95_IRQn = 79,
172 Reserved96_IRQn = 80,
173 DAC0_IRQn = 81,
174 Reserved98_IRQn = 82,
175 TSI0_IRQn = 83, /**< TSI0 interrupt */
176 MCG_IRQn = 84, /**< MCG interrupt */
177 LPTimer_IRQn = 85, /**< LPTimer interrupt */
178 Reserved102_IRQn = 86,
179 PORTA_IRQn = 87, /**< Port A interrupt */
180 PORTB_IRQn = 88, /**< Port B interrupt */
181 PORTC_IRQn = 89, /**< Port C interrupt */
182 PORTD_IRQn = 90, /**< Port D interrupt */
183 PORTE_IRQn = 91, /**< Port E interrupt */
184 Reserved108_IRQn = 92,
185 Reserved109_IRQn = 93,
186 SWI_IRQn = 94 /**< Software interrupt */
187
188 } IRQn_Type;
189
190 /**
191 * @}
192 */ /* end of group Interrupt_vector_numbers */
193
194
195 /* ----------------------------------------------------------------------------
196 -- Cortex M4 Core Configuration
197 ---------------------------------------------------------------------------- */
198
199 /**
200 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
201 * @{
202 */
203
204 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
205 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
206 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
207
208 #include "core_cm4.h" /* Core Peripheral Access Layer */
209 #include "system_MK20DX256.h" /* Device specific configuration file */
210
211 /**
212 * @}
213 */ /* end of group Cortex_Core_Configuration */
214
215
216 /* ----------------------------------------------------------------------------
217 -- Device Peripheral Access Layer
218 ---------------------------------------------------------------------------- */
219
220 /**
221 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
222 * @{
223 */
224
225
226 /*
227 ** Start of section using anonymous unions
228 */
229
230 #if defined(__ARMCC_VERSION)
231 #pragma push
232 #pragma anon_unions
233 #elif defined(__CWCC__)
234 #pragma push
235 #pragma cpp_extensions on
236 #elif defined(__GNUC__)
237 /* anonymous unions are enabled by default */
238 #elif defined(__IAR_SYSTEMS_ICC__)
239 #pragma language=extended
240 #else
241 #error Not supported compiler type
242 #endif
243
244 /* ----------------------------------------------------------------------------
245 -- ADC Peripheral Access Layer
246 ---------------------------------------------------------------------------- */
247
248 /**
249 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
250 * @{
251 */
252
253 /** ADC - Register Layout Typedef */
254 typedef struct {
255 __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
256 __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
257 __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
258 __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
259 __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
260 __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
261 __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
262 __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
263 __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
264 __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
265 __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
266 __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
267 __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
268 __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
269 __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
270 __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
271 __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
272 __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
273 uint8_t RESERVED_0[4];
274 __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
275 __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
276 __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
277 __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
278 __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
279 __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
280 __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
281 } ADC_Type;
282
283 /* ----------------------------------------------------------------------------
284 -- ADC Register Masks
285 ---------------------------------------------------------------------------- */
286
287 /**
288 * @addtogroup ADC_Register_Masks ADC Register Masks
289 * @{
290 */
291
292 /* SC1 Bit Fields */
293 #define ADC_SC1_ADCH_MASK 0x1Fu
294 #define ADC_SC1_ADCH_SHIFT 0
295 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
296 #define ADC_SC1_DIFF_MASK 0x20u
297 #define ADC_SC1_DIFF_SHIFT 5
298 #define ADC_SC1_AIEN_MASK 0x40u
299 #define ADC_SC1_AIEN_SHIFT 6
300 #define ADC_SC1_COCO_MASK 0x80u
301 #define ADC_SC1_COCO_SHIFT 7
302 /* CFG1 Bit Fields */
303 #define ADC_CFG1_ADICLK_MASK 0x3u
304 #define ADC_CFG1_ADICLK_SHIFT 0
305 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
306 #define ADC_CFG1_MODE_MASK 0xCu
307 #define ADC_CFG1_MODE_SHIFT 2
308 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
309 #define ADC_CFG1_ADLSMP_MASK 0x10u
310 #define ADC_CFG1_ADLSMP_SHIFT 4
311 #define ADC_CFG1_ADIV_MASK 0x60u
312 #define ADC_CFG1_ADIV_SHIFT 5
313 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
314 #define ADC_CFG1_ADLPC_MASK 0x80u
315 #define ADC_CFG1_ADLPC_SHIFT 7
316 /* CFG2 Bit Fields */
317 #define ADC_CFG2_ADLSTS_MASK 0x3u
318 #define ADC_CFG2_ADLSTS_SHIFT 0
319 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
320 #define ADC_CFG2_ADHSC_MASK 0x4u
321 #define ADC_CFG2_ADHSC_SHIFT 2
322 #define ADC_CFG2_ADACKEN_MASK 0x8u
323 #define ADC_CFG2_ADACKEN_SHIFT 3
324 #define ADC_CFG2_MUXSEL_MASK 0x10u
325 #define ADC_CFG2_MUXSEL_SHIFT 4
326 /* R Bit Fields */
327 #define ADC_R_D_MASK 0xFFFFu
328 #define ADC_R_D_SHIFT 0
329 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
330 /* CV1 Bit Fields */
331 #define ADC_CV1_CV_MASK 0xFFFFu
332 #define ADC_CV1_CV_SHIFT 0
333 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
334 /* CV2 Bit Fields */
335 #define ADC_CV2_CV_MASK 0xFFFFu
336 #define ADC_CV2_CV_SHIFT 0
337 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
338 /* SC2 Bit Fields */
339 #define ADC_SC2_REFSEL_MASK 0x3u
340 #define ADC_SC2_REFSEL_SHIFT 0
341 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
342 #define ADC_SC2_DMAEN_MASK 0x4u
343 #define ADC_SC2_DMAEN_SHIFT 2
344 #define ADC_SC2_ACREN_MASK 0x8u
345 #define ADC_SC2_ACREN_SHIFT 3
346 #define ADC_SC2_ACFGT_MASK 0x10u
347 #define ADC_SC2_ACFGT_SHIFT 4
348 #define ADC_SC2_ACFE_MASK 0x20u
349 #define ADC_SC2_ACFE_SHIFT 5
350 #define ADC_SC2_ADTRG_MASK 0x40u
351 #define ADC_SC2_ADTRG_SHIFT 6
352 #define ADC_SC2_ADACT_MASK 0x80u
353 #define ADC_SC2_ADACT_SHIFT 7
354 /* SC3 Bit Fields */
355 #define ADC_SC3_AVGS_MASK 0x3u
356 #define ADC_SC3_AVGS_SHIFT 0
357 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
358 #define ADC_SC3_AVGE_MASK 0x4u
359 #define ADC_SC3_AVGE_SHIFT 2
360 #define ADC_SC3_ADCO_MASK 0x8u
361 #define ADC_SC3_ADCO_SHIFT 3
362 #define ADC_SC3_CALF_MASK 0x40u
363 #define ADC_SC3_CALF_SHIFT 6
364 #define ADC_SC3_CAL_MASK 0x80u
365 #define ADC_SC3_CAL_SHIFT 7
366 /* OFS Bit Fields */
367 #define ADC_OFS_OFS_MASK 0xFFFFu
368 #define ADC_OFS_OFS_SHIFT 0
369 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
370 /* PG Bit Fields */
371 #define ADC_PG_PG_MASK 0xFFFFu
372 #define ADC_PG_PG_SHIFT 0
373 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
374 /* MG Bit Fields */
375 #define ADC_MG_MG_MASK 0xFFFFu
376 #define ADC_MG_MG_SHIFT 0
377 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
378 /* CLPD Bit Fields */
379 #define ADC_CLPD_CLPD_MASK 0x3Fu
380 #define ADC_CLPD_CLPD_SHIFT 0
381 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
382 /* CLPS Bit Fields */
383 #define ADC_CLPS_CLPS_MASK 0x3Fu
384 #define ADC_CLPS_CLPS_SHIFT 0
385 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
386 /* CLP4 Bit Fields */
387 #define ADC_CLP4_CLP4_MASK 0x3FFu
388 #define ADC_CLP4_CLP4_SHIFT 0
389 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
390 /* CLP3 Bit Fields */
391 #define ADC_CLP3_CLP3_MASK 0x1FFu
392 #define ADC_CLP3_CLP3_SHIFT 0
393 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
394 /* CLP2 Bit Fields */
395 #define ADC_CLP2_CLP2_MASK 0xFFu
396 #define ADC_CLP2_CLP2_SHIFT 0
397 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
398 /* CLP1 Bit Fields */
399 #define ADC_CLP1_CLP1_MASK 0x7Fu
400 #define ADC_CLP1_CLP1_SHIFT 0
401 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
402 /* CLP0 Bit Fields */
403 #define ADC_CLP0_CLP0_MASK 0x3Fu
404 #define ADC_CLP0_CLP0_SHIFT 0
405 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
406 /* CLMD Bit Fields */
407 #define ADC_CLMD_CLMD_MASK 0x3Fu
408 #define ADC_CLMD_CLMD_SHIFT 0
409 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
410 /* CLMS Bit Fields */
411 #define ADC_CLMS_CLMS_MASK 0x3Fu
412 #define ADC_CLMS_CLMS_SHIFT 0
413 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
414 /* CLM4 Bit Fields */
415 #define ADC_CLM4_CLM4_MASK 0x3FFu
416 #define ADC_CLM4_CLM4_SHIFT 0
417 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
418 /* CLM3 Bit Fields */
419 #define ADC_CLM3_CLM3_MASK 0x1FFu
420 #define ADC_CLM3_CLM3_SHIFT 0
421 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
422 /* CLM2 Bit Fields */
423 #define ADC_CLM2_CLM2_MASK 0xFFu
424 #define ADC_CLM2_CLM2_SHIFT 0
425 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
426 /* CLM1 Bit Fields */
427 #define ADC_CLM1_CLM1_MASK 0x7Fu
428 #define ADC_CLM1_CLM1_SHIFT 0
429 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
430 /* CLM0 Bit Fields */
431 #define ADC_CLM0_CLM0_MASK 0x3Fu
432 #define ADC_CLM0_CLM0_SHIFT 0
433 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
434
435 /**
436 * @}
437 */ /* end of group ADC_Register_Masks */
438
439
440 /* ADC - Peripheral instance base addresses */
441 /** Peripheral ADC0 base address */
442 #define ADC0_BASE (0x4003B000u)
443 /** Peripheral ADC0 base pointer */
444 #define ADC0 ((ADC_Type *)ADC0_BASE)
445
446 /**
447 * @}
448 */ /* end of group ADC_Peripheral_Access_Layer */
449
450
451 /* ----------------------------------------------------------------------------
452 -- CMP Peripheral Access Layer
453 ---------------------------------------------------------------------------- */
454
455 /**
456 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
457 * @{
458 */
459
460 /** CMP - Register Layout Typedef */
461 typedef struct {
462 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
463 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
464 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
465 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
466 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
467 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
468 } CMP_Type;
469
470 /* ----------------------------------------------------------------------------
471 -- CMP Register Masks
472 ---------------------------------------------------------------------------- */
473
474 /**
475 * @addtogroup CMP_Register_Masks CMP Register Masks
476 * @{
477 */
478
479 /* CR0 Bit Fields */
480 #define CMP_CR0_HYSTCTR_MASK 0x3u
481 #define CMP_CR0_HYSTCTR_SHIFT 0
482 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
483 #define CMP_CR0_FILTER_CNT_MASK 0x70u
484 #define CMP_CR0_FILTER_CNT_SHIFT 4
485 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
486 /* CR1 Bit Fields */
487 #define CMP_CR1_EN_MASK 0x1u
488 #define CMP_CR1_EN_SHIFT 0
489 #define CMP_CR1_OPE_MASK 0x2u
490 #define CMP_CR1_OPE_SHIFT 1
491 #define CMP_CR1_COS_MASK 0x4u
492 #define CMP_CR1_COS_SHIFT 2
493 #define CMP_CR1_INV_MASK 0x8u
494 #define CMP_CR1_INV_SHIFT 3
495 #define CMP_CR1_PMODE_MASK 0x10u
496 #define CMP_CR1_PMODE_SHIFT 4
497 #define CMP_CR1_WE_MASK 0x40u
498 #define CMP_CR1_WE_SHIFT 6
499 #define CMP_CR1_SE_MASK 0x80u
500 #define CMP_CR1_SE_SHIFT 7
501 /* FPR Bit Fields */
502 #define CMP_FPR_FILT_PER_MASK 0xFFu
503 #define CMP_FPR_FILT_PER_SHIFT 0
504 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
505 /* SCR Bit Fields */
506 #define CMP_SCR_COUT_MASK 0x1u
507 #define CMP_SCR_COUT_SHIFT 0
508 #define CMP_SCR_CFF_MASK 0x2u
509 #define CMP_SCR_CFF_SHIFT 1
510 #define CMP_SCR_CFR_MASK 0x4u
511 #define CMP_SCR_CFR_SHIFT 2
512 #define CMP_SCR_IEF_MASK 0x8u
513 #define CMP_SCR_IEF_SHIFT 3
514 #define CMP_SCR_IER_MASK 0x10u
515 #define CMP_SCR_IER_SHIFT 4
516 #define CMP_SCR_DMAEN_MASK 0x40u
517 #define CMP_SCR_DMAEN_SHIFT 6
518 /* DACCR Bit Fields */
519 #define CMP_DACCR_VOSEL_MASK 0x3Fu
520 #define CMP_DACCR_VOSEL_SHIFT 0
521 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
522 #define CMP_DACCR_VRSEL_MASK 0x40u
523 #define CMP_DACCR_VRSEL_SHIFT 6
524 #define CMP_DACCR_DACEN_MASK 0x80u
525 #define CMP_DACCR_DACEN_SHIFT 7
526 /* MUXCR Bit Fields */
527 #define CMP_MUXCR_MSEL_MASK 0x7u
528 #define CMP_MUXCR_MSEL_SHIFT 0
529 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
530 #define CMP_MUXCR_PSEL_MASK 0x38u
531 #define CMP_MUXCR_PSEL_SHIFT 3
532 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
533
534 /**
535 * @}
536 */ /* end of group CMP_Register_Masks */
537
538
539 /* CMP - Peripheral instance base addresses */
540 /** Peripheral CMP0 base address */
541 #define CMP0_BASE (0x40073000u)
542 /** Peripheral CMP0 base pointer */
543 #define CMP0 ((CMP_Type *)CMP0_BASE)
544 /** Peripheral CMP1 base address */
545 #define CMP1_BASE (0x40073008u)
546 /** Peripheral CMP1 base pointer */
547 #define CMP1 ((CMP_Type *)CMP1_BASE)
548
549 /**
550 * @}
551 */ /* end of group CMP_Peripheral_Access_Layer */
552
553
554 /* ----------------------------------------------------------------------------
555 -- CMT Peripheral Access Layer
556 ---------------------------------------------------------------------------- */
557
558 /**
559 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
560 * @{
561 */
562
563 /** CMT - Register Layout Typedef */
564 typedef struct {
565 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
566 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
567 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
568 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
569 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
570 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
571 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
572 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
573 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
574 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
575 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
576 __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
577 } CMT_Type;
578
579 /* ----------------------------------------------------------------------------
580 -- CMT Register Masks
581 ---------------------------------------------------------------------------- */
582
583 /**
584 * @addtogroup CMT_Register_Masks CMT Register Masks
585 * @{
586 */
587
588 /* CGH1 Bit Fields */
589 #define CMT_CGH1_PH_MASK 0xFFu
590 #define CMT_CGH1_PH_SHIFT 0
591 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
592 /* CGL1 Bit Fields */
593 #define CMT_CGL1_PL_MASK 0xFFu
594 #define CMT_CGL1_PL_SHIFT 0
595 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
596 /* CGH2 Bit Fields */
597 #define CMT_CGH2_SH_MASK 0xFFu
598 #define CMT_CGH2_SH_SHIFT 0
599 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
600 /* CGL2 Bit Fields */
601 #define CMT_CGL2_SL_MASK 0xFFu
602 #define CMT_CGL2_SL_SHIFT 0
603 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
604 /* OC Bit Fields */
605 #define CMT_OC_IROPEN_MASK 0x20u
606 #define CMT_OC_IROPEN_SHIFT 5
607 #define CMT_OC_CMTPOL_MASK 0x40u
608 #define CMT_OC_CMTPOL_SHIFT 6
609 #define CMT_OC_IROL_MASK 0x80u
610 #define CMT_OC_IROL_SHIFT 7
611 /* MSC Bit Fields */
612 #define CMT_MSC_MCGEN_MASK 0x1u
613 #define CMT_MSC_MCGEN_SHIFT 0
614 #define CMT_MSC_EOCIE_MASK 0x2u
615 #define CMT_MSC_EOCIE_SHIFT 1
616 #define CMT_MSC_FSK_MASK 0x4u
617 #define CMT_MSC_FSK_SHIFT 2
618 #define CMT_MSC_BASE_MASK 0x8u
619 #define CMT_MSC_BASE_SHIFT 3
620 #define CMT_MSC_EXSPC_MASK 0x10u
621 #define CMT_MSC_EXSPC_SHIFT 4
622 #define CMT_MSC_CMTDIV_MASK 0x60u
623 #define CMT_MSC_CMTDIV_SHIFT 5
624 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
625 #define CMT_MSC_EOCF_MASK 0x80u
626 #define CMT_MSC_EOCF_SHIFT 7
627 /* CMD1 Bit Fields */
628 #define CMT_CMD1_MB_MASK 0xFFu
629 #define CMT_CMD1_MB_SHIFT 0
630 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
631 /* CMD2 Bit Fields */
632 #define CMT_CMD2_MB_MASK 0xFFu
633 #define CMT_CMD2_MB_SHIFT 0
634 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
635 /* CMD3 Bit Fields */
636 #define CMT_CMD3_SB_MASK 0xFFu
637 #define CMT_CMD3_SB_SHIFT 0
638 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
639 /* CMD4 Bit Fields */
640 #define CMT_CMD4_SB_MASK 0xFFu
641 #define CMT_CMD4_SB_SHIFT 0
642 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
643 /* PPS Bit Fields */
644 #define CMT_PPS_PPSDIV_MASK 0xFu
645 #define CMT_PPS_PPSDIV_SHIFT 0
646 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
647 /* DMA Bit Fields */
648 #define CMT_DMA_DMA_MASK 0x1u
649 #define CMT_DMA_DMA_SHIFT 0
650
651 /**
652 * @}
653 */ /* end of group CMT_Register_Masks */
654
655
656 /* CMT - Peripheral instance base addresses */
657 /** Peripheral CMT base address */
658 #define CMT_BASE (0x40062000u)
659 /** Peripheral CMT base pointer */
660 #define CMT ((CMT_Type *)CMT_BASE)
661
662 /**
663 * @}
664 */ /* end of group CMT_Peripheral_Access_Layer */
665
666
667 /* ----------------------------------------------------------------------------
668 -- CRC Peripheral Access Layer
669 ---------------------------------------------------------------------------- */
670
671 /**
672 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
673 * @{
674 */
675
676 /** CRC - Register Layout Typedef */
677 typedef struct {
678 union { /* offset: 0x0 */
679 struct { /* offset: 0x0 */
680 __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
681 __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
682 } ACCESS16BIT;
683 __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
684 struct { /* offset: 0x0 */
685 __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
686 __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
687 __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
688 __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
689 } ACCESS8BIT;
690 };
691 union { /* offset: 0x4 */
692 struct { /* offset: 0x4 */
693 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
694 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
695 } GPOLY_ACCESS16BIT;
696 __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
697 struct { /* offset: 0x4 */
698 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
699 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
700 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
701 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
702 } GPOLY_ACCESS8BIT;
703 };
704 union { /* offset: 0x8 */
705 __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
706 struct { /* offset: 0x8 */
707 uint8_t RESERVED_0[3];
708 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
709 } CTRL_ACCESS8BIT;
710 };
711 } CRC_Type;
712
713 /* ----------------------------------------------------------------------------
714 -- CRC Register Masks
715 ---------------------------------------------------------------------------- */
716
717 /**
718 * @addtogroup CRC_Register_Masks CRC Register Masks
719 * @{
720 */
721
722 /* CRCL Bit Fields */
723 #define CRC_CRCL_CRCL_MASK 0xFFFFu
724 #define CRC_CRCL_CRCL_SHIFT 0
725 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
726 /* CRCH Bit Fields */
727 #define CRC_CRCH_CRCH_MASK 0xFFFFu
728 #define CRC_CRCH_CRCH_SHIFT 0
729 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
730 /* CRC Bit Fields */
731 #define CRC_CRC_LL_MASK 0xFFu
732 #define CRC_CRC_LL_SHIFT 0
733 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
734 #define CRC_CRC_LU_MASK 0xFF00u
735 #define CRC_CRC_LU_SHIFT 8
736 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
737 #define CRC_CRC_HL_MASK 0xFF0000u
738 #define CRC_CRC_HL_SHIFT 16
739 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
740 #define CRC_CRC_HU_MASK 0xFF000000u
741 #define CRC_CRC_HU_SHIFT 24
742 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
743 /* CRCLL Bit Fields */
744 #define CRC_CRCLL_CRCLL_MASK 0xFFu
745 #define CRC_CRCLL_CRCLL_SHIFT 0
746 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
747 /* CRCLU Bit Fields */
748 #define CRC_CRCLU_CRCLU_MASK 0xFFu
749 #define CRC_CRCLU_CRCLU_SHIFT 0
750 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
751 /* CRCHL Bit Fields */
752 #define CRC_CRCHL_CRCHL_MASK 0xFFu
753 #define CRC_CRCHL_CRCHL_SHIFT 0
754 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
755 /* CRCHU Bit Fields */
756 #define CRC_CRCHU_CRCHU_MASK 0xFFu
757 #define CRC_CRCHU_CRCHU_SHIFT 0
758 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
759 /* GPOLYL Bit Fields */
760 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
761 #define CRC_GPOLYL_GPOLYL_SHIFT 0
762 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
763 /* GPOLYH Bit Fields */
764 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
765 #define CRC_GPOLYH_GPOLYH_SHIFT 0
766 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
767 /* GPOLY Bit Fields */
768 #define CRC_GPOLY_LOW_MASK 0xFFFFu
769 #define CRC_GPOLY_LOW_SHIFT 0
770 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
771 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
772 #define CRC_GPOLY_HIGH_SHIFT 16
773 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
774 /* GPOLYLL Bit Fields */
775 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
776 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
777 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
778 /* GPOLYLU Bit Fields */
779 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
780 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
781 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
782 /* GPOLYHL Bit Fields */
783 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
784 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
785 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
786 /* GPOLYHU Bit Fields */
787 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
788 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
789 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
790 /* CTRL Bit Fields */
791 #define CRC_CTRL_TCRC_MASK 0x1000000u
792 #define CRC_CTRL_TCRC_SHIFT 24
793 #define CRC_CTRL_WAS_MASK 0x2000000u
794 #define CRC_CTRL_WAS_SHIFT 25
795 #define CRC_CTRL_FXOR_MASK 0x4000000u
796 #define CRC_CTRL_FXOR_SHIFT 26
797 #define CRC_CTRL_TOTR_MASK 0x30000000u
798 #define CRC_CTRL_TOTR_SHIFT 28
799 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
800 #define CRC_CTRL_TOT_MASK 0xC0000000u
801 #define CRC_CTRL_TOT_SHIFT 30
802 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
803 /* CTRLHU Bit Fields */
804 #define CRC_CTRLHU_TCRC_MASK 0x1u
805 #define CRC_CTRLHU_TCRC_SHIFT 0
806 #define CRC_CTRLHU_WAS_MASK 0x2u
807 #define CRC_CTRLHU_WAS_SHIFT 1
808 #define CRC_CTRLHU_FXOR_MASK 0x4u
809 #define CRC_CTRLHU_FXOR_SHIFT 2
810 #define CRC_CTRLHU_TOTR_MASK 0x30u
811 #define CRC_CTRLHU_TOTR_SHIFT 4
812 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
813 #define CRC_CTRLHU_TOT_MASK 0xC0u
814 #define CRC_CTRLHU_TOT_SHIFT 6
815 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
816
817 /**
818 * @}
819 */ /* end of group CRC_Register_Masks */
820
821
822 /* CRC - Peripheral instance base addresses */
823 /** Peripheral CRC base address */
824 #define CRC_BASE (0x40032000u)
825 /** Peripheral CRC base pointer */
826 #define CRC0 ((CRC_Type *)CRC_BASE)
827
828 /**
829 * @}
830 */ /* end of group CRC_Peripheral_Access_Layer */
831
832
833 /* ----------------------------------------------------------------------------
834 -- DAC Peripheral Access Layer
835 ---------------------------------------------------------------------------- */
836
837 /**
838 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
839 * @{
840 */
841
842 /** DAC - Register Layout Typedef */
843 typedef struct {
844 struct { /* offset: 0x0, array step: 0x2 */
845 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
846 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
847 } DAT[16];
848 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
849 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
850 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
851 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
852 } DAC_Type, *DAC_MemMapPtr;
853
854 /* ----------------------------------------------------------------------------
855 -- DAC Register Masks
856 ---------------------------------------------------------------------------- */
857
858 /**
859 * @addtogroup DAC_Register_Masks DAC Register Masks
860 * @{
861 */
862
863 /* DATL Bit Fields */
864 #define DAC_DATL_DATA0_MASK 0xFFu
865 #define DAC_DATL_DATA0_SHIFT 0
866 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
867 /* DATH Bit Fields */
868 #define DAC_DATH_DATA1_MASK 0xFu
869 #define DAC_DATH_DATA1_SHIFT 0
870 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
871 /* SR Bit Fields */
872 #define DAC_SR_DACBFRPBF_MASK 0x1u
873 #define DAC_SR_DACBFRPBF_SHIFT 0
874 #define DAC_SR_DACBFRPTF_MASK 0x2u
875 #define DAC_SR_DACBFRPTF_SHIFT 1
876 #define DAC_SR_DACBFWMF_MASK 0x4u
877 #define DAC_SR_DACBFWMF_SHIFT 2
878 /* C0 Bit Fields */
879 #define DAC_C0_DACBBIEN_MASK 0x1u
880 #define DAC_C0_DACBBIEN_SHIFT 0
881 #define DAC_C0_DACBTIEN_MASK 0x2u
882 #define DAC_C0_DACBTIEN_SHIFT 1
883 #define DAC_C0_DACBWIEN_MASK 0x4u
884 #define DAC_C0_DACBWIEN_SHIFT 2
885 #define DAC_C0_LPEN_MASK 0x8u
886 #define DAC_C0_LPEN_SHIFT 3
887 #define DAC_C0_DACSWTRG_MASK 0x10u
888 #define DAC_C0_DACSWTRG_SHIFT 4
889 #define DAC_C0_DACTRGSEL_MASK 0x20u
890 #define DAC_C0_DACTRGSEL_SHIFT 5
891 #define DAC_C0_DACRFS_MASK 0x40u
892 #define DAC_C0_DACRFS_SHIFT 6
893 #define DAC_C0_DACEN_MASK 0x80u
894 #define DAC_C0_DACEN_SHIFT 7
895 /* C1 Bit Fields */
896 #define DAC_C1_DACBFEN_MASK 0x1u
897 #define DAC_C1_DACBFEN_SHIFT 0
898 #define DAC_C1_DACBFMD_MASK 0x6u
899 #define DAC_C1_DACBFMD_SHIFT 1
900 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
901 #define DAC_C1_DACBFWM_MASK 0x18u
902 #define DAC_C1_DACBFWM_SHIFT 3
903 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
904 #define DAC_C1_DMAEN_MASK 0x80u
905 #define DAC_C1_DMAEN_SHIFT 7
906 /* C2 Bit Fields */
907 #define DAC_C2_DACBFUP_MASK 0xFu
908 #define DAC_C2_DACBFUP_SHIFT 0
909 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
910 #define DAC_C2_DACBFRP_MASK 0xF0u
911 #define DAC_C2_DACBFRP_SHIFT 4
912 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
913
914 /**
915 * @}
916 */ /* end of group DAC_Register_Masks */
917
918
919 /* DAC - Peripheral instance base addresses */
920 /** Peripheral DAC0 base address */
921 #define DAC0_BASE (0x400CC000u)
922 /** Peripheral DAC0 base pointer */
923 #define DAC0 ((DAC_Type *)DAC0_BASE)
924 /** Array initializer of DAC peripheral base pointers */
925 #define DAC_BASES { DAC0 }
926
927 /**
928 * @}
929 */ /* end of group DAC_Peripheral_Access_Layer */
930
931
932 /* ----------------------------------------------------------------------------
933 -- DMA Peripheral Access Layer
934 ---------------------------------------------------------------------------- */
935
936 /**
937 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
938 * @{
939 */
940
941 /** DMA - Register Layout Typedef */
942 typedef struct {
943 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
944 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
945 uint8_t RESERVED_0[4];
946 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
947 uint8_t RESERVED_1[4];
948 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
949 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
950 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
951 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
952 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
953 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
954 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
955 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
956 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
957 uint8_t RESERVED_2[4];
958 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
959 uint8_t RESERVED_3[4];
960 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
961 uint8_t RESERVED_4[4];
962 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
963 uint8_t RESERVED_5[200];
964 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
965 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
966 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
967 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
968 uint8_t RESERVED_6[3836];
969 struct { /* offset: 0x1000, array step: 0x20 */
970 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
971 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
972 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
973 union { /* offset: 0x1008, array step: 0x20 */
974 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
975 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
976 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
977 };
978 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
979 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
980 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
981 union { /* offset: 0x1016, array step: 0x20 */
982 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
983 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
984 };
985 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
986 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
987 union { /* offset: 0x101E, array step: 0x20 */
988 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
989 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
990 };
991 } TCD[4];
992 } DMA_Type;
993
994 /* ----------------------------------------------------------------------------
995 -- DMA Register Masks
996 ---------------------------------------------------------------------------- */
997
998 /**
999 * @addtogroup DMA_Register_Masks DMA Register Masks
1000 * @{
1001 */
1002
1003 /* CR Bit Fields */
1004 #define DMA_CR_EDBG_MASK 0x2u
1005 #define DMA_CR_EDBG_SHIFT 1
1006 #define DMA_CR_ERCA_MASK 0x4u
1007 #define DMA_CR_ERCA_SHIFT 2
1008 #define DMA_CR_HOE_MASK 0x10u
1009 #define DMA_CR_HOE_SHIFT 4
1010 #define DMA_CR_HALT_MASK 0x20u
1011 #define DMA_CR_HALT_SHIFT 5
1012 #define DMA_CR_CLM_MASK 0x40u
1013 #define DMA_CR_CLM_SHIFT 6
1014 #define DMA_CR_EMLM_MASK 0x80u
1015 #define DMA_CR_EMLM_SHIFT 7
1016 #define DMA_CR_ECX_MASK 0x10000u
1017 #define DMA_CR_ECX_SHIFT 16
1018 #define DMA_CR_CX_MASK 0x20000u
1019 #define DMA_CR_CX_SHIFT 17
1020 /* ES Bit Fields */
1021 #define DMA_ES_DBE_MASK 0x1u
1022 #define DMA_ES_DBE_SHIFT 0
1023 #define DMA_ES_SBE_MASK 0x2u
1024 #define DMA_ES_SBE_SHIFT 1
1025 #define DMA_ES_SGE_MASK 0x4u
1026 #define DMA_ES_SGE_SHIFT 2
1027 #define DMA_ES_NCE_MASK 0x8u
1028 #define DMA_ES_NCE_SHIFT 3
1029 #define DMA_ES_DOE_MASK 0x10u
1030 #define DMA_ES_DOE_SHIFT 4
1031 #define DMA_ES_DAE_MASK 0x20u
1032 #define DMA_ES_DAE_SHIFT 5
1033 #define DMA_ES_SOE_MASK 0x40u
1034 #define DMA_ES_SOE_SHIFT 6
1035 #define DMA_ES_SAE_MASK 0x80u
1036 #define DMA_ES_SAE_SHIFT 7
1037 #define DMA_ES_ERRCHN_MASK 0xF00u
1038 #define DMA_ES_ERRCHN_SHIFT 8
1039 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
1040 #define DMA_ES_CPE_MASK 0x4000u
1041 #define DMA_ES_CPE_SHIFT 14
1042 #define DMA_ES_ECX_MASK 0x10000u
1043 #define DMA_ES_ECX_SHIFT 16
1044 #define DMA_ES_VLD_MASK 0x80000000u
1045 #define DMA_ES_VLD_SHIFT 31
1046 /* ERQ Bit Fields */
1047 #define DMA_ERQ_ERQ0_MASK 0x1u
1048 #define DMA_ERQ_ERQ0_SHIFT 0
1049 #define DMA_ERQ_ERQ1_MASK 0x2u
1050 #define DMA_ERQ_ERQ1_SHIFT 1
1051 #define DMA_ERQ_ERQ2_MASK 0x4u
1052 #define DMA_ERQ_ERQ2_SHIFT 2
1053 #define DMA_ERQ_ERQ3_MASK 0x8u
1054 #define DMA_ERQ_ERQ3_SHIFT 3
1055 /* EEI Bit Fields */
1056 #define DMA_EEI_EEI0_MASK 0x1u
1057 #define DMA_EEI_EEI0_SHIFT 0
1058 #define DMA_EEI_EEI1_MASK 0x2u
1059 #define DMA_EEI_EEI1_SHIFT 1
1060 #define DMA_EEI_EEI2_MASK 0x4u
1061 #define DMA_EEI_EEI2_SHIFT 2
1062 #define DMA_EEI_EEI3_MASK 0x8u
1063 #define DMA_EEI_EEI3_SHIFT 3
1064 /* CEEI Bit Fields */
1065 #define DMA_CEEI_CEEI_MASK 0xFu
1066 #define DMA_CEEI_CEEI_SHIFT 0
1067 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
1068 #define DMA_CEEI_CAEE_MASK 0x40u
1069 #define DMA_CEEI_CAEE_SHIFT 6
1070 #define DMA_CEEI_NOP_MASK 0x80u
1071 #define DMA_CEEI_NOP_SHIFT 7
1072 /* SEEI Bit Fields */
1073 #define DMA_SEEI_SEEI_MASK 0xFu
1074 #define DMA_SEEI_SEEI_SHIFT 0
1075 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
1076 #define DMA_SEEI_SAEE_MASK 0x40u
1077 #define DMA_SEEI_SAEE_SHIFT 6
1078 #define DMA_SEEI_NOP_MASK 0x80u
1079 #define DMA_SEEI_NOP_SHIFT 7
1080 /* CERQ Bit Fields */
1081 #define DMA_CERQ_CERQ_MASK 0xFu
1082 #define DMA_CERQ_CERQ_SHIFT 0
1083 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
1084 #define DMA_CERQ_CAER_MASK 0x40u
1085 #define DMA_CERQ_CAER_SHIFT 6
1086 #define DMA_CERQ_NOP_MASK 0x80u
1087 #define DMA_CERQ_NOP_SHIFT 7
1088 /* SERQ Bit Fields */
1089 #define DMA_SERQ_SERQ_MASK 0xFu
1090 #define DMA_SERQ_SERQ_SHIFT 0
1091 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
1092 #define DMA_SERQ_SAER_MASK 0x40u
1093 #define DMA_SERQ_SAER_SHIFT 6
1094 #define DMA_SERQ_NOP_MASK 0x80u
1095 #define DMA_SERQ_NOP_SHIFT 7
1096 /* CDNE Bit Fields */
1097 #define DMA_CDNE_CDNE_MASK 0xFu
1098 #define DMA_CDNE_CDNE_SHIFT 0
1099 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
1100 #define DMA_CDNE_CADN_MASK 0x40u
1101 #define DMA_CDNE_CADN_SHIFT 6
1102 #define DMA_CDNE_NOP_MASK 0x80u
1103 #define DMA_CDNE_NOP_SHIFT 7
1104 /* SSRT Bit Fields */
1105 #define DMA_SSRT_SSRT_MASK 0xFu
1106 #define DMA_SSRT_SSRT_SHIFT 0
1107 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
1108 #define DMA_SSRT_SAST_MASK 0x40u
1109 #define DMA_SSRT_SAST_SHIFT 6
1110 #define DMA_SSRT_NOP_MASK 0x80u
1111 #define DMA_SSRT_NOP_SHIFT 7
1112 /* CERR Bit Fields */
1113 #define DMA_CERR_CERR_MASK 0xFu
1114 #define DMA_CERR_CERR_SHIFT 0
1115 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
1116 #define DMA_CERR_CAEI_MASK 0x40u
1117 #define DMA_CERR_CAEI_SHIFT 6
1118 #define DMA_CERR_NOP_MASK 0x80u
1119 #define DMA_CERR_NOP_SHIFT 7
1120 /* CINT Bit Fields */
1121 #define DMA_CINT_CINT_MASK 0xFu
1122 #define DMA_CINT_CINT_SHIFT 0
1123 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
1124 #define DMA_CINT_CAIR_MASK 0x40u
1125 #define DMA_CINT_CAIR_SHIFT 6
1126 #define DMA_CINT_NOP_MASK 0x80u
1127 #define DMA_CINT_NOP_SHIFT 7
1128 /* INT Bit Fields */
1129 #define DMA_INT_INT0_MASK 0x1u
1130 #define DMA_INT_INT0_SHIFT 0
1131 #define DMA_INT_INT1_MASK 0x2u
1132 #define DMA_INT_INT1_SHIFT 1
1133 #define DMA_INT_INT2_MASK 0x4u
1134 #define DMA_INT_INT2_SHIFT 2
1135 #define DMA_INT_INT3_MASK 0x8u
1136 #define DMA_INT_INT3_SHIFT 3
1137 /* ERR Bit Fields */
1138 #define DMA_ERR_ERR0_MASK 0x1u
1139 #define DMA_ERR_ERR0_SHIFT 0
1140 #define DMA_ERR_ERR1_MASK 0x2u
1141 #define DMA_ERR_ERR1_SHIFT 1
1142 #define DMA_ERR_ERR2_MASK 0x4u
1143 #define DMA_ERR_ERR2_SHIFT 2
1144 #define DMA_ERR_ERR3_MASK 0x8u
1145 #define DMA_ERR_ERR3_SHIFT 3
1146 /* HRS Bit Fields */
1147 #define DMA_HRS_HRS0_MASK 0x1u
1148 #define DMA_HRS_HRS0_SHIFT 0
1149 #define DMA_HRS_HRS1_MASK 0x2u
1150 #define DMA_HRS_HRS1_SHIFT 1
1151 #define DMA_HRS_HRS2_MASK 0x4u
1152 #define DMA_HRS_HRS2_SHIFT 2
1153 #define DMA_HRS_HRS3_MASK 0x8u
1154 #define DMA_HRS_HRS3_SHIFT 3
1155 /* DCHPRI3 Bit Fields */
1156 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
1157 #define DMA_DCHPRI3_CHPRI_SHIFT 0
1158 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
1159 #define DMA_DCHPRI3_DPA_MASK 0x40u
1160 #define DMA_DCHPRI3_DPA_SHIFT 6
1161 #define DMA_DCHPRI3_ECP_MASK 0x80u
1162 #define DMA_DCHPRI3_ECP_SHIFT 7
1163 /* DCHPRI2 Bit Fields */
1164 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
1165 #define DMA_DCHPRI2_CHPRI_SHIFT 0
1166 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
1167 #define DMA_DCHPRI2_DPA_MASK 0x40u
1168 #define DMA_DCHPRI2_DPA_SHIFT 6
1169 #define DMA_DCHPRI2_ECP_MASK 0x80u
1170 #define DMA_DCHPRI2_ECP_SHIFT 7
1171 /* DCHPRI1 Bit Fields */
1172 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
1173 #define DMA_DCHPRI1_CHPRI_SHIFT 0
1174 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
1175 #define DMA_DCHPRI1_DPA_MASK 0x40u
1176 #define DMA_DCHPRI1_DPA_SHIFT 6
1177 #define DMA_DCHPRI1_ECP_MASK 0x80u
1178 #define DMA_DCHPRI1_ECP_SHIFT 7
1179 /* DCHPRI0 Bit Fields */
1180 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
1181 #define DMA_DCHPRI0_CHPRI_SHIFT 0
1182 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
1183 #define DMA_DCHPRI0_DPA_MASK 0x40u
1184 #define DMA_DCHPRI0_DPA_SHIFT 6
1185 #define DMA_DCHPRI0_ECP_MASK 0x80u
1186 #define DMA_DCHPRI0_ECP_SHIFT 7
1187 /* SADDR Bit Fields */
1188 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
1189 #define DMA_SADDR_SADDR_SHIFT 0
1190 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
1191 /* SOFF Bit Fields */
1192 #define DMA_SOFF_SOFF_MASK 0xFFFFu
1193 #define DMA_SOFF_SOFF_SHIFT 0
1194 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
1195 /* ATTR Bit Fields */
1196 #define DMA_ATTR_DSIZE_MASK 0x7u
1197 #define DMA_ATTR_DSIZE_SHIFT 0
1198 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
1199 #define DMA_ATTR_DMOD_MASK 0xF8u
1200 #define DMA_ATTR_DMOD_SHIFT 3
1201 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
1202 #define DMA_ATTR_SSIZE_MASK 0x700u
1203 #define DMA_ATTR_SSIZE_SHIFT 8
1204 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
1205 #define DMA_ATTR_SMOD_MASK 0xF800u
1206 #define DMA_ATTR_SMOD_SHIFT 11
1207 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
1208 /* NBYTES_MLNO Bit Fields */
1209 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
1210 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
1211 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
1212 /* NBYTES_MLOFFNO Bit Fields */
1213 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
1214 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
1215 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
1216 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
1217 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
1218 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
1219 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
1220 /* NBYTES_MLOFFYES Bit Fields */
1221 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
1222 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
1223 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
1224 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
1225 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
1226 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
1227 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
1228 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
1229 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
1230 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
1231 /* SLAST Bit Fields */
1232 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
1233 #define DMA_SLAST_SLAST_SHIFT 0
1234 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
1235 /* DADDR Bit Fields */
1236 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
1237 #define DMA_DADDR_DADDR_SHIFT 0
1238 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
1239 /* DOFF Bit Fields */
1240 #define DMA_DOFF_DOFF_MASK 0xFFFFu
1241 #define DMA_DOFF_DOFF_SHIFT 0
1242 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
1243 /* CITER_ELINKNO Bit Fields */
1244 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
1245 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
1246 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
1247 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
1248 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
1249 /* CITER_ELINKYES Bit Fields */
1250 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
1251 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
1252 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
1253 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
1254 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
1255 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
1256 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
1257 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
1258 /* DLAST_SGA Bit Fields */
1259 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
1260 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
1261 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
1262 /* CSR Bit Fields */
1263 #define DMA_CSR_START_MASK 0x1u
1264 #define DMA_CSR_START_SHIFT 0
1265 #define DMA_CSR_INTMAJOR_MASK 0x2u
1266 #define DMA_CSR_INTMAJOR_SHIFT 1
1267 #define DMA_CSR_INTHALF_MASK 0x4u
1268 #define DMA_CSR_INTHALF_SHIFT 2
1269 #define DMA_CSR_DREQ_MASK 0x8u
1270 #define DMA_CSR_DREQ_SHIFT 3
1271 #define DMA_CSR_ESG_MASK 0x10u
1272 #define DMA_CSR_ESG_SHIFT 4
1273 #define DMA_CSR_MAJORELINK_MASK 0x20u
1274 #define DMA_CSR_MAJORELINK_SHIFT 5
1275 #define DMA_CSR_ACTIVE_MASK 0x40u
1276 #define DMA_CSR_ACTIVE_SHIFT 6
1277 #define DMA_CSR_DONE_MASK 0x80u
1278 #define DMA_CSR_DONE_SHIFT 7
1279 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
1280 #define DMA_CSR_MAJORLINKCH_SHIFT 8
1281 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
1282 #define DMA_CSR_BWC_MASK 0xC000u
1283 #define DMA_CSR_BWC_SHIFT 14
1284 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
1285 /* BITER_ELINKNO Bit Fields */
1286 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
1287 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
1288 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
1289 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
1290 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
1291 /* BITER_ELINKYES Bit Fields */
1292 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
1293 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
1294 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
1295 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
1296 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
1297 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
1298 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
1299 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
1300
1301 /**
1302 * @}
1303 */ /* end of group DMA_Register_Masks */
1304
1305
1306 /* DMA - Peripheral instance base addresses */
1307 /** Peripheral DMA base address */
1308 #define DMA_BASE (0x40008000u)
1309 /** Peripheral DMA base pointer */
1310 #define DMA0 ((DMA_Type *)DMA_BASE)
1311
1312 /**
1313 * @}
1314 */ /* end of group DMA_Peripheral_Access_Layer */
1315
1316
1317 /* ----------------------------------------------------------------------------
1318 -- DMAMUX Peripheral Access Layer
1319 ---------------------------------------------------------------------------- */
1320
1321 /**
1322 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
1323 * @{
1324 */
1325
1326 /** DMAMUX - Register Layout Typedef */
1327 typedef struct {
1328 __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
1329 } DMAMUX_Type;
1330
1331 /* ----------------------------------------------------------------------------
1332 -- DMAMUX Register Masks
1333 ---------------------------------------------------------------------------- */
1334
1335 /**
1336 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
1337 * @{
1338 */
1339
1340 /* CHCFG Bit Fields */
1341 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
1342 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
1343 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
1344 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
1345 #define DMAMUX_CHCFG_TRIG_SHIFT 6
1346 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
1347 #define DMAMUX_CHCFG_ENBL_SHIFT 7
1348
1349 /**
1350 * @}
1351 */ /* end of group DMAMUX_Register_Masks */
1352
1353
1354 /* DMAMUX - Peripheral instance base addresses */
1355 /** Peripheral DMAMUX base address */
1356 #define DMAMUX_BASE (0x40021000u)
1357 /** Peripheral DMAMUX base pointer */
1358 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
1359
1360 /**
1361 * @}
1362 */ /* end of group DMAMUX_Peripheral_Access_Layer */
1363
1364
1365 /* ----------------------------------------------------------------------------
1366 -- EWM Peripheral Access Layer
1367 ---------------------------------------------------------------------------- */
1368
1369 /**
1370 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
1371 * @{
1372 */
1373
1374 /** EWM - Register Layout Typedef */
1375 typedef struct {
1376 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
1377 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
1378 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
1379 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
1380 } EWM_Type;
1381
1382 /* ----------------------------------------------------------------------------
1383 -- EWM Register Masks
1384 ---------------------------------------------------------------------------- */
1385
1386 /**
1387 * @addtogroup EWM_Register_Masks EWM Register Masks
1388 * @{
1389 */
1390
1391 /* CTRL Bit Fields */
1392 #define EWM_CTRL_EWMEN_MASK 0x1u
1393 #define EWM_CTRL_EWMEN_SHIFT 0
1394 #define EWM_CTRL_ASSIN_MASK 0x2u
1395 #define EWM_CTRL_ASSIN_SHIFT 1
1396 #define EWM_CTRL_INEN_MASK 0x4u
1397 #define EWM_CTRL_INEN_SHIFT 2
1398 #define EWM_CTRL_INTEN_MASK 0x8u
1399 #define EWM_CTRL_INTEN_SHIFT 3
1400 /* SERV Bit Fields */
1401 #define EWM_SERV_SERVICE_MASK 0xFFu
1402 #define EWM_SERV_SERVICE_SHIFT 0
1403 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
1404 /* CMPL Bit Fields */
1405 #define EWM_CMPL_COMPAREL_MASK 0xFFu
1406 #define EWM_CMPL_COMPAREL_SHIFT 0
1407 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
1408 /* CMPH Bit Fields */
1409 #define EWM_CMPH_COMPAREH_MASK 0xFFu
1410 #define EWM_CMPH_COMPAREH_SHIFT 0
1411 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
1412
1413 /**
1414 * @}
1415 */ /* end of group EWM_Register_Masks */
1416
1417
1418 /* EWM - Peripheral instance base addresses */
1419 /** Peripheral EWM base address */
1420 #define EWM_BASE (0x40061000u)
1421 /** Peripheral EWM base pointer */
1422 #define EWM ((EWM_Type *)EWM_BASE)
1423
1424 /**
1425 * @}
1426 */ /* end of group EWM_Peripheral_Access_Layer */
1427
1428
1429 /* ----------------------------------------------------------------------------
1430 -- FMC Peripheral Access Layer
1431 ---------------------------------------------------------------------------- */
1432
1433 /**
1434 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
1435 * @{
1436 */
1437
1438 /** FMC - Register Layout Typedef */
1439 typedef struct {
1440 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
1441 __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
1442 uint8_t RESERVED_0[248];
1443 struct { /* offset: 0x100, array step: 0x20 */
1444 __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
1445 uint8_t RESERVED_0[24];
1446 } TAG_WAY[4];
1447 uint8_t RESERVED_1[132];
1448 struct { /* offset: 0x204, array step: 0x8 */
1449 __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
1450 uint8_t RESERVED_0[4];
1451 } DATAW0S[2];
1452 uint8_t RESERVED_2[48];
1453 struct { /* offset: 0x244, array step: 0x8 */
1454 __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
1455 uint8_t RESERVED_0[4];
1456 } DATAW1S[2];
1457 uint8_t RESERVED_3[48];
1458 struct { /* offset: 0x284, array step: 0x8 */
1459 __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
1460 uint8_t RESERVED_0[4];
1461 } DATAW2S[2];
1462 uint8_t RESERVED_4[48];
1463 struct { /* offset: 0x2C4, array step: 0x8 */
1464 __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
1465 uint8_t RESERVED_0[4];
1466 } DATAW3S[2];
1467 } FMC_Type;
1468
1469 /* ----------------------------------------------------------------------------
1470 -- FMC Register Masks
1471 ---------------------------------------------------------------------------- */
1472
1473 /**
1474 * @addtogroup FMC_Register_Masks FMC Register Masks
1475 * @{
1476 */
1477
1478 /* PFAPR Bit Fields */
1479 #define FMC_PFAPR_M0AP_MASK 0x3u
1480 #define FMC_PFAPR_M0AP_SHIFT 0
1481 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
1482 #define FMC_PFAPR_M1AP_MASK 0xCu
1483 #define FMC_PFAPR_M1AP_SHIFT 2
1484 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
1485 #define FMC_PFAPR_M2AP_MASK 0x30u
1486 #define FMC_PFAPR_M2AP_SHIFT 4
1487 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
1488 #define FMC_PFAPR_M3AP_MASK 0xC0u
1489 #define FMC_PFAPR_M3AP_SHIFT 6
1490 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
1491 #define FMC_PFAPR_M0PFD_MASK 0x10000u
1492 #define FMC_PFAPR_M0PFD_SHIFT 16
1493 #define FMC_PFAPR_M1PFD_MASK 0x20000u
1494 #define FMC_PFAPR_M1PFD_SHIFT 17
1495 #define FMC_PFAPR_M2PFD_MASK 0x40000u
1496 #define FMC_PFAPR_M2PFD_SHIFT 18
1497 #define FMC_PFAPR_M3PFD_MASK 0x80000u
1498 #define FMC_PFAPR_M3PFD_SHIFT 19
1499 /* PFB0CR Bit Fields */
1500 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
1501 #define FMC_PFB0CR_B0SEBE_SHIFT 0
1502 #define FMC_PFB0CR_B0IPE_MASK 0x2u
1503 #define FMC_PFB0CR_B0IPE_SHIFT 1
1504 #define FMC_PFB0CR_B0DPE_MASK 0x4u
1505 #define FMC_PFB0CR_B0DPE_SHIFT 2
1506 #define FMC_PFB0CR_B0ICE_MASK 0x8u
1507 #define FMC_PFB0CR_B0ICE_SHIFT 3
1508 #define FMC_PFB0CR_B0DCE_MASK 0x10u
1509 #define FMC_PFB0CR_B0DCE_SHIFT 4
1510 #define FMC_PFB0CR_CRC_MASK 0xE0u
1511 #define FMC_PFB0CR_CRC_SHIFT 5
1512 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
1513 #define FMC_PFB0CR_B0MW_MASK 0x60000u
1514 #define FMC_PFB0CR_B0MW_SHIFT 17
1515 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
1516 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
1517 #define FMC_PFB0CR_S_B_INV_SHIFT 19
1518 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
1519 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
1520 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
1521 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
1522 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
1523 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
1524 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
1525 #define FMC_PFB0CR_B0RWSC_SHIFT 28
1526 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
1527 /* TAGVD Bit Fields */
1528 #define FMC_TAGVD_valid_MASK 0x1u
1529 #define FMC_TAGVD_valid_SHIFT 0
1530 #define FMC_TAGVD_tag_MASK 0x7FFC0u
1531 #define FMC_TAGVD_tag_SHIFT 6
1532 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
1533 /* DATAW0S Bit Fields */
1534 #define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
1535 #define FMC_DATAW0S_data_SHIFT 0
1536 #define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
1537 /* DATAW1S Bit Fields */
1538 #define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
1539 #define FMC_DATAW1S_data_SHIFT 0
1540 #define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
1541 /* DATAW2S Bit Fields */
1542 #define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
1543 #define FMC_DATAW2S_data_SHIFT 0
1544 #define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
1545 /* DATAW3S Bit Fields */
1546 #define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
1547 #define FMC_DATAW3S_data_SHIFT 0
1548 #define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
1549
1550 /**
1551 * @}
1552 */ /* end of group FMC_Register_Masks */
1553
1554
1555 /* FMC - Peripheral instance base addresses */
1556 /** Peripheral FMC base address */
1557 #define FMC_BASE (0x4001F000u)
1558 /** Peripheral FMC base pointer */
1559 #define FMC ((FMC_Type *)FMC_BASE)
1560
1561 /**
1562 * @}
1563 */ /* end of group FMC_Peripheral_Access_Layer */
1564
1565
1566 /* ----------------------------------------------------------------------------
1567 -- FTFL Peripheral Access Layer
1568 ---------------------------------------------------------------------------- */
1569
1570 /**
1571 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
1572 * @{
1573 */
1574
1575 /** FTFL - Register Layout Typedef */
1576 typedef struct {
1577 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
1578 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
1579 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
1580 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
1581 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
1582 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
1583 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
1584 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
1585 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
1586 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
1587 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
1588 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
1589 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
1590 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
1591 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
1592 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
1593 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
1594 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
1595 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
1596 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
1597 uint8_t RESERVED_0[2];
1598 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
1599 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
1600 } FTFL_Type;
1601
1602 /* ----------------------------------------------------------------------------
1603 -- FTFL Register Masks
1604 ---------------------------------------------------------------------------- */
1605
1606 /**
1607 * @addtogroup FTFL_Register_Masks FTFL Register Masks
1608 * @{
1609 */
1610
1611 /* FSTAT Bit Fields */
1612 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
1613 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
1614 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
1615 #define FTFL_FSTAT_FPVIOL_SHIFT 4
1616 #define FTFL_FSTAT_ACCERR_MASK 0x20u
1617 #define FTFL_FSTAT_ACCERR_SHIFT 5
1618 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
1619 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
1620 #define FTFL_FSTAT_CCIF_MASK 0x80u
1621 #define FTFL_FSTAT_CCIF_SHIFT 7
1622 /* FCNFG Bit Fields */
1623 #define FTFL_FCNFG_EEERDY_MASK 0x1u
1624 #define FTFL_FCNFG_EEERDY_SHIFT 0
1625 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
1626 #define FTFL_FCNFG_RAMRDY_SHIFT 1
1627 #define FTFL_FCNFG_PFLSH_MASK 0x4u
1628 #define FTFL_FCNFG_PFLSH_SHIFT 2
1629 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
1630 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
1631 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
1632 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
1633 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
1634 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
1635 #define FTFL_FCNFG_CCIE_MASK 0x80u
1636 #define FTFL_FCNFG_CCIE_SHIFT 7
1637 /* FSEC Bit Fields */
1638 #define FTFL_FSEC_SEC_MASK 0x3u
1639 #define FTFL_FSEC_SEC_SHIFT 0
1640 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
1641 #define FTFL_FSEC_FSLACC_MASK 0xCu
1642 #define FTFL_FSEC_FSLACC_SHIFT 2
1643 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
1644 #define FTFL_FSEC_MEEN_MASK 0x30u
1645 #define FTFL_FSEC_MEEN_SHIFT 4
1646 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
1647 #define FTFL_FSEC_KEYEN_MASK 0xC0u
1648 #define FTFL_FSEC_KEYEN_SHIFT 6
1649 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
1650 /* FOPT Bit Fields */
1651 #define FTFL_FOPT_OPT_MASK 0xFFu
1652 #define FTFL_FOPT_OPT_SHIFT 0
1653 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
1654 /* FCCOB3 Bit Fields */
1655 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
1656 #define FTFL_FCCOB3_CCOBn_SHIFT 0
1657 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
1658 /* FCCOB2 Bit Fields */
1659 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
1660 #define FTFL_FCCOB2_CCOBn_SHIFT 0
1661 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
1662 /* FCCOB1 Bit Fields */
1663 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
1664 #define FTFL_FCCOB1_CCOBn_SHIFT 0
1665 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
1666 /* FCCOB0 Bit Fields */
1667 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
1668 #define FTFL_FCCOB0_CCOBn_SHIFT 0
1669 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
1670 /* FCCOB7 Bit Fields */
1671 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
1672 #define FTFL_FCCOB7_CCOBn_SHIFT 0
1673 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
1674 /* FCCOB6 Bit Fields */
1675 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
1676 #define FTFL_FCCOB6_CCOBn_SHIFT 0
1677 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
1678 /* FCCOB5 Bit Fields */
1679 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
1680 #define FTFL_FCCOB5_CCOBn_SHIFT 0
1681 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
1682 /* FCCOB4 Bit Fields */
1683 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
1684 #define FTFL_FCCOB4_CCOBn_SHIFT 0
1685 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
1686 /* FCCOBB Bit Fields */
1687 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
1688 #define FTFL_FCCOBB_CCOBn_SHIFT 0
1689 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
1690 /* FCCOBA Bit Fields */
1691 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
1692 #define FTFL_FCCOBA_CCOBn_SHIFT 0
1693 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
1694 /* FCCOB9 Bit Fields */
1695 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
1696 #define FTFL_FCCOB9_CCOBn_SHIFT 0
1697 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
1698 /* FCCOB8 Bit Fields */
1699 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
1700 #define FTFL_FCCOB8_CCOBn_SHIFT 0
1701 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
1702 /* FPROT3 Bit Fields */
1703 #define FTFL_FPROT3_PROT_MASK 0xFFu
1704 #define FTFL_FPROT3_PROT_SHIFT 0
1705 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
1706 /* FPROT2 Bit Fields */
1707 #define FTFL_FPROT2_PROT_MASK 0xFFu
1708 #define FTFL_FPROT2_PROT_SHIFT 0
1709 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
1710 /* FPROT1 Bit Fields */
1711 #define FTFL_FPROT1_PROT_MASK 0xFFu
1712 #define FTFL_FPROT1_PROT_SHIFT 0
1713 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
1714 /* FPROT0 Bit Fields */
1715 #define FTFL_FPROT0_PROT_MASK 0xFFu
1716 #define FTFL_FPROT0_PROT_SHIFT 0
1717 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
1718 /* FEPROT Bit Fields */
1719 #define FTFL_FEPROT_EPROT_MASK 0xFFu
1720 #define FTFL_FEPROT_EPROT_SHIFT 0
1721 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
1722 /* FDPROT Bit Fields */
1723 #define FTFL_FDPROT_DPROT_MASK 0xFFu
1724 #define FTFL_FDPROT_DPROT_SHIFT 0
1725 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
1726
1727 /**
1728 * @}
1729 */ /* end of group FTFL_Register_Masks */
1730
1731
1732 /* FTFL - Peripheral instance base addresses */
1733 /** Peripheral FTFL base address */
1734 #define FTFL_BASE (0x40020000u)
1735 /** Peripheral FTFL base pointer */
1736 #define FTFL ((FTFL_Type *)FTFL_BASE)
1737
1738 /**
1739 * @}
1740 */ /* end of group FTFL_Peripheral_Access_Layer */
1741
1742
1743 /* ----------------------------------------------------------------------------
1744 -- FTM Peripheral Access Layer
1745 ---------------------------------------------------------------------------- */
1746
1747 /**
1748 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
1749 * @{
1750 */
1751
1752 /** FTM - Register Layout Typedef */
1753 typedef struct {
1754 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
1755 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
1756 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
1757 struct { /* offset: 0xC, array step: 0x8 */
1758 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
1759 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
1760 } CONTROLS[8];
1761 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
1762 __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
1763 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
1764 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
1765 __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
1766 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
1767 __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
1768 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
1769 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
1770 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
1771 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
1772 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
1773 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
1774 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
1775 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
1776 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
1777 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
1778 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
1779 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
1780 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
1781 } FTM_Type;
1782
1783 /* ----------------------------------------------------------------------------
1784 -- FTM Register Masks
1785 ---------------------------------------------------------------------------- */
1786
1787 /**
1788 * @addtogroup FTM_Register_Masks FTM Register Masks
1789 * @{
1790 */
1791
1792 /* SC Bit Fields */
1793 #define FTM_SC_PS_MASK 0x7u
1794 #define FTM_SC_PS_SHIFT 0
1795 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
1796 #define FTM_SC_CLKS_MASK 0x18u
1797 #define FTM_SC_CLKS_SHIFT 3
1798 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
1799 #define FTM_SC_CPWMS_MASK 0x20u
1800 #define FTM_SC_CPWMS_SHIFT 5
1801 #define FTM_SC_TOIE_MASK 0x40u
1802 #define FTM_SC_TOIE_SHIFT 6
1803 #define FTM_SC_TOF_MASK 0x80u
1804 #define FTM_SC_TOF_SHIFT 7
1805 /* CNT Bit Fields */
1806 #define FTM_CNT_COUNT_MASK 0xFFFFu
1807 #define FTM_CNT_COUNT_SHIFT 0
1808 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
1809 /* MOD Bit Fields */
1810 #define FTM_MOD_MOD_MASK 0xFFFFu
1811 #define FTM_MOD_MOD_SHIFT 0
1812 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
1813 /* CnSC Bit Fields */
1814 #define FTM_CnSC_DMA_MASK 0x1u
1815 #define FTM_CnSC_DMA_SHIFT 0
1816 #define FTM_CnSC_ELSA_MASK 0x4u
1817 #define FTM_CnSC_ELSA_SHIFT 2
1818 #define FTM_CnSC_ELSB_MASK 0x8u
1819 #define FTM_CnSC_ELSB_SHIFT 3
1820 #define FTM_CnSC_MSA_MASK 0x10u
1821 #define FTM_CnSC_MSA_SHIFT 4
1822 #define FTM_CnSC_MSB_MASK 0x20u
1823 #define FTM_CnSC_MSB_SHIFT 5
1824 #define FTM_CnSC_CHIE_MASK 0x40u
1825 #define FTM_CnSC_CHIE_SHIFT 6
1826 #define FTM_CnSC_CHF_MASK 0x80u
1827 #define FTM_CnSC_CHF_SHIFT 7
1828 /* CnV Bit Fields */
1829 #define FTM_CnV_VAL_MASK 0xFFFFu
1830 #define FTM_CnV_VAL_SHIFT 0
1831 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
1832 /* CNTIN Bit Fields */
1833 #define FTM_CNTIN_INIT_MASK 0xFFFFu
1834 #define FTM_CNTIN_INIT_SHIFT 0
1835 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
1836 /* STATUS Bit Fields */
1837 #define FTM_STATUS_CH0F_MASK 0x1u
1838 #define FTM_STATUS_CH0F_SHIFT 0
1839 #define FTM_STATUS_CH1F_MASK 0x2u
1840 #define FTM_STATUS_CH1F_SHIFT 1
1841 #define FTM_STATUS_CH2F_MASK 0x4u
1842 #define FTM_STATUS_CH2F_SHIFT 2
1843 #define FTM_STATUS_CH3F_MASK 0x8u
1844 #define FTM_STATUS_CH3F_SHIFT 3
1845 #define FTM_STATUS_CH4F_MASK 0x10u
1846 #define FTM_STATUS_CH4F_SHIFT 4
1847 #define FTM_STATUS_CH5F_MASK 0x20u
1848 #define FTM_STATUS_CH5F_SHIFT 5
1849 #define FTM_STATUS_CH6F_MASK 0x40u
1850 #define FTM_STATUS_CH6F_SHIFT 6
1851 #define FTM_STATUS_CH7F_MASK 0x80u
1852 #define FTM_STATUS_CH7F_SHIFT 7
1853 /* MODE Bit Fields */
1854 #define FTM_MODE_FTMEN_MASK 0x1u
1855 #define FTM_MODE_FTMEN_SHIFT 0
1856 #define FTM_MODE_INIT_MASK 0x2u
1857 #define FTM_MODE_INIT_SHIFT 1
1858 #define FTM_MODE_WPDIS_MASK 0x4u
1859 #define FTM_MODE_WPDIS_SHIFT 2
1860 #define FTM_MODE_PWMSYNC_MASK 0x8u
1861 #define FTM_MODE_PWMSYNC_SHIFT 3
1862 #define FTM_MODE_CAPTEST_MASK 0x10u
1863 #define FTM_MODE_CAPTEST_SHIFT 4
1864 #define FTM_MODE_FAULTM_MASK 0x60u
1865 #define FTM_MODE_FAULTM_SHIFT 5
1866 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
1867 #define FTM_MODE_FAULTIE_MASK 0x80u
1868 #define FTM_MODE_FAULTIE_SHIFT 7
1869 /* SYNC Bit Fields */
1870 #define FTM_SYNC_CNTMIN_MASK 0x1u
1871 #define FTM_SYNC_CNTMIN_SHIFT 0
1872 #define FTM_SYNC_CNTMAX_MASK 0x2u
1873 #define FTM_SYNC_CNTMAX_SHIFT 1
1874 #define FTM_SYNC_REINIT_MASK 0x4u
1875 #define FTM_SYNC_REINIT_SHIFT 2
1876 #define FTM_SYNC_SYNCHOM_MASK 0x8u
1877 #define FTM_SYNC_SYNCHOM_SHIFT 3
1878 #define FTM_SYNC_TRIG0_MASK 0x10u
1879 #define FTM_SYNC_TRIG0_SHIFT 4
1880 #define FTM_SYNC_TRIG1_MASK 0x20u
1881 #define FTM_SYNC_TRIG1_SHIFT 5
1882 #define FTM_SYNC_TRIG2_MASK 0x40u
1883 #define FTM_SYNC_TRIG2_SHIFT 6
1884 #define FTM_SYNC_SWSYNC_MASK 0x80u
1885 #define FTM_SYNC_SWSYNC_SHIFT 7
1886 /* OUTINIT Bit Fields */
1887 #define FTM_OUTINIT_CH0OI_MASK 0x1u
1888 #define FTM_OUTINIT_CH0OI_SHIFT 0
1889 #define FTM_OUTINIT_CH1OI_MASK 0x2u
1890 #define FTM_OUTINIT_CH1OI_SHIFT 1
1891 #define FTM_OUTINIT_CH2OI_MASK 0x4u
1892 #define FTM_OUTINIT_CH2OI_SHIFT 2
1893 #define FTM_OUTINIT_CH3OI_MASK 0x8u
1894 #define FTM_OUTINIT_CH3OI_SHIFT 3
1895 #define FTM_OUTINIT_CH4OI_MASK 0x10u
1896 #define FTM_OUTINIT_CH4OI_SHIFT 4
1897 #define FTM_OUTINIT_CH5OI_MASK 0x20u
1898 #define FTM_OUTINIT_CH5OI_SHIFT 5
1899 #define FTM_OUTINIT_CH6OI_MASK 0x40u
1900 #define FTM_OUTINIT_CH6OI_SHIFT 6
1901 #define FTM_OUTINIT_CH7OI_MASK 0x80u
1902 #define FTM_OUTINIT_CH7OI_SHIFT 7
1903 /* OUTMASK Bit Fields */
1904 #define FTM_OUTMASK_CH0OM_MASK 0x1u
1905 #define FTM_OUTMASK_CH0OM_SHIFT 0
1906 #define FTM_OUTMASK_CH1OM_MASK 0x2u
1907 #define FTM_OUTMASK_CH1OM_SHIFT 1
1908 #define FTM_OUTMASK_CH2OM_MASK 0x4u
1909 #define FTM_OUTMASK_CH2OM_SHIFT 2
1910 #define FTM_OUTMASK_CH3OM_MASK 0x8u
1911 #define FTM_OUTMASK_CH3OM_SHIFT 3
1912 #define FTM_OUTMASK_CH4OM_MASK 0x10u
1913 #define FTM_OUTMASK_CH4OM_SHIFT 4
1914 #define FTM_OUTMASK_CH5OM_MASK 0x20u
1915 #define FTM_OUTMASK_CH5OM_SHIFT 5
1916 #define FTM_OUTMASK_CH6OM_MASK 0x40u
1917 #define FTM_OUTMASK_CH6OM_SHIFT 6
1918 #define FTM_OUTMASK_CH7OM_MASK 0x80u
1919 #define FTM_OUTMASK_CH7OM_SHIFT 7
1920 /* COMBINE Bit Fields */
1921 #define FTM_COMBINE_COMBINE0_MASK 0x1u
1922 #define FTM_COMBINE_COMBINE0_SHIFT 0
1923 #define FTM_COMBINE_COMP0_MASK 0x2u
1924 #define FTM_COMBINE_COMP0_SHIFT 1
1925 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
1926 #define FTM_COMBINE_DECAPEN0_SHIFT 2
1927 #define FTM_COMBINE_DECAP0_MASK 0x8u
1928 #define FTM_COMBINE_DECAP0_SHIFT 3
1929 #define FTM_COMBINE_DTEN0_MASK 0x10u
1930 #define FTM_COMBINE_DTEN0_SHIFT 4
1931 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
1932 #define FTM_COMBINE_SYNCEN0_SHIFT 5
1933 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
1934 #define FTM_COMBINE_FAULTEN0_SHIFT 6
1935 #define FTM_COMBINE_COMBINE1_MASK 0x100u
1936 #define FTM_COMBINE_COMBINE1_SHIFT 8
1937 #define FTM_COMBINE_COMP1_MASK 0x200u
1938 #define FTM_COMBINE_COMP1_SHIFT 9
1939 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
1940 #define FTM_COMBINE_DECAPEN1_SHIFT 10
1941 #define FTM_COMBINE_DECAP1_MASK 0x800u
1942 #define FTM_COMBINE_DECAP1_SHIFT 11
1943 #define FTM_COMBINE_DTEN1_MASK 0x1000u
1944 #define FTM_COMBINE_DTEN1_SHIFT 12
1945 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
1946 #define FTM_COMBINE_SYNCEN1_SHIFT 13
1947 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
1948 #define FTM_COMBINE_FAULTEN1_SHIFT 14
1949 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
1950 #define FTM_COMBINE_COMBINE2_SHIFT 16
1951 #define FTM_COMBINE_COMP2_MASK 0x20000u
1952 #define FTM_COMBINE_COMP2_SHIFT 17
1953 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
1954 #define FTM_COMBINE_DECAPEN2_SHIFT 18
1955 #define FTM_COMBINE_DECAP2_MASK 0x80000u
1956 #define FTM_COMBINE_DECAP2_SHIFT 19
1957 #define FTM_COMBINE_DTEN2_MASK 0x100000u
1958 #define FTM_COMBINE_DTEN2_SHIFT 20
1959 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
1960 #define FTM_COMBINE_SYNCEN2_SHIFT 21
1961 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
1962 #define FTM_COMBINE_FAULTEN2_SHIFT 22
1963 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
1964 #define FTM_COMBINE_COMBINE3_SHIFT 24
1965 #define FTM_COMBINE_COMP3_MASK 0x2000000u
1966 #define FTM_COMBINE_COMP3_SHIFT 25
1967 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
1968 #define FTM_COMBINE_DECAPEN3_SHIFT 26
1969 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
1970 #define FTM_COMBINE_DECAP3_SHIFT 27
1971 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
1972 #define FTM_COMBINE_DTEN3_SHIFT 28
1973 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
1974 #define FTM_COMBINE_SYNCEN3_SHIFT 29
1975 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
1976 #define FTM_COMBINE_FAULTEN3_SHIFT 30
1977 /* DEADTIME Bit Fields */
1978 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
1979 #define FTM_DEADTIME_DTVAL_SHIFT 0
1980 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
1981 #define FTM_DEADTIME_DTPS_MASK 0xC0u
1982 #define FTM_DEADTIME_DTPS_SHIFT 6
1983 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
1984 /* EXTTRIG Bit Fields */
1985 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
1986 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
1987 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
1988 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
1989 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
1990 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
1991 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
1992 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
1993 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
1994 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
1995 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
1996 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
1997 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
1998 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
1999 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
2000 #define FTM_EXTTRIG_TRIGF_SHIFT 7
2001 /* POL Bit Fields */
2002 #define FTM_POL_POL0_MASK 0x1u
2003 #define FTM_POL_POL0_SHIFT 0
2004 #define FTM_POL_POL1_MASK 0x2u
2005 #define FTM_POL_POL1_SHIFT 1
2006 #define FTM_POL_POL2_MASK 0x4u
2007 #define FTM_POL_POL2_SHIFT 2
2008 #define FTM_POL_POL3_MASK 0x8u
2009 #define FTM_POL_POL3_SHIFT 3
2010 #define FTM_POL_POL4_MASK 0x10u
2011 #define FTM_POL_POL4_SHIFT 4
2012 #define FTM_POL_POL5_MASK 0x20u
2013 #define FTM_POL_POL5_SHIFT 5
2014 #define FTM_POL_POL6_MASK 0x40u
2015 #define FTM_POL_POL6_SHIFT 6
2016 #define FTM_POL_POL7_MASK 0x80u
2017 #define FTM_POL_POL7_SHIFT 7
2018 /* FMS Bit Fields */
2019 #define FTM_FMS_FAULTF0_MASK 0x1u
2020 #define FTM_FMS_FAULTF0_SHIFT 0
2021 #define FTM_FMS_FAULTF1_MASK 0x2u
2022 #define FTM_FMS_FAULTF1_SHIFT 1
2023 #define FTM_FMS_FAULTF2_MASK 0x4u
2024 #define FTM_FMS_FAULTF2_SHIFT 2
2025 #define FTM_FMS_FAULTF3_MASK 0x8u
2026 #define FTM_FMS_FAULTF3_SHIFT 3
2027 #define FTM_FMS_FAULTIN_MASK 0x20u
2028 #define FTM_FMS_FAULTIN_SHIFT 5
2029 #define FTM_FMS_WPEN_MASK 0x40u
2030 #define FTM_FMS_WPEN_SHIFT 6
2031 #define FTM_FMS_FAULTF_MASK 0x80u
2032 #define FTM_FMS_FAULTF_SHIFT 7
2033 /* FILTER Bit Fields */
2034 #define FTM_FILTER_CH0FVAL_MASK 0xFu
2035 #define FTM_FILTER_CH0FVAL_SHIFT 0
2036 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
2037 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
2038 #define FTM_FILTER_CH1FVAL_SHIFT 4
2039 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
2040 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
2041 #define FTM_FILTER_CH2FVAL_SHIFT 8
2042 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
2043 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
2044 #define FTM_FILTER_CH3FVAL_SHIFT 12
2045 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
2046 /* FLTCTRL Bit Fields */
2047 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
2048 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
2049 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
2050 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
2051 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
2052 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
2053 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
2054 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
2055 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
2056 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
2057 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
2058 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
2059 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
2060 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
2061 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
2062 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
2063 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
2064 #define FTM_FLTCTRL_FFVAL_SHIFT 8
2065 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
2066 /* QDCTRL Bit Fields */
2067 #define FTM_QDCTRL_QUADEN_MASK 0x1u
2068 #define FTM_QDCTRL_QUADEN_SHIFT 0
2069 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
2070 #define FTM_QDCTRL_TOFDIR_SHIFT 1
2071 #define FTM_QDCTRL_QUADIR_MASK 0x4u
2072 #define FTM_QDCTRL_QUADIR_SHIFT 2
2073 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
2074 #define FTM_QDCTRL_QUADMODE_SHIFT 3
2075 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
2076 #define FTM_QDCTRL_PHBPOL_SHIFT 4
2077 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
2078 #define FTM_QDCTRL_PHAPOL_SHIFT 5
2079 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
2080 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
2081 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
2082 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
2083 /* CONF Bit Fields */
2084 #define FTM_CONF_NUMTOF_MASK 0x1Fu
2085 #define FTM_CONF_NUMTOF_SHIFT 0
2086 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
2087 #define FTM_CONF_BDMMODE_MASK 0xC0u
2088 #define FTM_CONF_BDMMODE_SHIFT 6
2089 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
2090 #define FTM_CONF_GTBEEN_MASK 0x200u
2091 #define FTM_CONF_GTBEEN_SHIFT 9
2092 #define FTM_CONF_GTBEOUT_MASK 0x400u
2093 #define FTM_CONF_GTBEOUT_SHIFT 10
2094 /* FLTPOL Bit Fields */
2095 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
2096 #define FTM_FLTPOL_FLT0POL_SHIFT 0
2097 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
2098 #define FTM_FLTPOL_FLT1POL_SHIFT 1
2099 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
2100 #define FTM_FLTPOL_FLT2POL_SHIFT 2
2101 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
2102 #define FTM_FLTPOL_FLT3POL_SHIFT 3
2103 /* SYNCONF Bit Fields */
2104 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
2105 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
2106 #define FTM_SYNCONF_CNTINC_MASK 0x4u
2107 #define FTM_SYNCONF_CNTINC_SHIFT 2
2108 #define FTM_SYNCONF_INVC_MASK 0x10u
2109 #define FTM_SYNCONF_INVC_SHIFT 4
2110 #define FTM_SYNCONF_SWOC_MASK 0x20u
2111 #define FTM_SYNCONF_SWOC_SHIFT 5
2112 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
2113 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
2114 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
2115 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
2116 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
2117 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
2118 #define FTM_SYNCONF_SWOM_MASK 0x400u
2119 #define FTM_SYNCONF_SWOM_SHIFT 10
2120 #define FTM_SYNCONF_SWINVC_MASK 0x800u
2121 #define FTM_SYNCONF_SWINVC_SHIFT 11
2122 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
2123 #define FTM_SYNCONF_SWSOC_SHIFT 12
2124 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
2125 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
2126 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
2127 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
2128 #define FTM_SYNCONF_HWOM_MASK 0x40000u
2129 #define FTM_SYNCONF_HWOM_SHIFT 18
2130 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
2131 #define FTM_SYNCONF_HWINVC_SHIFT 19
2132 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
2133 #define FTM_SYNCONF_HWSOC_SHIFT 20
2134 /* INVCTRL Bit Fields */
2135 #define FTM_INVCTRL_INV0EN_MASK 0x1u
2136 #define FTM_INVCTRL_INV0EN_SHIFT 0
2137 #define FTM_INVCTRL_INV1EN_MASK 0x2u
2138 #define FTM_INVCTRL_INV1EN_SHIFT 1
2139 #define FTM_INVCTRL_INV2EN_MASK 0x4u
2140 #define FTM_INVCTRL_INV2EN_SHIFT 2
2141 #define FTM_INVCTRL_INV3EN_MASK 0x8u
2142 #define FTM_INVCTRL_INV3EN_SHIFT 3
2143 /* SWOCTRL Bit Fields */
2144 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
2145 #define FTM_SWOCTRL_CH0OC_SHIFT 0
2146 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
2147 #define FTM_SWOCTRL_CH1OC_SHIFT 1
2148 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
2149 #define FTM_SWOCTRL_CH2OC_SHIFT 2
2150 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
2151 #define FTM_SWOCTRL_CH3OC_SHIFT 3
2152 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
2153 #define FTM_SWOCTRL_CH4OC_SHIFT 4
2154 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
2155 #define FTM_SWOCTRL_CH5OC_SHIFT 5
2156 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
2157 #define FTM_SWOCTRL_CH6OC_SHIFT 6
2158 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
2159 #define FTM_SWOCTRL_CH7OC_SHIFT 7
2160 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
2161 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
2162 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
2163 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
2164 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
2165 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
2166 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
2167 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
2168 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
2169 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
2170 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
2171 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
2172 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
2173 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
2174 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
2175 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
2176 /* PWMLOAD Bit Fields */
2177 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
2178 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
2179 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
2180 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
2181 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
2182 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
2183 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
2184 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
2185 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
2186 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
2187 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
2188 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
2189 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
2190 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
2191 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
2192 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
2193 #define FTM_PWMLOAD_LDOK_MASK 0x200u
2194 #define FTM_PWMLOAD_LDOK_SHIFT 9
2195
2196 /**
2197 * @}
2198 */ /* end of group FTM_Register_Masks */
2199
2200
2201 /* FTM - Peripheral instance base addresses */
2202 /** Peripheral FTM0 base address */
2203 #define FTM0_BASE (0x40038000u)
2204 /** Peripheral FTM0 base pointer */
2205 #define FTM0 ((FTM_Type *)FTM0_BASE)
2206 /** Peripheral FTM1 base address */
2207 #define FTM1_BASE (0x40039000u)
2208 /** Peripheral FTM1 base pointer */
2209 #define FTM1 ((FTM_Type *)FTM1_BASE)
2210
2211 /**
2212 * @}
2213 */ /* end of group FTM_Peripheral_Access_Layer */
2214
2215
2216 /* ----------------------------------------------------------------------------
2217 -- GPIO Peripheral Access Layer
2218 ---------------------------------------------------------------------------- */
2219
2220 /**
2221 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
2222 * @{
2223 */
2224
2225 /** GPIO - Register Layout Typedef */
2226 typedef struct {
2227 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
2228 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
2229 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
2230 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
2231 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
2232 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
2233 } GPIO_Type;
2234
2235 /* ----------------------------------------------------------------------------
2236 -- GPIO Register Masks
2237 ---------------------------------------------------------------------------- */
2238
2239 /**
2240 * @addtogroup GPIO_Register_Masks GPIO Register Masks
2241 * @{
2242 */
2243
2244 /* PDOR Bit Fields */
2245 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
2246 #define GPIO_PDOR_PDO_SHIFT 0
2247 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
2248 /* PSOR Bit Fields */
2249 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
2250 #define GPIO_PSOR_PTSO_SHIFT 0
2251 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
2252 /* PCOR Bit Fields */
2253 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
2254 #define GPIO_PCOR_PTCO_SHIFT 0
2255 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
2256 /* PTOR Bit Fields */
2257 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
2258 #define GPIO_PTOR_PTTO_SHIFT 0
2259 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
2260 /* PDIR Bit Fields */
2261 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
2262 #define GPIO_PDIR_PDI_SHIFT 0
2263 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
2264 /* PDDR Bit Fields */
2265 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
2266 #define GPIO_PDDR_PDD_SHIFT 0
2267 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
2268
2269 /**
2270 * @}
2271 */ /* end of group GPIO_Register_Masks */
2272
2273
2274 /* GPIO - Peripheral instance base addresses */
2275 /** Peripheral PTA base address */
2276 #define PTA_BASE (0x400FF000u)
2277 /** Peripheral PTA base pointer */
2278 #define PTA ((GPIO_Type *)PTA_BASE)
2279 /** Peripheral PTB base address */
2280 #define PTB_BASE (0x400FF040u)
2281 /** Peripheral PTB base pointer */
2282 #define PTB ((GPIO_Type *)PTB_BASE)
2283 /** Peripheral PTC base address */
2284 #define PTC_BASE (0x400FF080u)
2285 /** Peripheral PTC base pointer */
2286 #define PTC ((GPIO_Type *)PTC_BASE)
2287 /** Peripheral PTD base address */
2288 #define PTD_BASE (0x400FF0C0u)
2289 /** Peripheral PTD base pointer */
2290 #define PTD ((GPIO_Type *)PTD_BASE)
2291 /** Peripheral PTE base address */
2292 #define PTE_BASE (0x400FF100u)
2293 /** Peripheral PTE base pointer */
2294 #define PTE ((GPIO_Type *)PTE_BASE)
2295
2296 /**
2297 * @}
2298 */ /* end of group GPIO_Peripheral_Access_Layer */
2299
2300
2301 /* ----------------------------------------------------------------------------
2302 -- I2C Peripheral Access Layer
2303 ---------------------------------------------------------------------------- */
2304
2305 /**
2306 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
2307 * @{
2308 */
2309
2310 /** I2C - Register Layout Typedef */
2311 typedef struct {
2312 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
2313 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
2314 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
2315 __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
2316 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
2317 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
2318 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
2319 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
2320 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
2321 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
2322 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
2323 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
2324 } I2C_Type;
2325
2326 /* ----------------------------------------------------------------------------
2327 -- I2C Register Masks
2328 ---------------------------------------------------------------------------- */
2329
2330 /**
2331 * @addtogroup I2C_Register_Masks I2C Register Masks
2332 * @{
2333 */
2334
2335 /* A1 Bit Fields */
2336 #define I2C_A1_AD_MASK 0xFEu
2337 #define I2C_A1_AD_SHIFT 1
2338 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
2339 /* F Bit Fields */
2340 #define I2C_F_ICR_MASK 0x3Fu
2341 #define I2C_F_ICR_SHIFT 0
2342 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
2343 #define I2C_F_MULT_MASK 0xC0u
2344 #define I2C_F_MULT_SHIFT 6
2345 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
2346 /* C1 Bit Fields */
2347 #define I2C_C1_DMAEN_MASK 0x1u
2348 #define I2C_C1_DMAEN_SHIFT 0
2349 #define I2C_C1_WUEN_MASK 0x2u
2350 #define I2C_C1_WUEN_SHIFT 1
2351 #define I2C_C1_RSTA_MASK 0x4u
2352 #define I2C_C1_RSTA_SHIFT 2
2353 #define I2C_C1_TXAK_MASK 0x8u
2354 #define I2C_C1_TXAK_SHIFT 3
2355 #define I2C_C1_TX_MASK 0x10u
2356 #define I2C_C1_TX_SHIFT 4
2357 #define I2C_C1_MST_MASK 0x20u
2358 #define I2C_C1_MST_SHIFT 5
2359 #define I2C_C1_IICIE_MASK 0x40u
2360 #define I2C_C1_IICIE_SHIFT 6
2361 #define I2C_C1_IICEN_MASK 0x80u
2362 #define I2C_C1_IICEN_SHIFT 7
2363 /* S Bit Fields */
2364 #define I2C_S_RXAK_MASK 0x1u
2365 #define I2C_S_RXAK_SHIFT 0
2366 #define I2C_S_IICIF_MASK 0x2u
2367 #define I2C_S_IICIF_SHIFT 1
2368 #define I2C_S_SRW_MASK 0x4u
2369 #define I2C_S_SRW_SHIFT 2
2370 #define I2C_S_RAM_MASK 0x8u
2371 #define I2C_S_RAM_SHIFT 3
2372 #define I2C_S_ARBL_MASK 0x10u
2373 #define I2C_S_ARBL_SHIFT 4
2374 #define I2C_S_BUSY_MASK 0x20u
2375 #define I2C_S_BUSY_SHIFT 5
2376 #define I2C_S_IAAS_MASK 0x40u
2377 #define I2C_S_IAAS_SHIFT 6
2378 #define I2C_S_TCF_MASK 0x80u
2379 #define I2C_S_TCF_SHIFT 7
2380 /* D Bit Fields */
2381 #define I2C_D_DATA_MASK 0xFFu
2382 #define I2C_D_DATA_SHIFT 0
2383 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
2384 /* C2 Bit Fields */
2385 #define I2C_C2_AD_MASK 0x7u
2386 #define I2C_C2_AD_SHIFT 0
2387 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
2388 #define I2C_C2_RMEN_MASK 0x8u
2389 #define I2C_C2_RMEN_SHIFT 3
2390 #define I2C_C2_SBRC_MASK 0x10u
2391 #define I2C_C2_SBRC_SHIFT 4
2392 #define I2C_C2_HDRS_MASK 0x20u
2393 #define I2C_C2_HDRS_SHIFT 5
2394 #define I2C_C2_ADEXT_MASK 0x40u
2395 #define I2C_C2_ADEXT_SHIFT 6
2396 #define I2C_C2_GCAEN_MASK 0x80u
2397 #define I2C_C2_GCAEN_SHIFT 7
2398 /* FLT Bit Fields */
2399 #define I2C_FLT_FLT_MASK 0x1Fu
2400 #define I2C_FLT_FLT_SHIFT 0
2401 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
2402 /* RA Bit Fields */
2403 #define I2C_RA_RAD_MASK 0xFEu
2404 #define I2C_RA_RAD_SHIFT 1
2405 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
2406 /* SMB Bit Fields */
2407 #define I2C_SMB_SHTF2IE_MASK 0x1u
2408 #define I2C_SMB_SHTF2IE_SHIFT 0
2409 #define I2C_SMB_SHTF2_MASK 0x2u
2410 #define I2C_SMB_SHTF2_SHIFT 1
2411 #define I2C_SMB_SHTF1_MASK 0x4u
2412 #define I2C_SMB_SHTF1_SHIFT 2
2413 #define I2C_SMB_SLTF_MASK 0x8u
2414 #define I2C_SMB_SLTF_SHIFT 3
2415 #define I2C_SMB_TCKSEL_MASK 0x10u
2416 #define I2C_SMB_TCKSEL_SHIFT 4
2417 #define I2C_SMB_SIICAEN_MASK 0x20u
2418 #define I2C_SMB_SIICAEN_SHIFT 5
2419 #define I2C_SMB_ALERTEN_MASK 0x40u
2420 #define I2C_SMB_ALERTEN_SHIFT 6
2421 #define I2C_SMB_FACK_MASK 0x80u
2422 #define I2C_SMB_FACK_SHIFT 7
2423 /* A2 Bit Fields */
2424 #define I2C_A2_SAD_MASK 0xFEu
2425 #define I2C_A2_SAD_SHIFT 1
2426 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
2427 /* SLTH Bit Fields */
2428 #define I2C_SLTH_SSLT_MASK 0xFFu
2429 #define I2C_SLTH_SSLT_SHIFT 0
2430 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
2431 /* SLTL Bit Fields */
2432 #define I2C_SLTL_SSLT_MASK 0xFFu
2433 #define I2C_SLTL_SSLT_SHIFT 0
2434 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
2435
2436 /**
2437 * @}
2438 */ /* end of group I2C_Register_Masks */
2439
2440
2441 /* I2C - Peripheral instance base addresses */
2442 /** Peripheral I2C0 base address */
2443 #define I2C0_BASE (0x40066000u)
2444 #define I2C1_BASE (0x40067000u)
2445 /** Peripheral I2C0 base pointer */
2446 #define I2C0 ((I2C_Type *)I2C0_BASE)
2447 #define I2C1 ((I2C_Type *)I2C1_BASE)
2448 /**
2449 * @}
2450 */ /* end of group I2C_Peripheral_Access_Layer */
2451
2452
2453 /* ----------------------------------------------------------------------------
2454 -- I2S Peripheral Access Layer
2455 ---------------------------------------------------------------------------- */
2456
2457 /**
2458 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
2459 * @{
2460 */
2461
2462 /** I2S - Register Layout Typedef */
2463 typedef struct {
2464 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
2465 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
2466 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
2467 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
2468 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
2469 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
2470 uint8_t RESERVED_0[8];
2471 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
2472 uint8_t RESERVED_1[24];
2473 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
2474 uint8_t RESERVED_2[24];
2475 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
2476 uint8_t RESERVED_3[28];
2477 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
2478 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
2479 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
2480 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
2481 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
2482 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
2483 uint8_t RESERVED_4[8];
2484 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
2485 uint8_t RESERVED_5[24];
2486 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
2487 uint8_t RESERVED_6[24];
2488 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
2489 uint8_t RESERVED_7[28];
2490 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
2491 __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
2492 } I2S_Type;
2493
2494 /* ----------------------------------------------------------------------------
2495 -- I2S Register Masks
2496 ---------------------------------------------------------------------------- */
2497
2498 /**
2499 * @addtogroup I2S_Register_Masks I2S Register Masks
2500 * @{
2501 */
2502
2503 /* TCSR Bit Fields */
2504 #define I2S_TCSR_FRDE_MASK 0x1u
2505 #define I2S_TCSR_FRDE_SHIFT 0
2506 #define I2S_TCSR_FWDE_MASK 0x2u
2507 #define I2S_TCSR_FWDE_SHIFT 1
2508 #define I2S_TCSR_FRIE_MASK 0x100u
2509 #define I2S_TCSR_FRIE_SHIFT 8
2510 #define I2S_TCSR_FWIE_MASK 0x200u
2511 #define I2S_TCSR_FWIE_SHIFT 9
2512 #define I2S_TCSR_FEIE_MASK 0x400u
2513 #define I2S_TCSR_FEIE_SHIFT 10
2514 #define I2S_TCSR_SEIE_MASK 0x800u
2515 #define I2S_TCSR_SEIE_SHIFT 11
2516 #define I2S_TCSR_WSIE_MASK 0x1000u
2517 #define I2S_TCSR_WSIE_SHIFT 12
2518 #define I2S_TCSR_FRF_MASK 0x10000u
2519 #define I2S_TCSR_FRF_SHIFT 16
2520 #define I2S_TCSR_FWF_MASK 0x20000u
2521 #define I2S_TCSR_FWF_SHIFT 17
2522 #define I2S_TCSR_FEF_MASK 0x40000u
2523 #define I2S_TCSR_FEF_SHIFT 18
2524 #define I2S_TCSR_SEF_MASK 0x80000u
2525 #define I2S_TCSR_SEF_SHIFT 19
2526 #define I2S_TCSR_WSF_MASK 0x100000u
2527 #define I2S_TCSR_WSF_SHIFT 20
2528 #define I2S_TCSR_SR_MASK 0x1000000u
2529 #define I2S_TCSR_SR_SHIFT 24
2530 #define I2S_TCSR_FR_MASK 0x2000000u
2531 #define I2S_TCSR_FR_SHIFT 25
2532 #define I2S_TCSR_BCE_MASK 0x10000000u
2533 #define I2S_TCSR_BCE_SHIFT 28
2534 #define I2S_TCSR_DBGE_MASK 0x20000000u
2535 #define I2S_TCSR_DBGE_SHIFT 29
2536 #define I2S_TCSR_STOPE_MASK 0x40000000u
2537 #define I2S_TCSR_STOPE_SHIFT 30
2538 #define I2S_TCSR_TE_MASK 0x80000000u
2539 #define I2S_TCSR_TE_SHIFT 31
2540 /* TCR1 Bit Fields */
2541 #define I2S_TCR1_TFW_MASK 0x7u
2542 #define I2S_TCR1_TFW_SHIFT 0
2543 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
2544 /* TCR2 Bit Fields */
2545 #define I2S_TCR2_DIV_MASK 0xFFu
2546 #define I2S_TCR2_DIV_SHIFT 0
2547 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
2548 #define I2S_TCR2_BCD_MASK 0x1000000u
2549 #define I2S_TCR2_BCD_SHIFT 24
2550 #define I2S_TCR2_BCP_MASK 0x2000000u
2551 #define I2S_TCR2_BCP_SHIFT 25
2552 #define I2S_TCR2_MSEL_MASK 0xC000000u
2553 #define I2S_TCR2_MSEL_SHIFT 26
2554 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
2555 #define I2S_TCR2_BCI_MASK 0x10000000u
2556 #define I2S_TCR2_BCI_SHIFT 28
2557 #define I2S_TCR2_BCS_MASK 0x20000000u
2558 #define I2S_TCR2_BCS_SHIFT 29
2559 #define I2S_TCR2_SYNC_MASK 0xC0000000u
2560 #define I2S_TCR2_SYNC_SHIFT 30
2561 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
2562 /* TCR3 Bit Fields */
2563 #define I2S_TCR3_WDFL_MASK 0x1Fu
2564 #define I2S_TCR3_WDFL_SHIFT 0
2565 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
2566 #define I2S_TCR3_TCE_MASK 0x30000u
2567 #define I2S_TCR3_TCE_SHIFT 16
2568 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
2569 /* TCR4 Bit Fields */
2570 #define I2S_TCR4_FSD_MASK 0x1u
2571 #define I2S_TCR4_FSD_SHIFT 0
2572 #define I2S_TCR4_FSP_MASK 0x2u
2573 #define I2S_TCR4_FSP_SHIFT 1
2574 #define I2S_TCR4_FSE_MASK 0x8u
2575 #define I2S_TCR4_FSE_SHIFT 3
2576 #define I2S_TCR4_MF_MASK 0x10u
2577 #define I2S_TCR4_MF_SHIFT 4
2578 #define I2S_TCR4_SYWD_MASK 0x1F00u
2579 #define I2S_TCR4_SYWD_SHIFT 8
2580 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
2581 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
2582 #define I2S_TCR4_FRSZ_SHIFT 16
2583 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
2584 /* TCR5 Bit Fields */
2585 #define I2S_TCR5_FBT_MASK 0x1F00u
2586 #define I2S_TCR5_FBT_SHIFT 8
2587 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
2588 #define I2S_TCR5_W0W_MASK 0x1F0000u
2589 #define I2S_TCR5_W0W_SHIFT 16
2590 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
2591 #define I2S_TCR5_WNW_MASK 0x1F000000u
2592 #define I2S_TCR5_WNW_SHIFT 24
2593 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
2594 /* TDR Bit Fields */
2595 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
2596 #define I2S_TDR_TDR_SHIFT 0
2597 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
2598 /* TFR Bit Fields */
2599 #define I2S_TFR_RFP_MASK 0xFu
2600 #define I2S_TFR_RFP_SHIFT 0
2601 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
2602 #define I2S_TFR_WFP_MASK 0xF0000u
2603 #define I2S_TFR_WFP_SHIFT 16
2604 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
2605 /* TMR Bit Fields */
2606 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
2607 #define I2S_TMR_TWM_SHIFT 0
2608 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
2609 /* RCSR Bit Fields */
2610 #define I2S_RCSR_FRDE_MASK 0x1u
2611 #define I2S_RCSR_FRDE_SHIFT 0
2612 #define I2S_RCSR_FWDE_MASK 0x2u
2613 #define I2S_RCSR_FWDE_SHIFT 1
2614 #define I2S_RCSR_FRIE_MASK 0x100u
2615 #define I2S_RCSR_FRIE_SHIFT 8
2616 #define I2S_RCSR_FWIE_MASK 0x200u
2617 #define I2S_RCSR_FWIE_SHIFT 9
2618 #define I2S_RCSR_FEIE_MASK 0x400u
2619 #define I2S_RCSR_FEIE_SHIFT 10
2620 #define I2S_RCSR_SEIE_MASK 0x800u
2621 #define I2S_RCSR_SEIE_SHIFT 11
2622 #define I2S_RCSR_WSIE_MASK 0x1000u
2623 #define I2S_RCSR_WSIE_SHIFT 12
2624 #define I2S_RCSR_FRF_MASK 0x10000u
2625 #define I2S_RCSR_FRF_SHIFT 16
2626 #define I2S_RCSR_FWF_MASK 0x20000u
2627 #define I2S_RCSR_FWF_SHIFT 17
2628 #define I2S_RCSR_FEF_MASK 0x40000u
2629 #define I2S_RCSR_FEF_SHIFT 18
2630 #define I2S_RCSR_SEF_MASK 0x80000u
2631 #define I2S_RCSR_SEF_SHIFT 19
2632 #define I2S_RCSR_WSF_MASK 0x100000u
2633 #define I2S_RCSR_WSF_SHIFT 20
2634 #define I2S_RCSR_SR_MASK 0x1000000u
2635 #define I2S_RCSR_SR_SHIFT 24
2636 #define I2S_RCSR_FR_MASK 0x2000000u
2637 #define I2S_RCSR_FR_SHIFT 25
2638 #define I2S_RCSR_BCE_MASK 0x10000000u
2639 #define I2S_RCSR_BCE_SHIFT 28
2640 #define I2S_RCSR_DBGE_MASK 0x20000000u
2641 #define I2S_RCSR_DBGE_SHIFT 29
2642 #define I2S_RCSR_STOPE_MASK 0x40000000u
2643 #define I2S_RCSR_STOPE_SHIFT 30
2644 #define I2S_RCSR_RE_MASK 0x80000000u
2645 #define I2S_RCSR_RE_SHIFT 31
2646 /* RCR1 Bit Fields */
2647 #define I2S_RCR1_RFW_MASK 0x7u
2648 #define I2S_RCR1_RFW_SHIFT 0
2649 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
2650 /* RCR2 Bit Fields */
2651 #define I2S_RCR2_DIV_MASK 0xFFu
2652 #define I2S_RCR2_DIV_SHIFT 0
2653 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
2654 #define I2S_RCR2_BCD_MASK 0x1000000u
2655 #define I2S_RCR2_BCD_SHIFT 24
2656 #define I2S_RCR2_BCP_MASK 0x2000000u
2657 #define I2S_RCR2_BCP_SHIFT 25
2658 #define I2S_RCR2_MSEL_MASK 0xC000000u
2659 #define I2S_RCR2_MSEL_SHIFT 26
2660 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
2661 #define I2S_RCR2_BCI_MASK 0x10000000u
2662 #define I2S_RCR2_BCI_SHIFT 28
2663 #define I2S_RCR2_BCS_MASK 0x20000000u
2664 #define I2S_RCR2_BCS_SHIFT 29
2665 #define I2S_RCR2_SYNC_MASK 0xC0000000u
2666 #define I2S_RCR2_SYNC_SHIFT 30
2667 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
2668 /* RCR3 Bit Fields */
2669 #define I2S_RCR3_WDFL_MASK 0x1Fu
2670 #define I2S_RCR3_WDFL_SHIFT 0
2671 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
2672 #define I2S_RCR3_RCE_MASK 0x30000u
2673 #define I2S_RCR3_RCE_SHIFT 16
2674 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
2675 /* RCR4 Bit Fields */
2676 #define I2S_RCR4_FSD_MASK 0x1u
2677 #define I2S_RCR4_FSD_SHIFT 0
2678 #define I2S_RCR4_FSP_MASK 0x2u
2679 #define I2S_RCR4_FSP_SHIFT 1
2680 #define I2S_RCR4_FSE_MASK 0x8u
2681 #define I2S_RCR4_FSE_SHIFT 3
2682 #define I2S_RCR4_MF_MASK 0x10u
2683 #define I2S_RCR4_MF_SHIFT 4
2684 #define I2S_RCR4_SYWD_MASK 0x1F00u
2685 #define I2S_RCR4_SYWD_SHIFT 8
2686 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
2687 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
2688 #define I2S_RCR4_FRSZ_SHIFT 16
2689 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
2690 /* RCR5 Bit Fields */
2691 #define I2S_RCR5_FBT_MASK 0x1F00u
2692 #define I2S_RCR5_FBT_SHIFT 8
2693 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
2694 #define I2S_RCR5_W0W_MASK 0x1F0000u
2695 #define I2S_RCR5_W0W_SHIFT 16
2696 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
2697 #define I2S_RCR5_WNW_MASK 0x1F000000u
2698 #define I2S_RCR5_WNW_SHIFT 24
2699 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
2700 /* RDR Bit Fields */
2701 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
2702 #define I2S_RDR_RDR_SHIFT 0
2703 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
2704 /* RFR Bit Fields */
2705 #define I2S_RFR_RFP_MASK 0xFu
2706 #define I2S_RFR_RFP_SHIFT 0
2707 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
2708 #define I2S_RFR_WFP_MASK 0xF0000u
2709 #define I2S_RFR_WFP_SHIFT 16
2710 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
2711 /* RMR Bit Fields */
2712 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
2713 #define I2S_RMR_RWM_SHIFT 0
2714 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
2715 /* MCR Bit Fields */
2716 #define I2S_MCR_MICS_MASK 0x3000000u
2717 #define I2S_MCR_MICS_SHIFT 24
2718 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
2719 #define I2S_MCR_MOE_MASK 0x40000000u
2720 #define I2S_MCR_MOE_SHIFT 30
2721 #define I2S_MCR_DUF_MASK 0x80000000u
2722 #define I2S_MCR_DUF_SHIFT 31
2723 /* MDR Bit Fields */
2724 #define I2S_MDR_DIVIDE_MASK 0xFFFu
2725 #define I2S_MDR_DIVIDE_SHIFT 0
2726 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
2727 #define I2S_MDR_FRACT_MASK 0xFF000u
2728 #define I2S_MDR_FRACT_SHIFT 12
2729 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
2730
2731 /**
2732 * @}
2733 */ /* end of group I2S_Register_Masks */
2734
2735
2736 /* I2S - Peripheral instance base addresses */
2737 /** Peripheral I2S0 base address */
2738 #define I2S0_BASE (0x4002F000u)
2739 /** Peripheral I2S0 base pointer */
2740 #define I2S0 ((I2S_Type *)I2S0_BASE)
2741
2742 /**
2743 * @}
2744 */ /* end of group I2S_Peripheral_Access_Layer */
2745
2746
2747 /* ----------------------------------------------------------------------------
2748 -- LLWU Peripheral Access Layer
2749 ---------------------------------------------------------------------------- */
2750
2751 /**
2752 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
2753 * @{
2754 */
2755
2756 /** LLWU - Register Layout Typedef */
2757 typedef struct {
2758 __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
2759 __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
2760 __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
2761 __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
2762 __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
2763 __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
2764 __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
2765 __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
2766 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
2767 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
2768 __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
2769 } LLWU_Type;
2770
2771 /* ----------------------------------------------------------------------------
2772 -- LLWU Register Masks
2773 ---------------------------------------------------------------------------- */
2774
2775 /**
2776 * @addtogroup LLWU_Register_Masks LLWU Register Masks
2777 * @{
2778 */
2779
2780 /* PE1 Bit Fields */
2781 #define LLWU_PE1_WUPE0_MASK 0x3u
2782 #define LLWU_PE1_WUPE0_SHIFT 0
2783 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
2784 #define LLWU_PE1_WUPE1_MASK 0xCu
2785 #define LLWU_PE1_WUPE1_SHIFT 2
2786 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
2787 #define LLWU_PE1_WUPE2_MASK 0x30u
2788 #define LLWU_PE1_WUPE2_SHIFT 4
2789 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
2790 #define LLWU_PE1_WUPE3_MASK 0xC0u
2791 #define LLWU_PE1_WUPE3_SHIFT 6
2792 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
2793 /* PE2 Bit Fields */
2794 #define LLWU_PE2_WUPE4_MASK 0x3u
2795 #define LLWU_PE2_WUPE4_SHIFT 0
2796 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
2797 #define LLWU_PE2_WUPE5_MASK 0xCu
2798 #define LLWU_PE2_WUPE5_SHIFT 2
2799 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
2800 #define LLWU_PE2_WUPE6_MASK 0x30u
2801 #define LLWU_PE2_WUPE6_SHIFT 4
2802 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
2803 #define LLWU_PE2_WUPE7_MASK 0xC0u
2804 #define LLWU_PE2_WUPE7_SHIFT 6
2805 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
2806 /* PE3 Bit Fields */
2807 #define LLWU_PE3_WUPE8_MASK 0x3u
2808 #define LLWU_PE3_WUPE8_SHIFT 0
2809 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
2810 #define LLWU_PE3_WUPE9_MASK 0xCu
2811 #define LLWU_PE3_WUPE9_SHIFT 2
2812 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
2813 #define LLWU_PE3_WUPE10_MASK 0x30u
2814 #define LLWU_PE3_WUPE10_SHIFT 4
2815 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
2816 #define LLWU_PE3_WUPE11_MASK 0xC0u
2817 #define LLWU_PE3_WUPE11_SHIFT 6
2818 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
2819 /* PE4 Bit Fields */
2820 #define LLWU_PE4_WUPE12_MASK 0x3u
2821 #define LLWU_PE4_WUPE12_SHIFT 0
2822 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
2823 #define LLWU_PE4_WUPE13_MASK 0xCu
2824 #define LLWU_PE4_WUPE13_SHIFT 2
2825 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
2826 #define LLWU_PE4_WUPE14_MASK 0x30u
2827 #define LLWU_PE4_WUPE14_SHIFT 4
2828 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
2829 #define LLWU_PE4_WUPE15_MASK 0xC0u
2830 #define LLWU_PE4_WUPE15_SHIFT 6
2831 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
2832 /* ME Bit Fields */
2833 #define LLWU_ME_WUME0_MASK 0x1u
2834 #define LLWU_ME_WUME0_SHIFT 0
2835 #define LLWU_ME_WUME1_MASK 0x2u
2836 #define LLWU_ME_WUME1_SHIFT 1
2837 #define LLWU_ME_WUME2_MASK 0x4u
2838 #define LLWU_ME_WUME2_SHIFT 2
2839 #define LLWU_ME_WUME3_MASK 0x8u
2840 #define LLWU_ME_WUME3_SHIFT 3
2841 #define LLWU_ME_WUME4_MASK 0x10u
2842 #define LLWU_ME_WUME4_SHIFT 4
2843 #define LLWU_ME_WUME5_MASK 0x20u
2844 #define LLWU_ME_WUME5_SHIFT 5
2845 #define LLWU_ME_WUME6_MASK 0x40u
2846 #define LLWU_ME_WUME6_SHIFT 6
2847 #define LLWU_ME_WUME7_MASK 0x80u
2848 #define LLWU_ME_WUME7_SHIFT 7
2849 /* F1 Bit Fields */
2850 #define LLWU_F1_WUF0_MASK 0x1u
2851 #define LLWU_F1_WUF0_SHIFT 0
2852 #define LLWU_F1_WUF1_MASK 0x2u
2853 #define LLWU_F1_WUF1_SHIFT 1
2854 #define LLWU_F1_WUF2_MASK 0x4u
2855 #define LLWU_F1_WUF2_SHIFT 2
2856 #define LLWU_F1_WUF3_MASK 0x8u
2857 #define LLWU_F1_WUF3_SHIFT 3
2858 #define LLWU_F1_WUF4_MASK 0x10u
2859 #define LLWU_F1_WUF4_SHIFT 4
2860 #define LLWU_F1_WUF5_MASK 0x20u
2861 #define LLWU_F1_WUF5_SHIFT 5
2862 #define LLWU_F1_WUF6_MASK 0x40u
2863 #define LLWU_F1_WUF6_SHIFT 6
2864 #define LLWU_F1_WUF7_MASK 0x80u
2865 #define LLWU_F1_WUF7_SHIFT 7
2866 /* F2 Bit Fields */
2867 #define LLWU_F2_WUF8_MASK 0x1u
2868 #define LLWU_F2_WUF8_SHIFT 0
2869 #define LLWU_F2_WUF9_MASK 0x2u
2870 #define LLWU_F2_WUF9_SHIFT 1
2871 #define LLWU_F2_WUF10_MASK 0x4u
2872 #define LLWU_F2_WUF10_SHIFT 2
2873 #define LLWU_F2_WUF11_MASK 0x8u
2874 #define LLWU_F2_WUF11_SHIFT 3
2875 #define LLWU_F2_WUF12_MASK 0x10u
2876 #define LLWU_F2_WUF12_SHIFT 4
2877 #define LLWU_F2_WUF13_MASK 0x20u
2878 #define LLWU_F2_WUF13_SHIFT 5
2879 #define LLWU_F2_WUF14_MASK 0x40u
2880 #define LLWU_F2_WUF14_SHIFT 6
2881 #define LLWU_F2_WUF15_MASK 0x80u
2882 #define LLWU_F2_WUF15_SHIFT 7
2883 /* F3 Bit Fields */
2884 #define LLWU_F3_MWUF0_MASK 0x1u
2885 #define LLWU_F3_MWUF0_SHIFT 0
2886 #define LLWU_F3_MWUF1_MASK 0x2u
2887 #define LLWU_F3_MWUF1_SHIFT 1
2888 #define LLWU_F3_MWUF2_MASK 0x4u
2889 #define LLWU_F3_MWUF2_SHIFT 2
2890 #define LLWU_F3_MWUF3_MASK 0x8u
2891 #define LLWU_F3_MWUF3_SHIFT 3
2892 #define LLWU_F3_MWUF4_MASK 0x10u
2893 #define LLWU_F3_MWUF4_SHIFT 4
2894 #define LLWU_F3_MWUF5_MASK 0x20u
2895 #define LLWU_F3_MWUF5_SHIFT 5
2896 #define LLWU_F3_MWUF6_MASK 0x40u
2897 #define LLWU_F3_MWUF6_SHIFT 6
2898 #define LLWU_F3_MWUF7_MASK 0x80u
2899 #define LLWU_F3_MWUF7_SHIFT 7
2900 /* FILT1 Bit Fields */
2901 #define LLWU_FILT1_FILTSEL_MASK 0xFu
2902 #define LLWU_FILT1_FILTSEL_SHIFT 0
2903 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
2904 #define LLWU_FILT1_FILTE_MASK 0x60u
2905 #define LLWU_FILT1_FILTE_SHIFT 5
2906 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
2907 #define LLWU_FILT1_FILTF_MASK 0x80u
2908 #define LLWU_FILT1_FILTF_SHIFT 7
2909 /* FILT2 Bit Fields */
2910 #define LLWU_FILT2_FILTSEL_MASK 0xFu
2911 #define LLWU_FILT2_FILTSEL_SHIFT 0
2912 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
2913 #define LLWU_FILT2_FILTE_MASK 0x60u
2914 #define LLWU_FILT2_FILTE_SHIFT 5
2915 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
2916 #define LLWU_FILT2_FILTF_MASK 0x80u
2917 #define LLWU_FILT2_FILTF_SHIFT 7
2918 /* RST Bit Fields */
2919 #define LLWU_RST_RSTFILT_MASK 0x1u
2920 #define LLWU_RST_RSTFILT_SHIFT 0
2921 #define LLWU_RST_LLRSTE_MASK 0x2u
2922 #define LLWU_RST_LLRSTE_SHIFT 1
2923
2924 /**
2925 * @}
2926 */ /* end of group LLWU_Register_Masks */
2927
2928
2929 /* LLWU - Peripheral instance base addresses */
2930 /** Peripheral LLWU base address */
2931 #define LLWU_BASE (0x4007C000u)
2932 /** Peripheral LLWU base pointer */
2933 #define LLWU ((LLWU_Type *)LLWU_BASE)
2934
2935 /**
2936 * @}
2937 */ /* end of group LLWU_Peripheral_Access_Layer */
2938
2939
2940 /* ----------------------------------------------------------------------------
2941 -- LPTMR Peripheral Access Layer
2942 ---------------------------------------------------------------------------- */
2943
2944 /**
2945 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
2946 * @{
2947 */
2948
2949 /** LPTMR - Register Layout Typedef */
2950 typedef struct {
2951 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
2952 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
2953 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
2954 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
2955 } LPTMR_Type;
2956
2957 /* ----------------------------------------------------------------------------
2958 -- LPTMR Register Masks
2959 ---------------------------------------------------------------------------- */
2960
2961 /**
2962 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
2963 * @{
2964 */
2965
2966 /* CSR Bit Fields */
2967 #define LPTMR_CSR_TEN_MASK 0x1u
2968 #define LPTMR_CSR_TEN_SHIFT 0
2969 #define LPTMR_CSR_TMS_MASK 0x2u
2970 #define LPTMR_CSR_TMS_SHIFT 1
2971 #define LPTMR_CSR_TFC_MASK 0x4u
2972 #define LPTMR_CSR_TFC_SHIFT 2
2973 #define LPTMR_CSR_TPP_MASK 0x8u
2974 #define LPTMR_CSR_TPP_SHIFT 3
2975 #define LPTMR_CSR_TPS_MASK 0x30u
2976 #define LPTMR_CSR_TPS_SHIFT 4
2977 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
2978 #define LPTMR_CSR_TIE_MASK 0x40u
2979 #define LPTMR_CSR_TIE_SHIFT 6
2980 #define LPTMR_CSR_TCF_MASK 0x80u
2981 #define LPTMR_CSR_TCF_SHIFT 7
2982 /* PSR Bit Fields */
2983 #define LPTMR_PSR_PCS_MASK 0x3u
2984 #define LPTMR_PSR_PCS_SHIFT 0
2985 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
2986 #define LPTMR_PSR_PBYP_MASK 0x4u
2987 #define LPTMR_PSR_PBYP_SHIFT 2
2988 #define LPTMR_PSR_PRESCALE_MASK 0x78u
2989 #define LPTMR_PSR_PRESCALE_SHIFT 3
2990 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
2991 /* CMR Bit Fields */
2992 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
2993 #define LPTMR_CMR_COMPARE_SHIFT 0
2994 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
2995 /* CNR Bit Fields */
2996 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
2997 #define LPTMR_CNR_COUNTER_SHIFT 0
2998 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
2999
3000 /**
3001 * @}
3002 */ /* end of group LPTMR_Register_Masks */
3003
3004
3005 /* LPTMR - Peripheral instance base addresses */
3006 /** Peripheral LPTMR0 base address */
3007 #define LPTMR0_BASE (0x40040000u)
3008 /** Peripheral LPTMR0 base pointer */
3009 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
3010
3011 /**
3012 * @}
3013 */ /* end of group LPTMR_Peripheral_Access_Layer */
3014
3015
3016 /* ----------------------------------------------------------------------------
3017 -- MCG Peripheral Access Layer
3018 ---------------------------------------------------------------------------- */
3019
3020 /**
3021 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
3022 * @{
3023 */
3024
3025 /** MCG - Register Layout Typedef */
3026 typedef struct {
3027 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
3028 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
3029 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
3030 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
3031 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
3032 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
3033 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
3034 uint8_t RESERVED_0[1];
3035 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
3036 uint8_t RESERVED_1[1];
3037 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
3038 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
3039 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
3040 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
3041 } MCG_Type;
3042
3043 /* ----------------------------------------------------------------------------
3044 -- MCG Register Masks
3045 ---------------------------------------------------------------------------- */
3046
3047 /**
3048 * @addtogroup MCG_Register_Masks MCG Register Masks
3049 * @{
3050 */
3051
3052 /* C1 Bit Fields */
3053 #define MCG_C1_IREFSTEN_MASK 0x1u
3054 #define MCG_C1_IREFSTEN_SHIFT 0
3055 #define MCG_C1_IRCLKEN_MASK 0x2u
3056 #define MCG_C1_IRCLKEN_SHIFT 1
3057 #define MCG_C1_IREFS_MASK 0x4u
3058 #define MCG_C1_IREFS_SHIFT 2
3059 #define MCG_C1_FRDIV_MASK 0x38u
3060 #define MCG_C1_FRDIV_SHIFT 3
3061 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
3062 #define MCG_C1_CLKS_MASK 0xC0u
3063 #define MCG_C1_CLKS_SHIFT 6
3064 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
3065 /* C2 Bit Fields */
3066 #define MCG_C2_IRCS_MASK 0x1u
3067 #define MCG_C2_IRCS_SHIFT 0
3068 #define MCG_C2_LP_MASK 0x2u
3069 #define MCG_C2_LP_SHIFT 1
3070 #define MCG_C2_EREFS0_MASK 0x4u
3071 #define MCG_C2_EREFS0_SHIFT 2
3072 #define MCG_C2_HGO0_MASK 0x8u
3073 #define MCG_C2_HGO0_SHIFT 3
3074 #define MCG_C2_RANGE0_MASK 0x30u
3075 #define MCG_C2_RANGE0_SHIFT 4
3076 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
3077 #define MCG_C2_LOCRE0_MASK 0x80u
3078 #define MCG_C2_LOCRE0_SHIFT 7
3079 /* C3 Bit Fields */
3080 #define MCG_C3_SCTRIM_MASK 0xFFu
3081 #define MCG_C3_SCTRIM_SHIFT 0
3082 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
3083 /* C4 Bit Fields */
3084 #define MCG_C4_SCFTRIM_MASK 0x1u
3085 #define MCG_C4_SCFTRIM_SHIFT 0
3086 #define MCG_C4_FCTRIM_MASK 0x1Eu
3087 #define MCG_C4_FCTRIM_SHIFT 1
3088 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
3089 #define MCG_C4_DRST_DRS_MASK 0x60u
3090 #define MCG_C4_DRST_DRS_SHIFT 5
3091 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
3092 #define MCG_C4_DMX32_MASK 0x80u
3093 #define MCG_C4_DMX32_SHIFT 7
3094 /* C5 Bit Fields */
3095 #define MCG_C5_PRDIV0_MASK 0x1Fu
3096 #define MCG_C5_PRDIV0_SHIFT 0
3097 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
3098 #define MCG_C5_PLLSTEN0_MASK 0x20u
3099 #define MCG_C5_PLLSTEN0_SHIFT 5
3100 #define MCG_C5_PLLCLKEN0_MASK 0x40u
3101 #define MCG_C5_PLLCLKEN0_SHIFT 6
3102 /* C6 Bit Fields */
3103 #define MCG_C6_VDIV0_MASK 0x1Fu
3104 #define MCG_C6_VDIV0_SHIFT 0
3105 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
3106 #define MCG_C6_CME0_MASK 0x20u
3107 #define MCG_C6_CME0_SHIFT 5
3108 #define MCG_C6_PLLS_MASK 0x40u
3109 #define MCG_C6_PLLS_SHIFT 6
3110 #define MCG_C6_LOLIE0_MASK 0x80u
3111 #define MCG_C6_LOLIE0_SHIFT 7
3112 /* S Bit Fields */
3113 #define MCG_S_IRCST_MASK 0x1u
3114 #define MCG_S_IRCST_SHIFT 0
3115 #define MCG_S_OSCINIT0_MASK 0x2u
3116 #define MCG_S_OSCINIT0_SHIFT 1
3117 #define MCG_S_CLKST_MASK 0xCu
3118 #define MCG_S_CLKST_SHIFT 2
3119 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
3120 #define MCG_S_IREFST_MASK 0x10u
3121 #define MCG_S_IREFST_SHIFT 4
3122 #define MCG_S_PLLST_MASK 0x20u
3123 #define MCG_S_PLLST_SHIFT 5
3124 #define MCG_S_LOCK0_MASK 0x40u
3125 #define MCG_S_LOCK0_SHIFT 6
3126 #define MCG_S_LOLS0_MASK 0x80u
3127 #define MCG_S_LOLS0_SHIFT 7
3128 /* SC Bit Fields */
3129 #define MCG_SC_LOCS0_MASK 0x1u
3130 #define MCG_SC_LOCS0_SHIFT 0
3131 #define MCG_SC_FCRDIV_MASK 0xEu
3132 #define MCG_SC_FCRDIV_SHIFT 1
3133 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
3134 #define MCG_SC_FLTPRSRV_MASK 0x10u
3135 #define MCG_SC_FLTPRSRV_SHIFT 4
3136 #define MCG_SC_ATMF_MASK 0x20u
3137 #define MCG_SC_ATMF_SHIFT 5
3138 #define MCG_SC_ATMS_MASK 0x40u
3139 #define MCG_SC_ATMS_SHIFT 6
3140 #define MCG_SC_ATME_MASK 0x80u
3141 #define MCG_SC_ATME_SHIFT 7
3142 /* ATCVH Bit Fields */
3143 #define MCG_ATCVH_ATCVH_MASK 0xFFu
3144 #define MCG_ATCVH_ATCVH_SHIFT 0
3145 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
3146 /* ATCVL Bit Fields */
3147 #define MCG_ATCVL_ATCVL_MASK 0xFFu
3148 #define MCG_ATCVL_ATCVL_SHIFT 0
3149 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
3150 /* C7 Bit Fields */
3151 #define MCG_C7_OSCSEL_MASK 0x1u
3152 #define MCG_C7_OSCSEL_SHIFT 0
3153 /* C8 Bit Fields */
3154 #define MCG_C8_LOCS1_MASK 0x1u
3155 #define MCG_C8_LOCS1_SHIFT 0
3156 #define MCG_C8_CME1_MASK 0x20u
3157 #define MCG_C8_CME1_SHIFT 5
3158 #define MCG_C8_LOLRE_MASK 0x40u
3159 #define MCG_C8_LOLRE_SHIFT 6
3160 #define MCG_C8_LOCRE1_MASK 0x80u
3161 #define MCG_C8_LOCRE1_SHIFT 7
3162
3163 /**
3164 * @}
3165 */ /* end of group MCG_Register_Masks */
3166
3167
3168 /* MCG - Peripheral instance base addresses */
3169 /** Peripheral MCG base address */
3170 #define MCG_BASE (0x40064000u)
3171 /** Peripheral MCG base pointer */
3172 #define MCG ((MCG_Type *)MCG_BASE)
3173
3174 /**
3175 * @}
3176 */ /* end of group MCG_Peripheral_Access_Layer */
3177
3178
3179 /* ----------------------------------------------------------------------------
3180 -- NV Peripheral Access Layer
3181 ---------------------------------------------------------------------------- */
3182
3183 /**
3184 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
3185 * @{
3186 */
3187
3188 /** NV - Register Layout Typedef */
3189 typedef struct {
3190 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
3191 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
3192 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
3193 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
3194 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
3195 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
3196 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
3197 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
3198 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
3199 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
3200 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
3201 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
3202 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
3203 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
3204 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
3205 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
3206 } NV_Type;
3207
3208 /* ----------------------------------------------------------------------------
3209 -- NV Register Masks
3210 ---------------------------------------------------------------------------- */
3211
3212 /**
3213 * @addtogroup NV_Register_Masks NV Register Masks
3214 * @{
3215 */
3216
3217 /* BACKKEY3 Bit Fields */
3218 #define NV_BACKKEY3_KEY_MASK 0xFFu
3219 #define NV_BACKKEY3_KEY_SHIFT 0
3220 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
3221 /* BACKKEY2 Bit Fields */
3222 #define NV_BACKKEY2_KEY_MASK 0xFFu
3223 #define NV_BACKKEY2_KEY_SHIFT 0
3224 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
3225 /* BACKKEY1 Bit Fields */
3226 #define NV_BACKKEY1_KEY_MASK 0xFFu
3227 #define NV_BACKKEY1_KEY_SHIFT 0
3228 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
3229 /* BACKKEY0 Bit Fields */
3230 #define NV_BACKKEY0_KEY_MASK 0xFFu
3231 #define NV_BACKKEY0_KEY_SHIFT 0
3232 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
3233 /* BACKKEY7 Bit Fields */
3234 #define NV_BACKKEY7_KEY_MASK 0xFFu
3235 #define NV_BACKKEY7_KEY_SHIFT 0
3236 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
3237 /* BACKKEY6 Bit Fields */
3238 #define NV_BACKKEY6_KEY_MASK 0xFFu
3239 #define NV_BACKKEY6_KEY_SHIFT 0
3240 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
3241 /* BACKKEY5 Bit Fields */
3242 #define NV_BACKKEY5_KEY_MASK 0xFFu
3243 #define NV_BACKKEY5_KEY_SHIFT 0
3244 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
3245 /* BACKKEY4 Bit Fields */
3246 #define NV_BACKKEY4_KEY_MASK 0xFFu
3247 #define NV_BACKKEY4_KEY_SHIFT 0
3248 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
3249 /* FPROT3 Bit Fields */
3250 #define NV_FPROT3_PROT_MASK 0xFFu
3251 #define NV_FPROT3_PROT_SHIFT 0
3252 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
3253 /* FPROT2 Bit Fields */
3254 #define NV_FPROT2_PROT_MASK 0xFFu
3255 #define NV_FPROT2_PROT_SHIFT 0
3256 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
3257 /* FPROT1 Bit Fields */
3258 #define NV_FPROT1_PROT_MASK 0xFFu
3259 #define NV_FPROT1_PROT_SHIFT 0
3260 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
3261 /* FPROT0 Bit Fields */
3262 #define NV_FPROT0_PROT_MASK 0xFFu
3263 #define NV_FPROT0_PROT_SHIFT 0
3264 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
3265 /* FSEC Bit Fields */
3266 #define NV_FSEC_SEC_MASK 0x3u
3267 #define NV_FSEC_SEC_SHIFT 0
3268 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
3269 #define NV_FSEC_FSLACC_MASK 0xCu
3270 #define NV_FSEC_FSLACC_SHIFT 2
3271 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
3272 #define NV_FSEC_MEEN_MASK 0x30u
3273 #define NV_FSEC_MEEN_SHIFT 4
3274 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
3275 #define NV_FSEC_KEYEN_MASK 0xC0u
3276 #define NV_FSEC_KEYEN_SHIFT 6
3277 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
3278 /* FOPT Bit Fields */
3279 #define NV_FOPT_LPBOOT_MASK 0x1u
3280 #define NV_FOPT_LPBOOT_SHIFT 0
3281 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
3282 #define NV_FOPT_EZPORT_DIS_SHIFT 1
3283 /* FEPROT Bit Fields */
3284 #define NV_FEPROT_EPROT_MASK 0xFFu
3285 #define NV_FEPROT_EPROT_SHIFT 0
3286 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
3287 /* FDPROT Bit Fields */
3288 #define NV_FDPROT_DPROT_MASK 0xFFu
3289 #define NV_FDPROT_DPROT_SHIFT 0
3290 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
3291
3292 /**
3293 * @}
3294 */ /* end of group NV_Register_Masks */
3295
3296
3297 /* NV - Peripheral instance base addresses */
3298 /** Peripheral FTFL_FlashConfig base address */
3299 #define FTFL_FlashConfig_BASE (0x400u)
3300 /** Peripheral FTFL_FlashConfig base pointer */
3301 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
3302
3303 /**
3304 * @}
3305 */ /* end of group NV_Peripheral_Access_Layer */
3306
3307
3308 /* ----------------------------------------------------------------------------
3309 -- OSC Peripheral Access Layer
3310 ---------------------------------------------------------------------------- */
3311
3312 /**
3313 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
3314 * @{
3315 */
3316
3317 /** OSC - Register Layout Typedef */
3318 typedef struct {
3319 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
3320 } OSC_Type;
3321
3322 /* ----------------------------------------------------------------------------
3323 -- OSC Register Masks
3324 ---------------------------------------------------------------------------- */
3325
3326 /**
3327 * @addtogroup OSC_Register_Masks OSC Register Masks
3328 * @{
3329 */
3330
3331 /* CR Bit Fields */
3332 #define OSC_CR_SC16P_MASK 0x1u
3333 #define OSC_CR_SC16P_SHIFT 0
3334 #define OSC_CR_SC8P_MASK 0x2u
3335 #define OSC_CR_SC8P_SHIFT 1
3336 #define OSC_CR_SC4P_MASK 0x4u
3337 #define OSC_CR_SC4P_SHIFT 2
3338 #define OSC_CR_SC2P_MASK 0x8u
3339 #define OSC_CR_SC2P_SHIFT 3
3340 #define OSC_CR_EREFSTEN_MASK 0x20u
3341 #define OSC_CR_EREFSTEN_SHIFT 5
3342 #define OSC_CR_ERCLKEN_MASK 0x80u
3343 #define OSC_CR_ERCLKEN_SHIFT 7
3344
3345 /**
3346 * @}
3347 */ /* end of group OSC_Register_Masks */
3348
3349
3350 /* OSC - Peripheral instance base addresses */
3351 /** Peripheral OSC0 base address */
3352 #define OSC0_BASE (0x40065000u)
3353 /** Peripheral OSC0 base pointer */
3354 #define OSC0 ((OSC_Type *)OSC0_BASE)
3355
3356 /**
3357 * @}
3358 */ /* end of group OSC_Peripheral_Access_Layer */
3359
3360
3361 /* ----------------------------------------------------------------------------
3362 -- PDB Peripheral Access Layer
3363 ---------------------------------------------------------------------------- */
3364
3365 /**
3366 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
3367 * @{
3368 */
3369
3370 /** PDB - Register Layout Typedef */
3371 typedef struct {
3372 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
3373 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
3374 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
3375 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
3376 struct { /* offset: 0x10, array step: 0x10 */
3377 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
3378 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
3379 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
3380 } CH[1];
3381 uint8_t RESERVED_0[368];
3382 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
3383 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
3384 } PDB_Type;
3385
3386 /* ----------------------------------------------------------------------------
3387 -- PDB Register Masks
3388 ---------------------------------------------------------------------------- */
3389
3390 /**
3391 * @addtogroup PDB_Register_Masks PDB Register Masks
3392 * @{
3393 */
3394
3395 /* SC Bit Fields */
3396 #define PDB_SC_LDOK_MASK 0x1u
3397 #define PDB_SC_LDOK_SHIFT 0
3398 #define PDB_SC_CONT_MASK 0x2u
3399 #define PDB_SC_CONT_SHIFT 1
3400 #define PDB_SC_MULT_MASK 0xCu
3401 #define PDB_SC_MULT_SHIFT 2
3402 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
3403 #define PDB_SC_PDBIE_MASK 0x20u
3404 #define PDB_SC_PDBIE_SHIFT 5
3405 #define PDB_SC_PDBIF_MASK 0x40u
3406 #define PDB_SC_PDBIF_SHIFT 6
3407 #define PDB_SC_PDBEN_MASK 0x80u
3408 #define PDB_SC_PDBEN_SHIFT 7
3409 #define PDB_SC_TRGSEL_MASK 0xF00u
3410 #define PDB_SC_TRGSEL_SHIFT 8
3411 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
3412 #define PDB_SC_PRESCALER_MASK 0x7000u
3413 #define PDB_SC_PRESCALER_SHIFT 12
3414 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
3415 #define PDB_SC_DMAEN_MASK 0x8000u
3416 #define PDB_SC_DMAEN_SHIFT 15
3417 #define PDB_SC_SWTRIG_MASK 0x10000u
3418 #define PDB_SC_SWTRIG_SHIFT 16
3419 #define PDB_SC_PDBEIE_MASK 0x20000u
3420 #define PDB_SC_PDBEIE_SHIFT 17
3421 #define PDB_SC_LDMOD_MASK 0xC0000u
3422 #define PDB_SC_LDMOD_SHIFT 18
3423 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
3424 /* MOD Bit Fields */
3425 #define PDB_MOD_MOD_MASK 0xFFFFu
3426 #define PDB_MOD_MOD_SHIFT 0
3427 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
3428 /* CNT Bit Fields */
3429 #define PDB_CNT_CNT_MASK 0xFFFFu
3430 #define PDB_CNT_CNT_SHIFT 0
3431 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
3432 /* IDLY Bit Fields */
3433 #define PDB_IDLY_IDLY_MASK 0xFFFFu
3434 #define PDB_IDLY_IDLY_SHIFT 0
3435 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
3436 /* C1 Bit Fields */
3437 #define PDB_C1_EN_MASK 0xFFu
3438 #define PDB_C1_EN_SHIFT 0
3439 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
3440 #define PDB_C1_TOS_MASK 0xFF00u
3441 #define PDB_C1_TOS_SHIFT 8
3442 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
3443 #define PDB_C1_BB_MASK 0xFF0000u
3444 #define PDB_C1_BB_SHIFT 16
3445 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
3446 /* S Bit Fields */
3447 #define PDB_S_ERR_MASK 0xFFu
3448 #define PDB_S_ERR_SHIFT 0
3449 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
3450 #define PDB_S_CF_MASK 0xFF0000u
3451 #define PDB_S_CF_SHIFT 16
3452 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
3453 /* DLY Bit Fields */
3454 #define PDB_DLY_DLY_MASK 0xFFFFu
3455 #define PDB_DLY_DLY_SHIFT 0
3456 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
3457 /* POEN Bit Fields */
3458 #define PDB_POEN_POEN_MASK 0xFFu
3459 #define PDB_POEN_POEN_SHIFT 0
3460 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
3461 /* PODLY Bit Fields */
3462 #define PDB_PODLY_DLY2_MASK 0xFFFFu
3463 #define PDB_PODLY_DLY2_SHIFT 0
3464 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
3465 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
3466 #define PDB_PODLY_DLY1_SHIFT 16
3467 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
3468
3469 /**
3470 * @}
3471 */ /* end of group PDB_Register_Masks */
3472
3473
3474 /* PDB - Peripheral instance base addresses */
3475 /** Peripheral PDB0 base address */
3476 #define PDB0_BASE (0x40036000u)
3477 /** Peripheral PDB0 base pointer */
3478 #define PDB0 ((PDB_Type *)PDB0_BASE)
3479
3480 /**
3481 * @}
3482 */ /* end of group PDB_Peripheral_Access_Layer */
3483
3484
3485 /* ----------------------------------------------------------------------------
3486 -- PIT Peripheral Access Layer
3487 ---------------------------------------------------------------------------- */
3488
3489 /**
3490 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
3491 * @{
3492 */
3493
3494 /** PIT - Register Layout Typedef */
3495 typedef struct {
3496 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
3497 uint8_t RESERVED_0[252];
3498 struct { /* offset: 0x100, array step: 0x10 */
3499 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
3500 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
3501 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
3502 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
3503 } CHANNEL[4];
3504 } PIT_Type;
3505
3506 /* ----------------------------------------------------------------------------
3507 -- PIT Register Masks
3508 ---------------------------------------------------------------------------- */
3509
3510 /**
3511 * @addtogroup PIT_Register_Masks PIT Register Masks
3512 * @{
3513 */
3514
3515 /* MCR Bit Fields */
3516 #define PIT_MCR_FRZ_MASK 0x1u
3517 #define PIT_MCR_FRZ_SHIFT 0
3518 #define PIT_MCR_MDIS_MASK 0x2u
3519 #define PIT_MCR_MDIS_SHIFT 1
3520 /* LDVAL Bit Fields */
3521 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
3522 #define PIT_LDVAL_TSV_SHIFT 0
3523 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
3524 /* CVAL Bit Fields */
3525 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
3526 #define PIT_CVAL_TVL_SHIFT 0
3527 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
3528 /* TCTRL Bit Fields */
3529 #define PIT_TCTRL_TEN_MASK 0x1u
3530 #define PIT_TCTRL_TEN_SHIFT 0
3531 #define PIT_TCTRL_TIE_MASK 0x2u
3532 #define PIT_TCTRL_TIE_SHIFT 1
3533 /* TFLG Bit Fields */
3534 #define PIT_TFLG_TIF_MASK 0x1u
3535 #define PIT_TFLG_TIF_SHIFT 0
3536
3537 /**
3538 * @}
3539 */ /* end of group PIT_Register_Masks */
3540
3541
3542 /* PIT - Peripheral instance base addresses */
3543 /** Peripheral PIT base address */
3544 #define PIT_BASE (0x40037000u)
3545 /** Peripheral PIT base pointer */
3546 #define PIT ((PIT_Type *)PIT_BASE)
3547
3548 /**
3549 * @}
3550 */ /* end of group PIT_Peripheral_Access_Layer */
3551
3552
3553 /* ----------------------------------------------------------------------------
3554 -- PMC Peripheral Access Layer
3555 ---------------------------------------------------------------------------- */
3556
3557 /**
3558 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
3559 * @{
3560 */
3561
3562 /** PMC - Register Layout Typedef */
3563 typedef struct {
3564 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
3565 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
3566 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
3567 } PMC_Type;
3568
3569 /* ----------------------------------------------------------------------------
3570 -- PMC Register Masks
3571 ---------------------------------------------------------------------------- */
3572
3573 /**
3574 * @addtogroup PMC_Register_Masks PMC Register Masks
3575 * @{
3576 */
3577
3578 /* LVDSC1 Bit Fields */
3579 #define PMC_LVDSC1_LVDV_MASK 0x3u
3580 #define PMC_LVDSC1_LVDV_SHIFT 0
3581 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
3582 #define PMC_LVDSC1_LVDRE_MASK 0x10u
3583 #define PMC_LVDSC1_LVDRE_SHIFT 4
3584 #define PMC_LVDSC1_LVDIE_MASK 0x20u
3585 #define PMC_LVDSC1_LVDIE_SHIFT 5
3586 #define PMC_LVDSC1_LVDACK_MASK 0x40u
3587 #define PMC_LVDSC1_LVDACK_SHIFT 6
3588 #define PMC_LVDSC1_LVDF_MASK 0x80u
3589 #define PMC_LVDSC1_LVDF_SHIFT 7
3590 /* LVDSC2 Bit Fields */
3591 #define PMC_LVDSC2_LVWV_MASK 0x3u
3592 #define PMC_LVDSC2_LVWV_SHIFT 0
3593 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
3594 #define PMC_LVDSC2_LVWIE_MASK 0x20u
3595 #define PMC_LVDSC2_LVWIE_SHIFT 5
3596 #define PMC_LVDSC2_LVWACK_MASK 0x40u
3597 #define PMC_LVDSC2_LVWACK_SHIFT 6
3598 #define PMC_LVDSC2_LVWF_MASK 0x80u
3599 #define PMC_LVDSC2_LVWF_SHIFT 7
3600 /* REGSC Bit Fields */
3601 #define PMC_REGSC_BGBE_MASK 0x1u
3602 #define PMC_REGSC_BGBE_SHIFT 0
3603 #define PMC_REGSC_REGONS_MASK 0x4u
3604 #define PMC_REGSC_REGONS_SHIFT 2
3605 #define PMC_REGSC_ACKISO_MASK 0x8u
3606 #define PMC_REGSC_ACKISO_SHIFT 3
3607
3608 /**
3609 * @}
3610 */ /* end of group PMC_Register_Masks */
3611
3612
3613 /* PMC - Peripheral instance base addresses */
3614 /** Peripheral PMC base address */
3615 #define PMC_BASE (0x4007D000u)
3616 /** Peripheral PMC base pointer */
3617 #define PMC ((PMC_Type *)PMC_BASE)
3618
3619 /**
3620 * @}
3621 */ /* end of group PMC_Peripheral_Access_Layer */
3622
3623
3624 /* ----------------------------------------------------------------------------
3625 -- PORT Peripheral Access Layer
3626 ---------------------------------------------------------------------------- */
3627
3628 /**
3629 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
3630 * @{
3631 */
3632
3633 /** PORT - Register Layout Typedef */
3634 typedef struct {
3635 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
3636 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
3637 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
3638 uint8_t RESERVED_0[24];
3639 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
3640 uint8_t RESERVED_1[28];
3641 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
3642 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
3643 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
3644 } PORT_Type;
3645
3646 /* ----------------------------------------------------------------------------
3647 -- PORT Register Masks
3648 ---------------------------------------------------------------------------- */
3649
3650 /**
3651 * @addtogroup PORT_Register_Masks PORT Register Masks
3652 * @{
3653 */
3654
3655 /* PCR Bit Fields */
3656 #define PORT_PCR_PS_MASK 0x1u
3657 #define PORT_PCR_PS_SHIFT 0
3658 #define PORT_PCR_PE_MASK 0x2u
3659 #define PORT_PCR_PE_SHIFT 1
3660 #define PORT_PCR_SRE_MASK 0x4u
3661 #define PORT_PCR_SRE_SHIFT 2
3662 #define PORT_PCR_PFE_MASK 0x10u
3663 #define PORT_PCR_PFE_SHIFT 4
3664 #define PORT_PCR_ODE_MASK 0x20u
3665 #define PORT_PCR_ODE_SHIFT 5
3666 #define PORT_PCR_DSE_MASK 0x40u
3667 #define PORT_PCR_DSE_SHIFT 6
3668 #define PORT_PCR_MUX_MASK 0x700u
3669 #define PORT_PCR_MUX_SHIFT 8
3670 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
3671 #define PORT_PCR_LK_MASK 0x8000u
3672 #define PORT_PCR_LK_SHIFT 15
3673 #define PORT_PCR_IRQC_MASK 0xF0000u
3674 #define PORT_PCR_IRQC_SHIFT 16
3675 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
3676 #define PORT_PCR_ISF_MASK 0x1000000u
3677 #define PORT_PCR_ISF_SHIFT 24
3678 /* GPCLR Bit Fields */
3679 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
3680 #define PORT_GPCLR_GPWD_SHIFT 0
3681 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
3682 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
3683 #define PORT_GPCLR_GPWE_SHIFT 16
3684 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
3685 /* GPCHR Bit Fields */
3686 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
3687 #define PORT_GPCHR_GPWD_SHIFT 0
3688 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
3689 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
3690 #define PORT_GPCHR_GPWE_SHIFT 16
3691 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
3692 /* ISFR Bit Fields */
3693 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
3694 #define PORT_ISFR_ISF_SHIFT 0
3695 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
3696 /* DFER Bit Fields */
3697 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
3698 #define PORT_DFER_DFE_SHIFT 0
3699 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
3700 /* DFCR Bit Fields */
3701 #define PORT_DFCR_CS_MASK 0x1u
3702 #define PORT_DFCR_CS_SHIFT 0
3703 /* DFWR Bit Fields */
3704 #define PORT_DFWR_FILT_MASK 0x1Fu
3705 #define PORT_DFWR_FILT_SHIFT 0
3706 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
3707
3708 /**
3709 * @}
3710 */ /* end of group PORT_Register_Masks */
3711
3712
3713 /* PORT - Peripheral instance base addresses */
3714 /** Peripheral PORTA base address */
3715 #define PORTA_BASE (0x40049000u)
3716 /** Peripheral PORTA base pointer */
3717 #define PORTA ((PORT_Type *)PORTA_BASE)
3718 /** Peripheral PORTB base address */
3719 #define PORTB_BASE (0x4004A000u)
3720 /** Peripheral PORTB base pointer */
3721 #define PORTB ((PORT_Type *)PORTB_BASE)
3722 /** Peripheral PORTC base address */
3723 #define PORTC_BASE (0x4004B000u)
3724 /** Peripheral PORTC base pointer */
3725 #define PORTC ((PORT_Type *)PORTC_BASE)
3726 /** Peripheral PORTD base address */
3727 #define PORTD_BASE (0x4004C000u)
3728 /** Peripheral PORTD base pointer */
3729 #define PORTD ((PORT_Type *)PORTD_BASE)
3730 /** Peripheral PORTE base address */
3731 #define PORTE_BASE (0x4004D000u)
3732 /** Peripheral PORTE base pointer */
3733 #define PORTE ((PORT_Type *)PORTE_BASE)
3734
3735 /**
3736 * @}
3737 */ /* end of group PORT_Peripheral_Access_Layer */
3738
3739
3740 /* ----------------------------------------------------------------------------
3741 -- RCM Peripheral Access Layer
3742 ---------------------------------------------------------------------------- */
3743
3744 /**
3745 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
3746 * @{
3747 */
3748
3749 /** RCM - Register Layout Typedef */
3750 typedef struct {
3751 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
3752 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
3753 uint8_t RESERVED_0[2];
3754 __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
3755 __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
3756 uint8_t RESERVED_1[1];
3757 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
3758 } RCM_Type;
3759
3760 /* ----------------------------------------------------------------------------
3761 -- RCM Register Masks
3762 ---------------------------------------------------------------------------- */
3763
3764 /**
3765 * @addtogroup RCM_Register_Masks RCM Register Masks
3766 * @{
3767 */
3768
3769 /* SRS0 Bit Fields */
3770 #define RCM_SRS0_WAKEUP_MASK 0x1u
3771 #define RCM_SRS0_WAKEUP_SHIFT 0
3772 #define RCM_SRS0_LVD_MASK 0x2u
3773 #define RCM_SRS0_LVD_SHIFT 1
3774 #define RCM_SRS0_LOC_MASK 0x4u
3775 #define RCM_SRS0_LOC_SHIFT 2
3776 #define RCM_SRS0_LOL_MASK 0x8u
3777 #define RCM_SRS0_LOL_SHIFT 3
3778 #define RCM_SRS0_WDOG_MASK 0x20u
3779 #define RCM_SRS0_WDOG_SHIFT 5
3780 #define RCM_SRS0_PIN_MASK 0x40u
3781 #define RCM_SRS0_PIN_SHIFT 6
3782 #define RCM_SRS0_POR_MASK 0x80u
3783 #define RCM_SRS0_POR_SHIFT 7
3784 /* SRS1 Bit Fields */
3785 #define RCM_SRS1_JTAG_MASK 0x1u
3786 #define RCM_SRS1_JTAG_SHIFT 0
3787 #define RCM_SRS1_LOCKUP_MASK 0x2u
3788 #define RCM_SRS1_LOCKUP_SHIFT 1
3789 #define RCM_SRS1_SW_MASK 0x4u
3790 #define RCM_SRS1_SW_SHIFT 2
3791 #define RCM_SRS1_MDM_AP_MASK 0x8u
3792 #define RCM_SRS1_MDM_AP_SHIFT 3
3793 #define RCM_SRS1_EZPT_MASK 0x10u
3794 #define RCM_SRS1_EZPT_SHIFT 4
3795 #define RCM_SRS1_SACKERR_MASK 0x20u
3796 #define RCM_SRS1_SACKERR_SHIFT 5
3797 /* RPFC Bit Fields */
3798 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
3799 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
3800 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
3801 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
3802 #define RCM_RPFC_RSTFLTSS_SHIFT 2
3803 /* RPFW Bit Fields */
3804 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
3805 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
3806 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
3807 /* MR Bit Fields */
3808 #define RCM_MR_EZP_MS_MASK 0x2u
3809 #define RCM_MR_EZP_MS_SHIFT 1
3810
3811 /**
3812 * @}
3813 */ /* end of group RCM_Register_Masks */
3814
3815
3816 /* RCM - Peripheral instance base addresses */
3817 /** Peripheral RCM base address */
3818 #define RCM_BASE (0x4007F000u)
3819 /** Peripheral RCM base pointer */
3820 #define RCM ((RCM_Type *)RCM_BASE)
3821
3822 /**
3823 * @}
3824 */ /* end of group RCM_Peripheral_Access_Layer */
3825
3826
3827 /* ----------------------------------------------------------------------------
3828 -- RFSYS Peripheral Access Layer
3829 ---------------------------------------------------------------------------- */
3830
3831 /**
3832 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
3833 * @{
3834 */
3835
3836 /** RFSYS - Register Layout Typedef */
3837 typedef struct {
3838 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
3839 } RFSYS_Type;
3840
3841 /* ----------------------------------------------------------------------------
3842 -- RFSYS Register Masks
3843 ---------------------------------------------------------------------------- */
3844
3845 /**
3846 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
3847 * @{
3848 */
3849
3850 /* REG Bit Fields */
3851 #define RFSYS_REG_LL_MASK 0xFFu
3852 #define RFSYS_REG_LL_SHIFT 0
3853 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
3854 #define RFSYS_REG_LH_MASK 0xFF00u
3855 #define RFSYS_REG_LH_SHIFT 8
3856 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
3857 #define RFSYS_REG_HL_MASK 0xFF0000u
3858 #define RFSYS_REG_HL_SHIFT 16
3859 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
3860 #define RFSYS_REG_HH_MASK 0xFF000000u
3861 #define RFSYS_REG_HH_SHIFT 24
3862 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
3863
3864 /**
3865 * @}
3866 */ /* end of group RFSYS_Register_Masks */
3867
3868
3869 /* RFSYS - Peripheral instance base addresses */
3870 /** Peripheral RFSYS base address */
3871 #define RFSYS_BASE (0x40041000u)
3872 /** Peripheral RFSYS base pointer */
3873 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
3874
3875 /**
3876 * @}
3877 */ /* end of group RFSYS_Peripheral_Access_Layer */
3878
3879
3880 /* ----------------------------------------------------------------------------
3881 -- RFVBAT Peripheral Access Layer
3882 ---------------------------------------------------------------------------- */
3883
3884 /**
3885 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
3886 * @{
3887 */
3888
3889 /** RFVBAT - Register Layout Typedef */
3890 typedef struct {
3891 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
3892 } RFVBAT_Type;
3893
3894 /* ----------------------------------------------------------------------------
3895 -- RFVBAT Register Masks
3896 ---------------------------------------------------------------------------- */
3897
3898 /**
3899 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
3900 * @{
3901 */
3902
3903 /* REG Bit Fields */
3904 #define RFVBAT_REG_LL_MASK 0xFFu
3905 #define RFVBAT_REG_LL_SHIFT 0
3906 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
3907 #define RFVBAT_REG_LH_MASK 0xFF00u
3908 #define RFVBAT_REG_LH_SHIFT 8
3909 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
3910 #define RFVBAT_REG_HL_MASK 0xFF0000u
3911 #define RFVBAT_REG_HL_SHIFT 16
3912 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
3913 #define RFVBAT_REG_HH_MASK 0xFF000000u
3914 #define RFVBAT_REG_HH_SHIFT 24
3915 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
3916
3917 /**
3918 * @}
3919 */ /* end of group RFVBAT_Register_Masks */
3920
3921
3922 /* RFVBAT - Peripheral instance base addresses */
3923 /** Peripheral RFVBAT base address */
3924 #define RFVBAT_BASE (0x4003E000u)
3925 /** Peripheral RFVBAT base pointer */
3926 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
3927
3928 /**
3929 * @}
3930 */ /* end of group RFVBAT_Peripheral_Access_Layer */
3931
3932
3933 /* ----------------------------------------------------------------------------
3934 -- RTC Peripheral Access Layer
3935 ---------------------------------------------------------------------------- */
3936
3937 /**
3938 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
3939 * @{
3940 */
3941
3942 /** RTC - Register Layout Typedef */
3943 typedef struct {
3944 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
3945 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
3946 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
3947 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
3948 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
3949 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
3950 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
3951 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
3952 uint8_t RESERVED_0[2016];
3953 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
3954 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
3955 } RTC_Type;
3956
3957 /* ----------------------------------------------------------------------------
3958 -- RTC Register Masks
3959 ---------------------------------------------------------------------------- */
3960
3961 /**
3962 * @addtogroup RTC_Register_Masks RTC Register Masks
3963 * @{
3964 */
3965
3966 /* TSR Bit Fields */
3967 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
3968 #define RTC_TSR_TSR_SHIFT 0
3969 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
3970 /* TPR Bit Fields */
3971 #define RTC_TPR_TPR_MASK 0xFFFFu
3972 #define RTC_TPR_TPR_SHIFT 0
3973 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
3974 /* TAR Bit Fields */
3975 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
3976 #define RTC_TAR_TAR_SHIFT 0
3977 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
3978 /* TCR Bit Fields */
3979 #define RTC_TCR_TCR_MASK 0xFFu
3980 #define RTC_TCR_TCR_SHIFT 0
3981 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
3982 #define RTC_TCR_CIR_MASK 0xFF00u
3983 #define RTC_TCR_CIR_SHIFT 8
3984 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
3985 #define RTC_TCR_TCV_MASK 0xFF0000u
3986 #define RTC_TCR_TCV_SHIFT 16
3987 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
3988 #define RTC_TCR_CIC_MASK 0xFF000000u
3989 #define RTC_TCR_CIC_SHIFT 24
3990 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
3991 /* CR Bit Fields */
3992 #define RTC_CR_SWR_MASK 0x1u
3993 #define RTC_CR_SWR_SHIFT 0
3994 #define RTC_CR_WPE_MASK 0x2u
3995 #define RTC_CR_WPE_SHIFT 1
3996 #define RTC_CR_SUP_MASK 0x4u
3997 #define RTC_CR_SUP_SHIFT 2
3998 #define RTC_CR_UM_MASK 0x8u
3999 #define RTC_CR_UM_SHIFT 3
4000 #define RTC_CR_OSCE_MASK 0x100u
4001 #define RTC_CR_OSCE_SHIFT 8
4002 #define RTC_CR_CLKO_MASK 0x200u
4003 #define RTC_CR_CLKO_SHIFT 9
4004 #define RTC_CR_SC16P_MASK 0x400u
4005 #define RTC_CR_SC16P_SHIFT 10
4006 #define RTC_CR_SC8P_MASK 0x800u
4007 #define RTC_CR_SC8P_SHIFT 11
4008 #define RTC_CR_SC4P_MASK 0x1000u
4009 #define RTC_CR_SC4P_SHIFT 12
4010 #define RTC_CR_SC2P_MASK 0x2000u
4011 #define RTC_CR_SC2P_SHIFT 13
4012 /* SR Bit Fields */
4013 #define RTC_SR_TIF_MASK 0x1u
4014 #define RTC_SR_TIF_SHIFT 0
4015 #define RTC_SR_TOF_MASK 0x2u
4016 #define RTC_SR_TOF_SHIFT 1
4017 #define RTC_SR_TAF_MASK 0x4u
4018 #define RTC_SR_TAF_SHIFT 2
4019 #define RTC_SR_TCE_MASK 0x10u
4020 #define RTC_SR_TCE_SHIFT 4
4021 /* LR Bit Fields */
4022 #define RTC_LR_TCL_MASK 0x8u
4023 #define RTC_LR_TCL_SHIFT 3
4024 #define RTC_LR_CRL_MASK 0x10u
4025 #define RTC_LR_CRL_SHIFT 4
4026 #define RTC_LR_SRL_MASK 0x20u
4027 #define RTC_LR_SRL_SHIFT 5
4028 #define RTC_LR_LRL_MASK 0x40u
4029 #define RTC_LR_LRL_SHIFT 6
4030 /* IER Bit Fields */
4031 #define RTC_IER_TIIE_MASK 0x1u
4032 #define RTC_IER_TIIE_SHIFT 0
4033 #define RTC_IER_TOIE_MASK 0x2u
4034 #define RTC_IER_TOIE_SHIFT 1
4035 #define RTC_IER_TAIE_MASK 0x4u
4036 #define RTC_IER_TAIE_SHIFT 2
4037 #define RTC_IER_TSIE_MASK 0x10u
4038 #define RTC_IER_TSIE_SHIFT 4
4039 /* WAR Bit Fields */
4040 #define RTC_WAR_TSRW_MASK 0x1u
4041 #define RTC_WAR_TSRW_SHIFT 0
4042 #define RTC_WAR_TPRW_MASK 0x2u
4043 #define RTC_WAR_TPRW_SHIFT 1
4044 #define RTC_WAR_TARW_MASK 0x4u
4045 #define RTC_WAR_TARW_SHIFT 2
4046 #define RTC_WAR_TCRW_MASK 0x8u
4047 #define RTC_WAR_TCRW_SHIFT 3
4048 #define RTC_WAR_CRW_MASK 0x10u
4049 #define RTC_WAR_CRW_SHIFT 4
4050 #define RTC_WAR_SRW_MASK 0x20u
4051 #define RTC_WAR_SRW_SHIFT 5
4052 #define RTC_WAR_LRW_MASK 0x40u
4053 #define RTC_WAR_LRW_SHIFT 6
4054 #define RTC_WAR_IERW_MASK 0x80u
4055 #define RTC_WAR_IERW_SHIFT 7
4056 /* RAR Bit Fields */
4057 #define RTC_RAR_TSRR_MASK 0x1u
4058 #define RTC_RAR_TSRR_SHIFT 0
4059 #define RTC_RAR_TPRR_MASK 0x2u
4060 #define RTC_RAR_TPRR_SHIFT 1
4061 #define RTC_RAR_TARR_MASK 0x4u
4062 #define RTC_RAR_TARR_SHIFT 2
4063 #define RTC_RAR_TCRR_MASK 0x8u
4064 #define RTC_RAR_TCRR_SHIFT 3
4065 #define RTC_RAR_CRR_MASK 0x10u
4066 #define RTC_RAR_CRR_SHIFT 4
4067 #define RTC_RAR_SRR_MASK 0x20u
4068 #define RTC_RAR_SRR_SHIFT 5
4069 #define RTC_RAR_LRR_MASK 0x40u
4070 #define RTC_RAR_LRR_SHIFT 6
4071 #define RTC_RAR_IERR_MASK 0x80u
4072 #define RTC_RAR_IERR_SHIFT 7
4073
4074 /**
4075 * @}
4076 */ /* end of group RTC_Register_Masks */
4077
4078
4079 /* RTC - Peripheral instance base addresses */
4080 /** Peripheral RTC base address */
4081 #define RTC_BASE (0x4003D000u)
4082 /** Peripheral RTC base pointer */
4083 #define RTC ((RTC_Type *)RTC_BASE)
4084
4085 /**
4086 * @}
4087 */ /* end of group RTC_Peripheral_Access_Layer */
4088
4089
4090 /* ----------------------------------------------------------------------------
4091 -- SIM Peripheral Access Layer
4092 ---------------------------------------------------------------------------- */
4093
4094 /**
4095 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
4096 * @{
4097 */
4098
4099 /** SIM - Register Layout Typedef */
4100 typedef struct {
4101 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
4102 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
4103 uint8_t RESERVED_0[4092];
4104 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
4105 uint8_t RESERVED_1[4];
4106 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
4107 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
4108 uint8_t RESERVED_2[4];
4109 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
4110 uint8_t RESERVED_3[8];
4111 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
4112 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
4113 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
4114 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
4115 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
4116 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
4117 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
4118 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
4119 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
4120 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
4121 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
4122 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
4123 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
4124 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
4125 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
4126 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
4127 } SIM_Type;
4128
4129 /* ----------------------------------------------------------------------------
4130 -- SIM Register Masks
4131 ---------------------------------------------------------------------------- */
4132
4133 /**
4134 * @addtogroup SIM_Register_Masks SIM Register Masks
4135 * @{
4136 */
4137
4138 /* SOPT1 Bit Fields */
4139 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
4140 #define SIM_SOPT1_RAMSIZE_SHIFT 12
4141 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
4142 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
4143 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
4144 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
4145 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
4146 #define SIM_SOPT1_USBVSTBY_SHIFT 29
4147 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
4148 #define SIM_SOPT1_USBSSTBY_SHIFT 30
4149 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
4150 #define SIM_SOPT1_USBREGEN_SHIFT 31
4151 /* SOPT1CFG Bit Fields */
4152 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
4153 #define SIM_SOPT1CFG_URWE_SHIFT 24
4154 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
4155 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
4156 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
4157 #define SIM_SOPT1CFG_USSWE_SHIFT 26
4158 /* SOPT2 Bit Fields */
4159 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
4160 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
4161 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
4162 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
4163 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
4164 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
4165 #define SIM_SOPT2_PTD7PAD_SHIFT 11
4166 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
4167 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
4168 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
4169 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
4170 #define SIM_SOPT2_USBSRC_MASK 0x40000u
4171 #define SIM_SOPT2_USBSRC_SHIFT 18
4172 /* SOPT4 Bit Fields */
4173 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
4174 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
4175 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
4176 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
4177 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
4178 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
4179 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
4180 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
4181 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
4182 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
4183 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
4184 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
4185 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
4186 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
4187 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
4188 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
4189 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
4190 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
4191 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
4192 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
4193 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
4194 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
4195 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
4196 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
4197 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
4198 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
4199 /* SOPT5 Bit Fields */
4200 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
4201 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
4202 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
4203 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
4204 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
4205 #define SIM_SOPT5_UART1TXSRC_MASK 0x10u
4206 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
4207 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
4208 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
4209 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
4210 /* SOPT7 Bit Fields */
4211 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
4212 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
4213 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
4214 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
4215 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
4216 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
4217 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
4218 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
4219 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
4220 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
4221 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
4222 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
4223 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
4224 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
4225 /* SDID Bit Fields */
4226 #define SIM_SDID_PINID_MASK 0xFu
4227 #define SIM_SDID_PINID_SHIFT 0
4228 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
4229 #define SIM_SDID_FAMID_MASK 0x70u
4230 #define SIM_SDID_FAMID_SHIFT 4
4231 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
4232 #define SIM_SDID_REVID_MASK 0xF000u
4233 #define SIM_SDID_REVID_SHIFT 12
4234 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
4235 /* SCGC2 Bit Fields */
4236 #define SIM_SCGC2_DAC0_MASK 0x1000u
4237 #define SIM_SCGC2_DAC0_SHIFT 12
4238 /* SCGC3 Bit Fields */
4239 #define SIM_SCGC3_FTM2_MASK 0x1000000u
4240 #define SIM_SCGC3_FTM2_SHIFT 24
4241 #define SIM_SCGC3_ADC1_MASK 0x8000000u
4242 #define SIM_SCGC3_ADC1_SHIFT 27
4243 /* SCGC4 Bit Fields */
4244 #define SIM_SCGC4_EWM_MASK 0x2u
4245 #define SIM_SCGC4_EWM_SHIFT 1
4246 #define SIM_SCGC4_CMT_MASK 0x4u
4247 #define SIM_SCGC4_CMT_SHIFT 2
4248 #define SIM_SCGC4_I2C0_MASK 0x40u
4249 #define SIM_SCGC4_I2C0_SHIFT 6
4250 #define SIM_SCGC4_I2C1_MASK 0x80u
4251 #define SIM_SCGC4_I2C1_SHIFT 7
4252 #define SIM_SCGC4_UART0_MASK 0x400u
4253 #define SIM_SCGC4_UART0_SHIFT 10
4254 #define SIM_SCGC4_UART1_MASK 0x800u
4255 #define SIM_SCGC4_UART1_SHIFT 11
4256 #define SIM_SCGC4_UART2_MASK 0x1000u
4257 #define SIM_SCGC4_UART2_SHIFT 12
4258 #define SIM_SCGC4_USBOTG_MASK 0x40000u
4259 #define SIM_SCGC4_USBOTG_SHIFT 18
4260 #define SIM_SCGC4_CMP_MASK 0x80000u
4261 #define SIM_SCGC4_CMP_SHIFT 19
4262 #define SIM_SCGC4_VREF_MASK 0x100000u
4263 #define SIM_SCGC4_VREF_SHIFT 20
4264 /* SCGC5 Bit Fields */
4265 #define SIM_SCGC5_LPTIMER_MASK 0x1u
4266 #define SIM_SCGC5_LPTIMER_SHIFT 0
4267 #define SIM_SCGC5_TSI_MASK 0x20u
4268 #define SIM_SCGC5_TSI_SHIFT 5
4269 #define SIM_SCGC5_PORTA_MASK 0x200u
4270 #define SIM_SCGC5_PORTA_SHIFT 9
4271 #define SIM_SCGC5_PORTB_MASK 0x400u
4272 #define SIM_SCGC5_PORTB_SHIFT 10
4273 #define SIM_SCGC5_PORTC_MASK 0x800u
4274 #define SIM_SCGC5_PORTC_SHIFT 11
4275 #define SIM_SCGC5_PORTD_MASK 0x1000u
4276 #define SIM_SCGC5_PORTD_SHIFT 12
4277 #define SIM_SCGC5_PORTE_MASK 0x2000u
4278 #define SIM_SCGC5_PORTE_SHIFT 13
4279 /* SCGC6 Bit Fields */
4280 #define SIM_SCGC6_FTFL_MASK 0x1u
4281 #define SIM_SCGC6_FTFL_SHIFT 0
4282 #define SIM_SCGC6_DMAMUX_MASK 0x2u
4283 #define SIM_SCGC6_DMAMUX_SHIFT 1
4284 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
4285 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
4286 #define SIM_SCGC6_SPI0_MASK 0x1000u
4287 #define SIM_SCGC6_SPI0_SHIFT 12
4288 #define SIM_SCGC6_SPI1_MASK 0x2000u
4289 #define SIM_SCGC6_SPI1_SHIFT 13
4290 #define SIM_SCGC6_I2S_MASK 0x8000u
4291 #define SIM_SCGC6_I2S_SHIFT 15
4292 #define SIM_SCGC6_CRC_MASK 0x40000u
4293 #define SIM_SCGC6_CRC_SHIFT 18
4294 #define SIM_SCGC6_USBDCD_MASK 0x200000u
4295 #define SIM_SCGC6_USBDCD_SHIFT 21
4296 #define SIM_SCGC6_PDB_MASK 0x400000u
4297 #define SIM_SCGC6_PDB_SHIFT 22
4298 #define SIM_SCGC6_PIT_MASK 0x800000u
4299 #define SIM_SCGC6_PIT_SHIFT 23
4300 #define SIM_SCGC6_FTM0_MASK 0x1000000u
4301 #define SIM_SCGC6_FTM0_SHIFT 24
4302 #define SIM_SCGC6_FTM1_MASK 0x2000000u
4303 #define SIM_SCGC6_FTM1_SHIFT 25
4304 #define SIM_SCGC6_ADC0_MASK 0x8000000u
4305 #define SIM_SCGC6_ADC0_SHIFT 27
4306 #define SIM_SCGC6_RTC_MASK 0x20000000u
4307 #define SIM_SCGC6_RTC_SHIFT 29
4308 /* SCGC7 Bit Fields */
4309 #define SIM_SCGC7_DMA_MASK 0x2u
4310 #define SIM_SCGC7_DMA_SHIFT 1
4311 /* CLKDIV1 Bit Fields */
4312 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
4313 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
4314 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
4315 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
4316 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
4317 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
4318 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
4319 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
4320 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
4321 /* CLKDIV2 Bit Fields */
4322 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
4323 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
4324 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
4325 #define SIM_CLKDIV2_USBDIV_SHIFT 1
4326 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
4327 /* FCFG1 Bit Fields */
4328 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
4329 #define SIM_FCFG1_FLASHDIS_SHIFT 0
4330 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
4331 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
4332 #define SIM_FCFG1_DEPART_MASK 0xF00u
4333 #define SIM_FCFG1_DEPART_SHIFT 8
4334 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
4335 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
4336 #define SIM_FCFG1_EESIZE_SHIFT 16
4337 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
4338 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
4339 #define SIM_FCFG1_PFSIZE_SHIFT 24
4340 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
4341 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
4342 #define SIM_FCFG1_NVMSIZE_SHIFT 28
4343 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
4344 /* FCFG2 Bit Fields */
4345 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
4346 #define SIM_FCFG2_MAXADDR1_SHIFT 16
4347 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
4348 #define SIM_FCFG2_PFLSH_MASK 0x800000u
4349 #define SIM_FCFG2_PFLSH_SHIFT 23
4350 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
4351 #define SIM_FCFG2_MAXADDR0_SHIFT 24
4352 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
4353 /* UIDH Bit Fields */
4354 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
4355 #define SIM_UIDH_UID_SHIFT 0
4356 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
4357 /* UIDMH Bit Fields */
4358 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
4359 #define SIM_UIDMH_UID_SHIFT 0
4360 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
4361 /* UIDML Bit Fields */
4362 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
4363 #define SIM_UIDML_UID_SHIFT 0
4364 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
4365 /* UIDL Bit Fields */
4366 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
4367 #define SIM_UIDL_UID_SHIFT 0
4368 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
4369
4370 /**
4371 * @}
4372 */ /* end of group SIM_Register_Masks */
4373
4374
4375 /* SIM - Peripheral instance base addresses */
4376 /** Peripheral SIM base address */
4377 #define SIM_BASE (0x40047000u)
4378 /** Peripheral SIM base pointer */
4379 #define SIM ((SIM_Type *)SIM_BASE)
4380
4381 /**
4382 * @}
4383 */ /* end of group SIM_Peripheral_Access_Layer */
4384
4385
4386 /* ----------------------------------------------------------------------------
4387 -- SMC Peripheral Access Layer
4388 ---------------------------------------------------------------------------- */
4389
4390 /**
4391 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
4392 * @{
4393 */
4394
4395 /** SMC - Register Layout Typedef */
4396 typedef struct {
4397 __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
4398 __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
4399 __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
4400 __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
4401 } SMC_Type;
4402
4403 /* ----------------------------------------------------------------------------
4404 -- SMC Register Masks
4405 ---------------------------------------------------------------------------- */
4406
4407 /**
4408 * @addtogroup SMC_Register_Masks SMC Register Masks
4409 * @{
4410 */
4411
4412 /* PMPROT Bit Fields */
4413 #define SMC_PMPROT_AVLLS_MASK 0x2u
4414 #define SMC_PMPROT_AVLLS_SHIFT 1
4415 #define SMC_PMPROT_ALLS_MASK 0x8u
4416 #define SMC_PMPROT_ALLS_SHIFT 3
4417 #define SMC_PMPROT_AVLP_MASK 0x20u
4418 #define SMC_PMPROT_AVLP_SHIFT 5
4419 /* PMCTRL Bit Fields */
4420 #define SMC_PMCTRL_STOPM_MASK 0x7u
4421 #define SMC_PMCTRL_STOPM_SHIFT 0
4422 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
4423 #define SMC_PMCTRL_STOPA_MASK 0x8u
4424 #define SMC_PMCTRL_STOPA_SHIFT 3
4425 #define SMC_PMCTRL_RUNM_MASK 0x60u
4426 #define SMC_PMCTRL_RUNM_SHIFT 5
4427 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
4428 #define SMC_PMCTRL_LPWUI_MASK 0x80u
4429 #define SMC_PMCTRL_LPWUI_SHIFT 7
4430 /* VLLSCTRL Bit Fields */
4431 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
4432 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
4433 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
4434 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
4435 #define SMC_VLLSCTRL_PORPO_SHIFT 5
4436 /* PMSTAT Bit Fields */
4437 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
4438 #define SMC_PMSTAT_PMSTAT_SHIFT 0
4439 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
4440
4441 /**
4442 * @}
4443 */ /* end of group SMC_Register_Masks */
4444
4445
4446 /* SMC - Peripheral instance base addresses */
4447 /** Peripheral SMC base address */
4448 #define SMC_BASE (0x4007E000u)
4449 /** Peripheral SMC base pointer */
4450 #define SMC ((SMC_Type *)SMC_BASE)
4451
4452 /**
4453 * @}
4454 */ /* end of group SMC_Peripheral_Access_Layer */
4455
4456
4457 /* ----------------------------------------------------------------------------
4458 -- SPI Peripheral Access Layer
4459 ---------------------------------------------------------------------------- */
4460
4461 /**
4462 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
4463 * @{
4464 */
4465
4466 /** SPI - Register Layout Typedef */
4467 typedef struct {
4468 __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
4469 uint8_t RESERVED_0[4];
4470 __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
4471 union { /* offset: 0xC */
4472 __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
4473 __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
4474 };
4475 uint8_t RESERVED_1[24];
4476 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
4477 __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
4478 union { /* offset: 0x34 */
4479 __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
4480 __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
4481 };
4482 __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
4483 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
4484 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
4485 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
4486 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
4487 uint8_t RESERVED_2[48];
4488 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
4489 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
4490 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
4491 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
4492 } SPI_Type;
4493
4494 /* ----------------------------------------------------------------------------
4495 -- SPI Register Masks
4496 ---------------------------------------------------------------------------- */
4497
4498 /**
4499 * @addtogroup SPI_Register_Masks SPI Register Masks
4500 * @{
4501 */
4502
4503 /* MCR Bit Fields */
4504 #define SPI_MCR_HALT_MASK 0x1u
4505 #define SPI_MCR_HALT_SHIFT 0
4506 #define SPI_MCR_SMPL_PT_MASK 0x300u
4507 #define SPI_MCR_SMPL_PT_SHIFT 8
4508 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
4509 #define SPI_MCR_CLR_RXF_MASK 0x400u
4510 #define SPI_MCR_CLR_RXF_SHIFT 10
4511 #define SPI_MCR_CLR_TXF_MASK 0x800u
4512 #define SPI_MCR_CLR_TXF_SHIFT 11
4513 #define SPI_MCR_DIS_RXF_MASK 0x1000u
4514 #define SPI_MCR_DIS_RXF_SHIFT 12
4515 #define SPI_MCR_DIS_TXF_MASK 0x2000u
4516 #define SPI_MCR_DIS_TXF_SHIFT 13
4517 #define SPI_MCR_MDIS_MASK 0x4000u
4518 #define SPI_MCR_MDIS_SHIFT 14
4519 #define SPI_MCR_DOZE_MASK 0x8000u
4520 #define SPI_MCR_DOZE_SHIFT 15
4521 #define SPI_MCR_PCSIS_MASK 0x3F0000u
4522 #define SPI_MCR_PCSIS_SHIFT 16
4523 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
4524 #define SPI_MCR_ROOE_MASK 0x1000000u
4525 #define SPI_MCR_ROOE_SHIFT 24
4526 #define SPI_MCR_PCSSE_MASK 0x2000000u
4527 #define SPI_MCR_PCSSE_SHIFT 25
4528 #define SPI_MCR_MTFE_MASK 0x4000000u
4529 #define SPI_MCR_MTFE_SHIFT 26
4530 #define SPI_MCR_FRZ_MASK 0x8000000u
4531 #define SPI_MCR_FRZ_SHIFT 27
4532 #define SPI_MCR_DCONF_MASK 0x30000000u
4533 #define SPI_MCR_DCONF_SHIFT 28
4534 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
4535 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
4536 #define SPI_MCR_CONT_SCKE_SHIFT 30
4537 #define SPI_MCR_MSTR_MASK 0x80000000u
4538 #define SPI_MCR_MSTR_SHIFT 31
4539 /* TCR Bit Fields */
4540 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
4541 #define SPI_TCR_SPI_TCNT_SHIFT 16
4542 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
4543 /* CTAR Bit Fields */
4544 #define SPI_CTAR_BR_MASK 0xFu
4545 #define SPI_CTAR_BR_SHIFT 0
4546 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
4547 #define SPI_CTAR_DT_MASK 0xF0u
4548 #define SPI_CTAR_DT_SHIFT 4
4549 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
4550 #define SPI_CTAR_ASC_MASK 0xF00u
4551 #define SPI_CTAR_ASC_SHIFT 8
4552 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
4553 #define SPI_CTAR_CSSCK_MASK 0xF000u
4554 #define SPI_CTAR_CSSCK_SHIFT 12
4555 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
4556 #define SPI_CTAR_PBR_MASK 0x30000u
4557 #define SPI_CTAR_PBR_SHIFT 16
4558 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
4559 #define SPI_CTAR_PDT_MASK 0xC0000u
4560 #define SPI_CTAR_PDT_SHIFT 18
4561 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
4562 #define SPI_CTAR_PASC_MASK 0x300000u
4563 #define SPI_CTAR_PASC_SHIFT 20
4564 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
4565 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
4566 #define SPI_CTAR_PCSSCK_SHIFT 22
4567 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
4568 #define SPI_CTAR_LSBFE_MASK 0x1000000u
4569 #define SPI_CTAR_LSBFE_SHIFT 24
4570 #define SPI_CTAR_CPHA_MASK 0x2000000u
4571 #define SPI_CTAR_CPHA_SHIFT 25
4572 #define SPI_CTAR_CPOL_MASK 0x4000000u
4573 #define SPI_CTAR_CPOL_SHIFT 26
4574 #define SPI_CTAR_FMSZ_MASK 0x78000000u
4575 #define SPI_CTAR_FMSZ_SHIFT 27
4576 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
4577 #define SPI_CTAR_DBR_MASK 0x80000000u
4578 #define SPI_CTAR_DBR_SHIFT 31
4579 /* CTAR_SLAVE Bit Fields */
4580 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
4581 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
4582 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
4583 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
4584 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
4585 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
4586 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
4587 /* SR Bit Fields */
4588 #define SPI_SR_POPNXTPTR_MASK 0xFu
4589 #define SPI_SR_POPNXTPTR_SHIFT 0
4590 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
4591 #define SPI_SR_RXCTR_MASK 0xF0u
4592 #define SPI_SR_RXCTR_SHIFT 4
4593 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
4594 #define SPI_SR_TXNXTPTR_MASK 0xF00u
4595 #define SPI_SR_TXNXTPTR_SHIFT 8
4596 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
4597 #define SPI_SR_TXCTR_MASK 0xF000u
4598 #define SPI_SR_TXCTR_SHIFT 12
4599 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
4600 #define SPI_SR_RFDF_MASK 0x20000u
4601 #define SPI_SR_RFDF_SHIFT 17
4602 #define SPI_SR_RFOF_MASK 0x80000u
4603 #define SPI_SR_RFOF_SHIFT 19
4604 #define SPI_SR_TFFF_MASK 0x2000000u
4605 #define SPI_SR_TFFF_SHIFT 25
4606 #define SPI_SR_TFUF_MASK 0x8000000u
4607 #define SPI_SR_TFUF_SHIFT 27
4608 #define SPI_SR_EOQF_MASK 0x10000000u
4609 #define SPI_SR_EOQF_SHIFT 28
4610 #define SPI_SR_TXRXS_MASK 0x40000000u
4611 #define SPI_SR_TXRXS_SHIFT 30
4612 #define SPI_SR_TCF_MASK 0x80000000u
4613 #define SPI_SR_TCF_SHIFT 31
4614 /* RSER Bit Fields */
4615 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
4616 #define SPI_RSER_RFDF_DIRS_SHIFT 16
4617 #define SPI_RSER_RFDF_RE_MASK 0x20000u
4618 #define SPI_RSER_RFDF_RE_SHIFT 17
4619 #define SPI_RSER_RFOF_RE_MASK 0x80000u
4620 #define SPI_RSER_RFOF_RE_SHIFT 19
4621 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
4622 #define SPI_RSER_TFFF_DIRS_SHIFT 24
4623 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
4624 #define SPI_RSER_TFFF_RE_SHIFT 25
4625 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
4626 #define SPI_RSER_TFUF_RE_SHIFT 27
4627 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
4628 #define SPI_RSER_EOQF_RE_SHIFT 28
4629 #define SPI_RSER_TCF_RE_MASK 0x80000000u
4630 #define SPI_RSER_TCF_RE_SHIFT 31
4631 /* PUSHR Bit Fields */
4632 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
4633 #define SPI_PUSHR_TXDATA_SHIFT 0
4634 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
4635 #define SPI_PUSHR_PCS_MASK 0x3F0000u
4636 #define SPI_PUSHR_PCS_SHIFT 16
4637 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
4638 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
4639 #define SPI_PUSHR_CTCNT_SHIFT 26
4640 #define SPI_PUSHR_EOQ_MASK 0x8000000u
4641 #define SPI_PUSHR_EOQ_SHIFT 27
4642 #define SPI_PUSHR_CTAS_MASK 0x70000000u
4643 #define SPI_PUSHR_CTAS_SHIFT 28
4644 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
4645 #define SPI_PUSHR_CONT_MASK 0x80000000u
4646 #define SPI_PUSHR_CONT_SHIFT 31
4647 /* PUSHR_SLAVE Bit Fields */
4648 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
4649 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
4650 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
4651 /* POPR Bit Fields */
4652 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
4653 #define SPI_POPR_RXDATA_SHIFT 0
4654 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
4655 /* TXFR0 Bit Fields */
4656 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
4657 #define SPI_TXFR0_TXDATA_SHIFT 0
4658 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
4659 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
4660 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
4661 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
4662 /* TXFR1 Bit Fields */
4663 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
4664 #define SPI_TXFR1_TXDATA_SHIFT 0
4665 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
4666 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
4667 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
4668 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
4669 /* TXFR2 Bit Fields */
4670 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
4671 #define SPI_TXFR2_TXDATA_SHIFT 0
4672 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
4673 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
4674 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
4675 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
4676 /* TXFR3 Bit Fields */
4677 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
4678 #define SPI_TXFR3_TXDATA_SHIFT 0
4679 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
4680 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
4681 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
4682 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
4683 /* RXFR0 Bit Fields */
4684 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
4685 #define SPI_RXFR0_RXDATA_SHIFT 0
4686 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
4687 /* RXFR1 Bit Fields */
4688 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
4689 #define SPI_RXFR1_RXDATA_SHIFT 0
4690 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
4691 /* RXFR2 Bit Fields */
4692 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
4693 #define SPI_RXFR2_RXDATA_SHIFT 0
4694 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
4695 /* RXFR3 Bit Fields */
4696 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
4697 #define SPI_RXFR3_RXDATA_SHIFT 0
4698 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
4699
4700 /**
4701 * @}
4702 */ /* end of group SPI_Register_Masks */
4703
4704
4705 /* SPI - Peripheral instance base addresses */
4706 /** Peripheral SPI0 base address */
4707 #define SPI0_BASE (0x4002C000u)
4708 /** Peripheral SPI0 base pointer */
4709 #define SPI0 ((SPI_Type *)SPI0_BASE)
4710
4711 /**
4712 * @}
4713 */ /* end of group SPI_Peripheral_Access_Layer */
4714
4715
4716 /* ----------------------------------------------------------------------------
4717 -- TSI Peripheral Access Layer
4718 ---------------------------------------------------------------------------- */
4719
4720 /**
4721 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
4722 * @{
4723 */
4724
4725 /** TSI - Register Layout Typedef */
4726 typedef struct {
4727 __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
4728 __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
4729 __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
4730 __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
4731 uint8_t RESERVED_0[240];
4732 __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
4733 __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
4734 __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
4735 __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
4736 __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
4737 __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
4738 __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
4739 __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
4740 __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
4741 } TSI_Type;
4742
4743 /* ----------------------------------------------------------------------------
4744 -- TSI Register Masks
4745 ---------------------------------------------------------------------------- */
4746
4747 /**
4748 * @addtogroup TSI_Register_Masks TSI Register Masks
4749 * @{
4750 */
4751
4752 /* GENCS Bit Fields */
4753 #define TSI_GENCS_STPE_MASK 0x1u
4754 #define TSI_GENCS_STPE_SHIFT 0
4755 #define TSI_GENCS_STM_MASK 0x2u
4756 #define TSI_GENCS_STM_SHIFT 1
4757 #define TSI_GENCS_ESOR_MASK 0x10u
4758 #define TSI_GENCS_ESOR_SHIFT 4
4759 #define TSI_GENCS_ERIE_MASK 0x20u
4760 #define TSI_GENCS_ERIE_SHIFT 5
4761 #define TSI_GENCS_TSIIE_MASK 0x40u
4762 #define TSI_GENCS_TSIIE_SHIFT 6
4763 #define TSI_GENCS_TSIEN_MASK 0x80u
4764 #define TSI_GENCS_TSIEN_SHIFT 7
4765 #define TSI_GENCS_SWTS_MASK 0x100u
4766 #define TSI_GENCS_SWTS_SHIFT 8
4767 #define TSI_GENCS_SCNIP_MASK 0x200u
4768 #define TSI_GENCS_SCNIP_SHIFT 9
4769 #define TSI_GENCS_OVRF_MASK 0x1000u
4770 #define TSI_GENCS_OVRF_SHIFT 12
4771 #define TSI_GENCS_EXTERF_MASK 0x2000u
4772 #define TSI_GENCS_EXTERF_SHIFT 13
4773 #define TSI_GENCS_OUTRGF_MASK 0x4000u
4774 #define TSI_GENCS_OUTRGF_SHIFT 14
4775 #define TSI_GENCS_EOSF_MASK 0x8000u
4776 #define TSI_GENCS_EOSF_SHIFT 15
4777 #define TSI_GENCS_PS_MASK 0x70000u
4778 #define TSI_GENCS_PS_SHIFT 16
4779 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
4780 #define TSI_GENCS_NSCN_MASK 0xF80000u
4781 #define TSI_GENCS_NSCN_SHIFT 19
4782 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
4783 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
4784 #define TSI_GENCS_LPSCNITV_SHIFT 24
4785 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
4786 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
4787 #define TSI_GENCS_LPCLKS_SHIFT 28
4788 /* SCANC Bit Fields */
4789 #define TSI_SCANC_AMPSC_MASK 0x7u
4790 #define TSI_SCANC_AMPSC_SHIFT 0
4791 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
4792 #define TSI_SCANC_AMCLKS_MASK 0x18u
4793 #define TSI_SCANC_AMCLKS_SHIFT 3
4794 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
4795 #define TSI_SCANC_SMOD_MASK 0xFF00u
4796 #define TSI_SCANC_SMOD_SHIFT 8
4797 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
4798 #define TSI_SCANC_EXTCHRG_MASK 0xF0000u
4799 #define TSI_SCANC_EXTCHRG_SHIFT 16
4800 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
4801 #define TSI_SCANC_REFCHRG_MASK 0xF000000u
4802 #define TSI_SCANC_REFCHRG_SHIFT 24
4803 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
4804 /* PEN Bit Fields */
4805 #define TSI_PEN_PEN0_MASK 0x1u
4806 #define TSI_PEN_PEN0_SHIFT 0
4807 #define TSI_PEN_PEN1_MASK 0x2u
4808 #define TSI_PEN_PEN1_SHIFT 1
4809 #define TSI_PEN_PEN2_MASK 0x4u
4810 #define TSI_PEN_PEN2_SHIFT 2
4811 #define TSI_PEN_PEN3_MASK 0x8u
4812 #define TSI_PEN_PEN3_SHIFT 3
4813 #define TSI_PEN_PEN4_MASK 0x10u
4814 #define TSI_PEN_PEN4_SHIFT 4
4815 #define TSI_PEN_PEN5_MASK 0x20u
4816 #define TSI_PEN_PEN5_SHIFT 5
4817 #define TSI_PEN_PEN6_MASK 0x40u
4818 #define TSI_PEN_PEN6_SHIFT 6
4819 #define TSI_PEN_PEN7_MASK 0x80u
4820 #define TSI_PEN_PEN7_SHIFT 7
4821 #define TSI_PEN_PEN8_MASK 0x100u
4822 #define TSI_PEN_PEN8_SHIFT 8
4823 #define TSI_PEN_PEN9_MASK 0x200u
4824 #define TSI_PEN_PEN9_SHIFT 9
4825 #define TSI_PEN_PEN10_MASK 0x400u
4826 #define TSI_PEN_PEN10_SHIFT 10
4827 #define TSI_PEN_PEN11_MASK 0x800u
4828 #define TSI_PEN_PEN11_SHIFT 11
4829 #define TSI_PEN_PEN12_MASK 0x1000u
4830 #define TSI_PEN_PEN12_SHIFT 12
4831 #define TSI_PEN_PEN13_MASK 0x2000u
4832 #define TSI_PEN_PEN13_SHIFT 13
4833 #define TSI_PEN_PEN14_MASK 0x4000u
4834 #define TSI_PEN_PEN14_SHIFT 14
4835 #define TSI_PEN_PEN15_MASK 0x8000u
4836 #define TSI_PEN_PEN15_SHIFT 15
4837 #define TSI_PEN_LPSP_MASK 0xF0000u
4838 #define TSI_PEN_LPSP_SHIFT 16
4839 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
4840 /* WUCNTR Bit Fields */
4841 #define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
4842 #define TSI_WUCNTR_WUCNT_SHIFT 0
4843 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
4844 /* CNTR1 Bit Fields */
4845 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
4846 #define TSI_CNTR1_CTN1_SHIFT 0
4847 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
4848 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
4849 #define TSI_CNTR1_CTN_SHIFT 16
4850 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
4851 /* CNTR3 Bit Fields */
4852 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
4853 #define TSI_CNTR3_CTN1_SHIFT 0
4854 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
4855 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
4856 #define TSI_CNTR3_CTN_SHIFT 16
4857 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
4858 /* CNTR5 Bit Fields */
4859 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
4860 #define TSI_CNTR5_CTN1_SHIFT 0
4861 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
4862 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
4863 #define TSI_CNTR5_CTN_SHIFT 16
4864 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
4865 /* CNTR7 Bit Fields */
4866 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
4867 #define TSI_CNTR7_CTN1_SHIFT 0
4868 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
4869 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
4870 #define TSI_CNTR7_CTN_SHIFT 16
4871 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
4872 /* CNTR9 Bit Fields */
4873 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
4874 #define TSI_CNTR9_CTN1_SHIFT 0
4875 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
4876 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
4877 #define TSI_CNTR9_CTN_SHIFT 16
4878 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
4879 /* CNTR11 Bit Fields */
4880 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
4881 #define TSI_CNTR11_CTN1_SHIFT 0
4882 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
4883 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
4884 #define TSI_CNTR11_CTN_SHIFT 16
4885 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
4886 /* CNTR13 Bit Fields */
4887 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
4888 #define TSI_CNTR13_CTN1_SHIFT 0
4889 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
4890 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
4891 #define TSI_CNTR13_CTN_SHIFT 16
4892 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
4893 /* CNTR15 Bit Fields */
4894 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
4895 #define TSI_CNTR15_CTN1_SHIFT 0
4896 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
4897 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
4898 #define TSI_CNTR15_CTN_SHIFT 16
4899 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
4900 /* THRESHOLD Bit Fields */
4901 #define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
4902 #define TSI_THRESHOLD_HTHH_SHIFT 0
4903 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
4904 #define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
4905 #define TSI_THRESHOLD_LTHH_SHIFT 16
4906 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
4907
4908 /**
4909 * @}
4910 */ /* end of group TSI_Register_Masks */
4911
4912
4913 /* TSI - Peripheral instance base addresses */
4914 /** Peripheral TSI0 base address */
4915 #define TSI0_BASE (0x40045000u)
4916 /** Peripheral TSI0 base pointer */
4917 #define TSI0 ((TSI_Type *)TSI0_BASE)
4918
4919 /**
4920 * @}
4921 */ /* end of group TSI_Peripheral_Access_Layer */
4922
4923
4924 /* ----------------------------------------------------------------------------
4925 -- UART Peripheral Access Layer
4926 ---------------------------------------------------------------------------- */
4927
4928 /**
4929 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
4930 * @{
4931 */
4932
4933 /** UART - Register Layout Typedef */
4934 typedef struct {
4935 __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
4936 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
4937 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
4938 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
4939 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
4940 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
4941 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
4942 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
4943 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
4944 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
4945 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
4946 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
4947 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
4948 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
4949 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
4950 uint8_t RESERVED_0[1];
4951 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
4952 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
4953 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
4954 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
4955 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
4956 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
4957 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
4958 uint8_t RESERVED_1[1];
4959 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
4960 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
4961 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
4962 union { /* offset: 0x1B */
4963 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
4964 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
4965 };
4966 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
4967 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
4968 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
4969 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
4970 uint8_t RESERVED_2[1];
4971 __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
4972 __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
4973 __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
4974 __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
4975 __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
4976 __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
4977 __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
4978 __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
4979 __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
4980 __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
4981 __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
4982 __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
4983 __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
4984 __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
4985 __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
4986 __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
4987 __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
4988 } UART_Type;
4989
4990 /* ----------------------------------------------------------------------------
4991 -- UART Register Masks
4992 ---------------------------------------------------------------------------- */
4993
4994 /**
4995 * @addtogroup UART_Register_Masks UART Register Masks
4996 * @{
4997 */
4998
4999 /* BDH Bit Fields */
5000 #define UART_BDH_SBR_MASK 0x1Fu
5001 #define UART_BDH_SBR_SHIFT 0
5002 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
5003 #define UART_BDH_RXEDGIE_MASK 0x40u
5004 #define UART_BDH_RXEDGIE_SHIFT 6
5005 #define UART_BDH_LBKDIE_MASK 0x80u
5006 #define UART_BDH_LBKDIE_SHIFT 7
5007 /* BDL Bit Fields */
5008 #define UART_BDL_SBR_MASK 0xFFu
5009 #define UART_BDL_SBR_SHIFT 0
5010 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
5011 /* C1 Bit Fields */
5012 #define UART_C1_PT_MASK 0x1u
5013 #define UART_C1_PT_SHIFT 0
5014 #define UART_C1_PE_MASK 0x2u
5015 #define UART_C1_PE_SHIFT 1
5016 #define UART_C1_ILT_MASK 0x4u
5017 #define UART_C1_ILT_SHIFT 2
5018 #define UART_C1_WAKE_MASK 0x8u
5019 #define UART_C1_WAKE_SHIFT 3
5020 #define UART_C1_M_MASK 0x10u
5021 #define UART_C1_M_SHIFT 4
5022 #define UART_C1_RSRC_MASK 0x20u
5023 #define UART_C1_RSRC_SHIFT 5
5024 #define UART_C1_UARTSWAI_MASK 0x40u
5025 #define UART_C1_UARTSWAI_SHIFT 6
5026 #define UART_C1_LOOPS_MASK 0x80u
5027 #define UART_C1_LOOPS_SHIFT 7
5028 /* C2 Bit Fields */
5029 #define UART_C2_SBK_MASK 0x1u
5030 #define UART_C2_SBK_SHIFT 0
5031 #define UART_C2_RWU_MASK 0x2u
5032 #define UART_C2_RWU_SHIFT 1
5033 #define UART_C2_RE_MASK 0x4u
5034 #define UART_C2_RE_SHIFT 2
5035 #define UART_C2_TE_MASK 0x8u
5036 #define UART_C2_TE_SHIFT 3
5037 #define UART_C2_ILIE_MASK 0x10u
5038 #define UART_C2_ILIE_SHIFT 4
5039 #define UART_C2_RIE_MASK 0x20u
5040 #define UART_C2_RIE_SHIFT 5
5041 #define UART_C2_TCIE_MASK 0x40u
5042 #define UART_C2_TCIE_SHIFT 6
5043 #define UART_C2_TIE_MASK 0x80u
5044 #define UART_C2_TIE_SHIFT 7
5045 /* S1 Bit Fields */
5046 #define UART_S1_PF_MASK 0x1u
5047 #define UART_S1_PF_SHIFT 0
5048 #define UART_S1_FE_MASK 0x2u
5049 #define UART_S1_FE_SHIFT 1
5050 #define UART_S1_NF_MASK 0x4u
5051 #define UART_S1_NF_SHIFT 2
5052 #define UART_S1_OR_MASK 0x8u
5053 #define UART_S1_OR_SHIFT 3
5054 #define UART_S1_IDLE_MASK 0x10u
5055 #define UART_S1_IDLE_SHIFT 4
5056 #define UART_S1_RDRF_MASK 0x20u
5057 #define UART_S1_RDRF_SHIFT 5
5058 #define UART_S1_TC_MASK 0x40u
5059 #define UART_S1_TC_SHIFT 6
5060 #define UART_S1_TDRE_MASK 0x80u
5061 #define UART_S1_TDRE_SHIFT 7
5062 /* S2 Bit Fields */
5063 #define UART_S2_RAF_MASK 0x1u
5064 #define UART_S2_RAF_SHIFT 0
5065 #define UART_S2_LBKDE_MASK 0x2u
5066 #define UART_S2_LBKDE_SHIFT 1
5067 #define UART_S2_BRK13_MASK 0x4u
5068 #define UART_S2_BRK13_SHIFT 2
5069 #define UART_S2_RWUID_MASK 0x8u
5070 #define UART_S2_RWUID_SHIFT 3
5071 #define UART_S2_RXINV_MASK 0x10u
5072 #define UART_S2_RXINV_SHIFT 4
5073 #define UART_S2_MSBF_MASK 0x20u
5074 #define UART_S2_MSBF_SHIFT 5
5075 #define UART_S2_RXEDGIF_MASK 0x40u
5076 #define UART_S2_RXEDGIF_SHIFT 6
5077 #define UART_S2_LBKDIF_MASK 0x80u
5078 #define UART_S2_LBKDIF_SHIFT 7
5079 /* C3 Bit Fields */
5080 #define UART_C3_PEIE_MASK 0x1u
5081 #define UART_C3_PEIE_SHIFT 0
5082 #define UART_C3_FEIE_MASK 0x2u
5083 #define UART_C3_FEIE_SHIFT 1
5084 #define UART_C3_NEIE_MASK 0x4u
5085 #define UART_C3_NEIE_SHIFT 2
5086 #define UART_C3_ORIE_MASK 0x8u
5087 #define UART_C3_ORIE_SHIFT 3
5088 #define UART_C3_TXINV_MASK 0x10u
5089 #define UART_C3_TXINV_SHIFT 4
5090 #define UART_C3_TXDIR_MASK 0x20u
5091 #define UART_C3_TXDIR_SHIFT 5
5092 #define UART_C3_T8_MASK 0x40u
5093 #define UART_C3_T8_SHIFT 6
5094 #define UART_C3_R8_MASK 0x80u
5095 #define UART_C3_R8_SHIFT 7
5096 /* D Bit Fields */
5097 #define UART_D_RT_MASK 0xFFu
5098 #define UART_D_RT_SHIFT 0
5099 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
5100 /* MA1 Bit Fields */
5101 #define UART_MA1_MA_MASK 0xFFu
5102 #define UART_MA1_MA_SHIFT 0
5103 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
5104 /* MA2 Bit Fields */
5105 #define UART_MA2_MA_MASK 0xFFu
5106 #define UART_MA2_MA_SHIFT 0
5107 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
5108 /* C4 Bit Fields */
5109 #define UART_C4_BRFA_MASK 0x1Fu
5110 #define UART_C4_BRFA_SHIFT 0
5111 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
5112 #define UART_C4_M10_MASK 0x20u
5113 #define UART_C4_M10_SHIFT 5
5114 #define UART_C4_MAEN2_MASK 0x40u
5115 #define UART_C4_MAEN2_SHIFT 6
5116 #define UART_C4_MAEN1_MASK 0x80u
5117 #define UART_C4_MAEN1_SHIFT 7
5118 /* C5 Bit Fields */
5119 #define UART_C5_RDMAS_MASK 0x20u
5120 #define UART_C5_RDMAS_SHIFT 5
5121 #define UART_C5_TDMAS_MASK 0x80u
5122 #define UART_C5_TDMAS_SHIFT 7
5123 /* ED Bit Fields */
5124 #define UART_ED_PARITYE_MASK 0x40u
5125 #define UART_ED_PARITYE_SHIFT 6
5126 #define UART_ED_NOISY_MASK 0x80u
5127 #define UART_ED_NOISY_SHIFT 7
5128 /* MODEM Bit Fields */
5129 #define UART_MODEM_TXCTSE_MASK 0x1u
5130 #define UART_MODEM_TXCTSE_SHIFT 0
5131 #define UART_MODEM_TXRTSE_MASK 0x2u
5132 #define UART_MODEM_TXRTSE_SHIFT 1
5133 #define UART_MODEM_TXRTSPOL_MASK 0x4u
5134 #define UART_MODEM_TXRTSPOL_SHIFT 2
5135 #define UART_MODEM_RXRTSE_MASK 0x8u
5136 #define UART_MODEM_RXRTSE_SHIFT 3
5137 /* IR Bit Fields */
5138 #define UART_IR_TNP_MASK 0x3u
5139 #define UART_IR_TNP_SHIFT 0
5140 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
5141 #define UART_IR_IREN_MASK 0x4u
5142 #define UART_IR_IREN_SHIFT 2
5143 /* PFIFO Bit Fields */
5144 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
5145 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
5146 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
5147 #define UART_PFIFO_RXFE_MASK 0x8u
5148 #define UART_PFIFO_RXFE_SHIFT 3
5149 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
5150 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
5151 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
5152 #define UART_PFIFO_TXFE_MASK 0x80u
5153 #define UART_PFIFO_TXFE_SHIFT 7
5154 /* CFIFO Bit Fields */
5155 #define UART_CFIFO_RXUFE_MASK 0x1u
5156 #define UART_CFIFO_RXUFE_SHIFT 0
5157 #define UART_CFIFO_TXOFE_MASK 0x2u
5158 #define UART_CFIFO_TXOFE_SHIFT 1
5159 #define UART_CFIFO_RXFLUSH_MASK 0x40u
5160 #define UART_CFIFO_RXFLUSH_SHIFT 6
5161 #define UART_CFIFO_TXFLUSH_MASK 0x80u
5162 #define UART_CFIFO_TXFLUSH_SHIFT 7
5163 /* SFIFO Bit Fields */
5164 #define UART_SFIFO_RXUF_MASK 0x1u
5165 #define UART_SFIFO_RXUF_SHIFT 0
5166 #define UART_SFIFO_TXOF_MASK 0x2u
5167 #define UART_SFIFO_TXOF_SHIFT 1
5168 #define UART_SFIFO_RXEMPT_MASK 0x40u
5169 #define UART_SFIFO_RXEMPT_SHIFT 6
5170 #define UART_SFIFO_TXEMPT_MASK 0x80u
5171 #define UART_SFIFO_TXEMPT_SHIFT 7
5172 /* TWFIFO Bit Fields */
5173 #define UART_TWFIFO_TXWATER_MASK 0xFFu
5174 #define UART_TWFIFO_TXWATER_SHIFT 0
5175 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
5176 /* TCFIFO Bit Fields */
5177 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
5178 #define UART_TCFIFO_TXCOUNT_SHIFT 0
5179 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
5180 /* RWFIFO Bit Fields */
5181 #define UART_RWFIFO_RXWATER_MASK 0xFFu
5182 #define UART_RWFIFO_RXWATER_SHIFT 0
5183 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
5184 /* RCFIFO Bit Fields */
5185 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
5186 #define UART_RCFIFO_RXCOUNT_SHIFT 0
5187 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
5188 /* C7816 Bit Fields */
5189 #define UART_C7816_ISO_7816E_MASK 0x1u
5190 #define UART_C7816_ISO_7816E_SHIFT 0
5191 #define UART_C7816_TTYPE_MASK 0x2u
5192 #define UART_C7816_TTYPE_SHIFT 1
5193 #define UART_C7816_INIT_MASK 0x4u
5194 #define UART_C7816_INIT_SHIFT 2
5195 #define UART_C7816_ANACK_MASK 0x8u
5196 #define UART_C7816_ANACK_SHIFT 3
5197 #define UART_C7816_ONACK_MASK 0x10u
5198 #define UART_C7816_ONACK_SHIFT 4
5199 /* IE7816 Bit Fields */
5200 #define UART_IE7816_RXTE_MASK 0x1u
5201 #define UART_IE7816_RXTE_SHIFT 0
5202 #define UART_IE7816_TXTE_MASK 0x2u
5203 #define UART_IE7816_TXTE_SHIFT 1
5204 #define UART_IE7816_GTVE_MASK 0x4u
5205 #define UART_IE7816_GTVE_SHIFT 2
5206 #define UART_IE7816_INITDE_MASK 0x10u
5207 #define UART_IE7816_INITDE_SHIFT 4
5208 #define UART_IE7816_BWTE_MASK 0x20u
5209 #define UART_IE7816_BWTE_SHIFT 5
5210 #define UART_IE7816_CWTE_MASK 0x40u
5211 #define UART_IE7816_CWTE_SHIFT 6
5212 #define UART_IE7816_WTE_MASK 0x80u
5213 #define UART_IE7816_WTE_SHIFT 7
5214 /* IS7816 Bit Fields */
5215 #define UART_IS7816_RXT_MASK 0x1u
5216 #define UART_IS7816_RXT_SHIFT 0
5217 #define UART_IS7816_TXT_MASK 0x2u
5218 #define UART_IS7816_TXT_SHIFT 1
5219 #define UART_IS7816_GTV_MASK 0x4u
5220 #define UART_IS7816_GTV_SHIFT 2
5221 #define UART_IS7816_INITD_MASK 0x10u
5222 #define UART_IS7816_INITD_SHIFT 4
5223 #define UART_IS7816_BWT_MASK 0x20u
5224 #define UART_IS7816_BWT_SHIFT 5
5225 #define UART_IS7816_CWT_MASK 0x40u
5226 #define UART_IS7816_CWT_SHIFT 6
5227 #define UART_IS7816_WT_MASK 0x80u
5228 #define UART_IS7816_WT_SHIFT 7
5229 /* WP7816_T_TYPE0 Bit Fields */
5230 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
5231 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
5232 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
5233 /* WP7816_T_TYPE1 Bit Fields */
5234 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
5235 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
5236 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
5237 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
5238 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
5239 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
5240 /* WN7816 Bit Fields */
5241 #define UART_WN7816_GTN_MASK 0xFFu
5242 #define UART_WN7816_GTN_SHIFT 0
5243 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
5244 /* WF7816 Bit Fields */
5245 #define UART_WF7816_GTFD_MASK 0xFFu
5246 #define UART_WF7816_GTFD_SHIFT 0
5247 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
5248 /* ET7816 Bit Fields */
5249 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
5250 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
5251 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
5252 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
5253 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
5254 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
5255 /* TL7816 Bit Fields */
5256 #define UART_TL7816_TLEN_MASK 0xFFu
5257 #define UART_TL7816_TLEN_SHIFT 0
5258 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
5259 /* C6 Bit Fields */
5260 #define UART_C6_CP_MASK 0x10u
5261 #define UART_C6_CP_SHIFT 4
5262 #define UART_C6_CE_MASK 0x20u
5263 #define UART_C6_CE_SHIFT 5
5264 #define UART_C6_TX709_MASK 0x40u
5265 #define UART_C6_TX709_SHIFT 6
5266 #define UART_C6_EN709_MASK 0x80u
5267 #define UART_C6_EN709_SHIFT 7
5268 /* PCTH Bit Fields */
5269 #define UART_PCTH_PCTH_MASK 0xFFu
5270 #define UART_PCTH_PCTH_SHIFT 0
5271 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
5272 /* PCTL Bit Fields */
5273 #define UART_PCTL_PCTL_MASK 0xFFu
5274 #define UART_PCTL_PCTL_SHIFT 0
5275 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
5276 /* B1T Bit Fields */
5277 #define UART_B1T_B1T_MASK 0xFFu
5278 #define UART_B1T_B1T_SHIFT 0
5279 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
5280 /* SDTH Bit Fields */
5281 #define UART_SDTH_SDTH_MASK 0xFFu
5282 #define UART_SDTH_SDTH_SHIFT 0
5283 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
5284 /* SDTL Bit Fields */
5285 #define UART_SDTL_SDTL_MASK 0xFFu
5286 #define UART_SDTL_SDTL_SHIFT 0
5287 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
5288 /* PRE Bit Fields */
5289 #define UART_PRE_PREAMBLE_MASK 0xFFu
5290 #define UART_PRE_PREAMBLE_SHIFT 0
5291 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
5292 /* TPL Bit Fields */
5293 #define UART_TPL_TPL_MASK 0xFFu
5294 #define UART_TPL_TPL_SHIFT 0
5295 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
5296 /* IE Bit Fields */
5297 #define UART_IE_TXFIE_MASK 0x1u
5298 #define UART_IE_TXFIE_SHIFT 0
5299 #define UART_IE_PSIE_MASK 0x2u
5300 #define UART_IE_PSIE_SHIFT 1
5301 #define UART_IE_PCTEIE_MASK 0x4u
5302 #define UART_IE_PCTEIE_SHIFT 2
5303 #define UART_IE_PTXIE_MASK 0x8u
5304 #define UART_IE_PTXIE_SHIFT 3
5305 #define UART_IE_PRXIE_MASK 0x10u
5306 #define UART_IE_PRXIE_SHIFT 4
5307 #define UART_IE_ISDIE_MASK 0x20u
5308 #define UART_IE_ISDIE_SHIFT 5
5309 #define UART_IE_WBEIE_MASK 0x40u
5310 #define UART_IE_WBEIE_SHIFT 6
5311 /* WB Bit Fields */
5312 #define UART_WB_WBASE_MASK 0xFFu
5313 #define UART_WB_WBASE_SHIFT 0
5314 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
5315 /* S3 Bit Fields */
5316 #define UART_S3_TXFF_MASK 0x1u
5317 #define UART_S3_TXFF_SHIFT 0
5318 #define UART_S3_PSF_MASK 0x2u
5319 #define UART_S3_PSF_SHIFT 1
5320 #define UART_S3_PCTEF_MASK 0x4u
5321 #define UART_S3_PCTEF_SHIFT 2
5322 #define UART_S3_PTXF_MASK 0x8u
5323 #define UART_S3_PTXF_SHIFT 3
5324 #define UART_S3_PRXF_MASK 0x10u
5325 #define UART_S3_PRXF_SHIFT 4
5326 #define UART_S3_ISD_MASK 0x20u
5327 #define UART_S3_ISD_SHIFT 5
5328 #define UART_S3_WBEF_MASK 0x40u
5329 #define UART_S3_WBEF_SHIFT 6
5330 #define UART_S3_PEF_MASK 0x80u
5331 #define UART_S3_PEF_SHIFT 7
5332 /* S4 Bit Fields */
5333 #define UART_S4_FE_MASK 0x1u
5334 #define UART_S4_FE_SHIFT 0
5335 #define UART_S4_ILCV_MASK 0x2u
5336 #define UART_S4_ILCV_SHIFT 1
5337 #define UART_S4_CDET_MASK 0xCu
5338 #define UART_S4_CDET_SHIFT 2
5339 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
5340 #define UART_S4_INITF_MASK 0x10u
5341 #define UART_S4_INITF_SHIFT 4
5342 /* RPL Bit Fields */
5343 #define UART_RPL_RPL_MASK 0xFFu
5344 #define UART_RPL_RPL_SHIFT 0
5345 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
5346 /* RPREL Bit Fields */
5347 #define UART_RPREL_RPREL_MASK 0xFFu
5348 #define UART_RPREL_RPREL_SHIFT 0
5349 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
5350 /* CPW Bit Fields */
5351 #define UART_CPW_CPW_MASK 0xFFu
5352 #define UART_CPW_CPW_SHIFT 0
5353 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
5354 /* RIDT Bit Fields */
5355 #define UART_RIDT_RIDT_MASK 0xFFu
5356 #define UART_RIDT_RIDT_SHIFT 0
5357 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
5358 /* TIDT Bit Fields */
5359 #define UART_TIDT_TIDT_MASK 0xFFu
5360 #define UART_TIDT_TIDT_SHIFT 0
5361 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
5362
5363 /**
5364 * @}
5365 */ /* end of group UART_Register_Masks */
5366
5367
5368 /* UART - Peripheral instance base addresses */
5369 /** Peripheral UART0 base address */
5370 #define UART0_BASE (0x4006A000u)
5371 /** Peripheral UART0 base pointer */
5372 #define UART0 ((UART_Type *)UART0_BASE)
5373 /** Peripheral UART1 base address */
5374 #define UART1_BASE (0x4006B000u)
5375 /** Peripheral UART1 base pointer */
5376 #define UART1 ((UART_Type *)UART1_BASE)
5377 /** Peripheral UART2 base address */
5378 #define UART2_BASE (0x4006C000u)
5379 /** Peripheral UART2 base pointer */
5380 #define UART2 ((UART_Type *)UART2_BASE)
5381
5382 /**
5383 * @}
5384 */ /* end of group UART_Peripheral_Access_Layer */
5385
5386
5387 /* ----------------------------------------------------------------------------
5388 -- USB Peripheral Access Layer
5389 ---------------------------------------------------------------------------- */
5390
5391 /**
5392 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
5393 * @{
5394 */
5395
5396 /** USB - Register Layout Typedef */
5397 typedef struct {
5398 __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
5399 uint8_t RESERVED_0[3];
5400 __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
5401 uint8_t RESERVED_1[3];
5402 __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
5403 uint8_t RESERVED_2[3];
5404 __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
5405 uint8_t RESERVED_3[3];
5406 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
5407 uint8_t RESERVED_4[3];
5408 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
5409 uint8_t RESERVED_5[3];
5410 __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
5411 uint8_t RESERVED_6[3];
5412 __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
5413 uint8_t RESERVED_7[99];
5414 __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
5415 uint8_t RESERVED_8[3];
5416 __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
5417 uint8_t RESERVED_9[3];
5418 __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
5419 uint8_t RESERVED_10[3];
5420 __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
5421 uint8_t RESERVED_11[3];
5422 __I uint8_t STAT; /**< Status Register, offset: 0x90 */
5423 uint8_t RESERVED_12[3];
5424 __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
5425 uint8_t RESERVED_13[3];
5426 __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
5427 uint8_t RESERVED_14[3];
5428 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
5429 uint8_t RESERVED_15[3];
5430 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
5431 uint8_t RESERVED_16[3];
5432 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
5433 uint8_t RESERVED_17[3];
5434 __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
5435 uint8_t RESERVED_18[3];
5436 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
5437 uint8_t RESERVED_19[3];
5438 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
5439 uint8_t RESERVED_20[3];
5440 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
5441 uint8_t RESERVED_21[11];
5442 struct { /* offset: 0xC0, array step: 0x4 */
5443 __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
5444 uint8_t RESERVED_0[3];
5445 } ENDPOINT[16];
5446 __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
5447 uint8_t RESERVED_22[3];
5448 __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
5449 uint8_t RESERVED_23[3];
5450 __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
5451 uint8_t RESERVED_24[3];
5452 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
5453 uint8_t RESERVED_25[7];
5454 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
5455 } USB_Type;
5456
5457 /* ----------------------------------------------------------------------------
5458 -- USB Register Masks
5459 ---------------------------------------------------------------------------- */
5460
5461 /**
5462 * @addtogroup USB_Register_Masks USB Register Masks
5463 * @{
5464 */
5465
5466 /* PERID Bit Fields */
5467 #define USB_PERID_ID_MASK 0x3Fu
5468 #define USB_PERID_ID_SHIFT 0
5469 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
5470 /* IDCOMP Bit Fields */
5471 #define USB_IDCOMP_NID_MASK 0x3Fu
5472 #define USB_IDCOMP_NID_SHIFT 0
5473 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
5474 /* REV Bit Fields */
5475 #define USB_REV_REV_MASK 0xFFu
5476 #define USB_REV_REV_SHIFT 0
5477 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
5478 /* ADDINFO Bit Fields */
5479 #define USB_ADDINFO_IEHOST_MASK 0x1u
5480 #define USB_ADDINFO_IEHOST_SHIFT 0
5481 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
5482 #define USB_ADDINFO_IRQNUM_SHIFT 3
5483 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
5484 /* OTGISTAT Bit Fields */
5485 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
5486 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
5487 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
5488 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
5489 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
5490 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
5491 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
5492 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
5493 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
5494 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
5495 #define USB_OTGISTAT_IDCHG_MASK 0x80u
5496 #define USB_OTGISTAT_IDCHG_SHIFT 7
5497 /* OTGICR Bit Fields */
5498 #define USB_OTGICR_AVBUSEN_MASK 0x1u
5499 #define USB_OTGICR_AVBUSEN_SHIFT 0
5500 #define USB_OTGICR_BSESSEN_MASK 0x4u
5501 #define USB_OTGICR_BSESSEN_SHIFT 2
5502 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
5503 #define USB_OTGICR_SESSVLDEN_SHIFT 3
5504 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
5505 #define USB_OTGICR_LINESTATEEN_SHIFT 5
5506 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
5507 #define USB_OTGICR_ONEMSECEN_SHIFT 6
5508 #define USB_OTGICR_IDEN_MASK 0x80u
5509 #define USB_OTGICR_IDEN_SHIFT 7
5510 /* OTGSTAT Bit Fields */
5511 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
5512 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
5513 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
5514 #define USB_OTGSTAT_BSESSEND_SHIFT 2
5515 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
5516 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
5517 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
5518 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
5519 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
5520 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
5521 #define USB_OTGSTAT_ID_MASK 0x80u
5522 #define USB_OTGSTAT_ID_SHIFT 7
5523 /* OTGCTL Bit Fields */
5524 #define USB_OTGCTL_OTGEN_MASK 0x4u
5525 #define USB_OTGCTL_OTGEN_SHIFT 2
5526 #define USB_OTGCTL_DMLOW_MASK 0x10u
5527 #define USB_OTGCTL_DMLOW_SHIFT 4
5528 #define USB_OTGCTL_DPLOW_MASK 0x20u
5529 #define USB_OTGCTL_DPLOW_SHIFT 5
5530 #define USB_OTGCTL_DPHIGH_MASK 0x80u
5531 #define USB_OTGCTL_DPHIGH_SHIFT 7
5532 /* ISTAT Bit Fields */
5533 #define USB_ISTAT_USBRST_MASK 0x1u
5534 #define USB_ISTAT_USBRST_SHIFT 0
5535 #define USB_ISTAT_ERROR_MASK 0x2u
5536 #define USB_ISTAT_ERROR_SHIFT 1
5537 #define USB_ISTAT_SOFTOK_MASK 0x4u
5538 #define USB_ISTAT_SOFTOK_SHIFT 2
5539 #define USB_ISTAT_TOKDNE_MASK 0x8u
5540 #define USB_ISTAT_TOKDNE_SHIFT 3
5541 #define USB_ISTAT_SLEEP_MASK 0x10u
5542 #define USB_ISTAT_SLEEP_SHIFT 4
5543 #define USB_ISTAT_RESUME_MASK 0x20u
5544 #define USB_ISTAT_RESUME_SHIFT 5
5545 #define USB_ISTAT_ATTACH_MASK 0x40u
5546 #define USB_ISTAT_ATTACH_SHIFT 6
5547 #define USB_ISTAT_STALL_MASK 0x80u
5548 #define USB_ISTAT_STALL_SHIFT 7
5549 /* INTEN Bit Fields */
5550 #define USB_INTEN_USBRSTEN_MASK 0x1u
5551 #define USB_INTEN_USBRSTEN_SHIFT 0
5552 #define USB_INTEN_ERROREN_MASK 0x2u
5553 #define USB_INTEN_ERROREN_SHIFT 1
5554 #define USB_INTEN_SOFTOKEN_MASK 0x4u
5555 #define USB_INTEN_SOFTOKEN_SHIFT 2
5556 #define USB_INTEN_TOKDNEEN_MASK 0x8u
5557 #define USB_INTEN_TOKDNEEN_SHIFT 3
5558 #define USB_INTEN_SLEEPEN_MASK 0x10u
5559 #define USB_INTEN_SLEEPEN_SHIFT 4
5560 #define USB_INTEN_RESUMEEN_MASK 0x20u
5561 #define USB_INTEN_RESUMEEN_SHIFT 5
5562 #define USB_INTEN_ATTACHEN_MASK 0x40u
5563 #define USB_INTEN_ATTACHEN_SHIFT 6
5564 #define USB_INTEN_STALLEN_MASK 0x80u
5565 #define USB_INTEN_STALLEN_SHIFT 7
5566 /* ERRSTAT Bit Fields */
5567 #define USB_ERRSTAT_PIDERR_MASK 0x1u
5568 #define USB_ERRSTAT_PIDERR_SHIFT 0
5569 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
5570 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
5571 #define USB_ERRSTAT_CRC16_MASK 0x4u
5572 #define USB_ERRSTAT_CRC16_SHIFT 2
5573 #define USB_ERRSTAT_DFN8_MASK 0x8u
5574 #define USB_ERRSTAT_DFN8_SHIFT 3
5575 #define USB_ERRSTAT_BTOERR_MASK 0x10u
5576 #define USB_ERRSTAT_BTOERR_SHIFT 4
5577 #define USB_ERRSTAT_DMAERR_MASK 0x20u
5578 #define USB_ERRSTAT_DMAERR_SHIFT 5
5579 #define USB_ERRSTAT_BTSERR_MASK 0x80u
5580 #define USB_ERRSTAT_BTSERR_SHIFT 7
5581 /* ERREN Bit Fields */
5582 #define USB_ERREN_PIDERREN_MASK 0x1u
5583 #define USB_ERREN_PIDERREN_SHIFT 0
5584 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
5585 #define USB_ERREN_CRC5EOFEN_SHIFT 1
5586 #define USB_ERREN_CRC16EN_MASK 0x4u
5587 #define USB_ERREN_CRC16EN_SHIFT 2
5588 #define USB_ERREN_DFN8EN_MASK 0x8u
5589 #define USB_ERREN_DFN8EN_SHIFT 3
5590 #define USB_ERREN_BTOERREN_MASK 0x10u
5591 #define USB_ERREN_BTOERREN_SHIFT 4
5592 #define USB_ERREN_DMAERREN_MASK 0x20u
5593 #define USB_ERREN_DMAERREN_SHIFT 5
5594 #define USB_ERREN_BTSERREN_MASK 0x80u
5595 #define USB_ERREN_BTSERREN_SHIFT 7
5596 /* STAT Bit Fields */
5597 #define USB_STAT_ODD_MASK 0x4u
5598 #define USB_STAT_ODD_SHIFT 2
5599 #define USB_STAT_TX_MASK 0x8u
5600 #define USB_STAT_TX_SHIFT 3
5601 #define USB_STAT_ENDP_MASK 0xF0u
5602 #define USB_STAT_ENDP_SHIFT 4
5603 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
5604 /* CTL Bit Fields */
5605 #define USB_CTL_USBENSOFEN_MASK 0x1u
5606 #define USB_CTL_USBENSOFEN_SHIFT 0
5607 #define USB_CTL_ODDRST_MASK 0x2u
5608 #define USB_CTL_ODDRST_SHIFT 1
5609 #define USB_CTL_RESUME_MASK 0x4u
5610 #define USB_CTL_RESUME_SHIFT 2
5611 #define USB_CTL_HOSTMODEEN_MASK 0x8u
5612 #define USB_CTL_HOSTMODEEN_SHIFT 3
5613 #define USB_CTL_RESET_MASK 0x10u
5614 #define USB_CTL_RESET_SHIFT 4
5615 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
5616 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
5617 #define USB_CTL_SE0_MASK 0x40u
5618 #define USB_CTL_SE0_SHIFT 6
5619 #define USB_CTL_JSTATE_MASK 0x80u
5620 #define USB_CTL_JSTATE_SHIFT 7
5621 /* ADDR Bit Fields */
5622 #define USB_ADDR_ADDR_MASK 0x7Fu
5623 #define USB_ADDR_ADDR_SHIFT 0
5624 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
5625 #define USB_ADDR_LSEN_MASK 0x80u
5626 #define USB_ADDR_LSEN_SHIFT 7
5627 /* BDTPAGE1 Bit Fields */
5628 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
5629 #define USB_BDTPAGE1_BDTBA_SHIFT 1
5630 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
5631 /* FRMNUML Bit Fields */
5632 #define USB_FRMNUML_FRM_MASK 0xFFu
5633 #define USB_FRMNUML_FRM_SHIFT 0
5634 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
5635 /* FRMNUMH Bit Fields */
5636 #define USB_FRMNUMH_FRM_MASK 0x7u
5637 #define USB_FRMNUMH_FRM_SHIFT 0
5638 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
5639 /* TOKEN Bit Fields */
5640 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
5641 #define USB_TOKEN_TOKENENDPT_SHIFT 0
5642 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
5643 #define USB_TOKEN_TOKENPID_MASK 0xF0u
5644 #define USB_TOKEN_TOKENPID_SHIFT 4
5645 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
5646 /* SOFTHLD Bit Fields */
5647 #define USB_SOFTHLD_CNT_MASK 0xFFu
5648 #define USB_SOFTHLD_CNT_SHIFT 0
5649 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
5650 /* BDTPAGE2 Bit Fields */
5651 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
5652 #define USB_BDTPAGE2_BDTBA_SHIFT 0
5653 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
5654 /* BDTPAGE3 Bit Fields */
5655 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
5656 #define USB_BDTPAGE3_BDTBA_SHIFT 0
5657 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
5658 /* ENDPT Bit Fields */
5659 #define USB_ENDPT_EPHSHK_MASK 0x1u
5660 #define USB_ENDPT_EPHSHK_SHIFT 0
5661 #define USB_ENDPT_EPSTALL_MASK 0x2u
5662 #define USB_ENDPT_EPSTALL_SHIFT 1
5663 #define USB_ENDPT_EPTXEN_MASK 0x4u
5664 #define USB_ENDPT_EPTXEN_SHIFT 2
5665 #define USB_ENDPT_EPRXEN_MASK 0x8u
5666 #define USB_ENDPT_EPRXEN_SHIFT 3
5667 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
5668 #define USB_ENDPT_EPCTLDIS_SHIFT 4
5669 #define USB_ENDPT_RETRYDIS_MASK 0x40u
5670 #define USB_ENDPT_RETRYDIS_SHIFT 6
5671 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
5672 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
5673 /* USBCTRL Bit Fields */
5674 #define USB_USBCTRL_PDE_MASK 0x40u
5675 #define USB_USBCTRL_PDE_SHIFT 6
5676 #define USB_USBCTRL_SUSP_MASK 0x80u
5677 #define USB_USBCTRL_SUSP_SHIFT 7
5678 /* OBSERVE Bit Fields */
5679 #define USB_OBSERVE_DMPD_MASK 0x10u
5680 #define USB_OBSERVE_DMPD_SHIFT 4
5681 #define USB_OBSERVE_DPPD_MASK 0x40u
5682 #define USB_OBSERVE_DPPD_SHIFT 6
5683 #define USB_OBSERVE_DPPU_MASK 0x80u
5684 #define USB_OBSERVE_DPPU_SHIFT 7
5685 /* CONTROL Bit Fields */
5686 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
5687 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
5688 /* USBTRC0 Bit Fields */
5689 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
5690 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
5691 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
5692 #define USB_USBTRC0_SYNC_DET_SHIFT 1
5693 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
5694 #define USB_USBTRC0_USBRESMEN_SHIFT 5
5695 #define USB_USBTRC0_USBRESET_MASK 0x80u
5696 #define USB_USBTRC0_USBRESET_SHIFT 7
5697 /* USBFRMADJUST Bit Fields */
5698 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
5699 #define USB_USBFRMADJUST_ADJ_SHIFT 0
5700 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
5701
5702 /**
5703 * @}
5704 */ /* end of group USB_Register_Masks */
5705
5706
5707 /* USB - Peripheral instance base addresses */
5708 /** Peripheral USB0 base address */
5709 #define USB0_BASE (0x40072000u)
5710 /** Peripheral USB0 base pointer */
5711 #define USB0 ((USB_Type *)USB0_BASE)
5712
5713 /**
5714 * @}
5715 */ /* end of group USB_Peripheral_Access_Layer */
5716
5717
5718 /* ----------------------------------------------------------------------------
5719 -- USBDCD Peripheral Access Layer
5720 ---------------------------------------------------------------------------- */
5721
5722 /**
5723 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
5724 * @{
5725 */
5726
5727 /** USBDCD - Register Layout Typedef */
5728 typedef struct {
5729 __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
5730 __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
5731 __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
5732 uint8_t RESERVED_0[4];
5733 __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
5734 __IO uint32_t TIMER1; /**< , offset: 0x14 */
5735 __IO uint32_t TIMER2; /**< , offset: 0x18 */
5736 } USBDCD_Type;
5737
5738 /* ----------------------------------------------------------------------------
5739 -- USBDCD Register Masks
5740 ---------------------------------------------------------------------------- */
5741
5742 /**
5743 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
5744 * @{
5745 */
5746
5747 /* CONTROL Bit Fields */
5748 #define USBDCD_CONTROL_IACK_MASK 0x1u
5749 #define USBDCD_CONTROL_IACK_SHIFT 0
5750 #define USBDCD_CONTROL_IF_MASK 0x100u
5751 #define USBDCD_CONTROL_IF_SHIFT 8
5752 #define USBDCD_CONTROL_IE_MASK 0x10000u
5753 #define USBDCD_CONTROL_IE_SHIFT 16
5754 #define USBDCD_CONTROL_START_MASK 0x1000000u
5755 #define USBDCD_CONTROL_START_SHIFT 24
5756 #define USBDCD_CONTROL_SR_MASK 0x2000000u
5757 #define USBDCD_CONTROL_SR_SHIFT 25
5758 /* CLOCK Bit Fields */
5759 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
5760 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
5761 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
5762 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
5763 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
5764 /* STATUS Bit Fields */
5765 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
5766 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
5767 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
5768 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
5769 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
5770 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
5771 #define USBDCD_STATUS_ERR_MASK 0x100000u
5772 #define USBDCD_STATUS_ERR_SHIFT 20
5773 #define USBDCD_STATUS_TO_MASK 0x200000u
5774 #define USBDCD_STATUS_TO_SHIFT 21
5775 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
5776 #define USBDCD_STATUS_ACTIVE_SHIFT 22
5777 /* TIMER0 Bit Fields */
5778 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
5779 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
5780 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
5781 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
5782 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
5783 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
5784 /* TIMER1 Bit Fields */
5785 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
5786 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
5787 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
5788 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
5789 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
5790 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
5791 /* TIMER2 Bit Fields */
5792 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
5793 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
5794 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
5795 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
5796 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
5797 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
5798
5799 /**
5800 * @}
5801 */ /* end of group USBDCD_Register_Masks */
5802
5803
5804 /* USBDCD - Peripheral instance base addresses */
5805 /** Peripheral USBDCD base address */
5806 #define USBDCD_BASE (0x40035000u)
5807 /** Peripheral USBDCD base pointer */
5808 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
5809
5810 /**
5811 * @}
5812 */ /* end of group USBDCD_Peripheral_Access_Layer */
5813
5814
5815 /* ----------------------------------------------------------------------------
5816 -- VREF Peripheral Access Layer
5817 ---------------------------------------------------------------------------- */
5818
5819 /**
5820 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
5821 * @{
5822 */
5823
5824 /** VREF - Register Layout Typedef */
5825 typedef struct {
5826 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
5827 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
5828 } VREF_Type;
5829
5830 /* ----------------------------------------------------------------------------
5831 -- VREF Register Masks
5832 ---------------------------------------------------------------------------- */
5833
5834 /**
5835 * @addtogroup VREF_Register_Masks VREF Register Masks
5836 * @{
5837 */
5838
5839 /* TRM Bit Fields */
5840 #define VREF_TRM_TRIM_MASK 0x3Fu
5841 #define VREF_TRM_TRIM_SHIFT 0
5842 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
5843 #define VREF_TRM_CHOPEN_MASK 0x40u
5844 #define VREF_TRM_CHOPEN_SHIFT 6
5845 /* SC Bit Fields */
5846 #define VREF_SC_MODE_LV_MASK 0x3u
5847 #define VREF_SC_MODE_LV_SHIFT 0
5848 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
5849 #define VREF_SC_VREFST_MASK 0x4u
5850 #define VREF_SC_VREFST_SHIFT 2
5851 #define VREF_SC_REGEN_MASK 0x40u
5852 #define VREF_SC_REGEN_SHIFT 6
5853 #define VREF_SC_VREFEN_MASK 0x80u
5854 #define VREF_SC_VREFEN_SHIFT 7
5855
5856 /**
5857 * @}
5858 */ /* end of group VREF_Register_Masks */
5859
5860
5861 /* VREF - Peripheral instance base addresses */
5862 /** Peripheral VREF base address */
5863 #define VREF_BASE (0x40074000u)
5864 /** Peripheral VREF base pointer */
5865 #define VREF ((VREF_Type *)VREF_BASE)
5866
5867 /**
5868 * @}
5869 */ /* end of group VREF_Peripheral_Access_Layer */
5870
5871
5872 /* ----------------------------------------------------------------------------
5873 -- WDOG Peripheral Access Layer
5874 ---------------------------------------------------------------------------- */
5875
5876 /**
5877 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
5878 * @{
5879 */
5880
5881 /** WDOG - Register Layout Typedef */
5882 typedef struct {
5883 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
5884 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
5885 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
5886 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
5887 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
5888 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
5889 __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
5890 __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
5891 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
5892 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
5893 __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
5894 __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
5895 } WDOG_Type;
5896
5897 /* ----------------------------------------------------------------------------
5898 -- WDOG Register Masks
5899 ---------------------------------------------------------------------------- */
5900
5901 /**
5902 * @addtogroup WDOG_Register_Masks WDOG Register Masks
5903 * @{
5904 */
5905
5906 /* STCTRLH Bit Fields */
5907 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
5908 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
5909 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
5910 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
5911 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
5912 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
5913 #define WDOG_STCTRLH_WINEN_MASK 0x8u
5914 #define WDOG_STCTRLH_WINEN_SHIFT 3
5915 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
5916 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
5917 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
5918 #define WDOG_STCTRLH_DBGEN_SHIFT 5
5919 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
5920 #define WDOG_STCTRLH_STOPEN_SHIFT 6
5921 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
5922 #define WDOG_STCTRLH_WAITEN_SHIFT 7
5923 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
5924 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
5925 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
5926 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
5927 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
5928 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
5929 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
5930 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
5931 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
5932 /* STCTRLL Bit Fields */
5933 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
5934 #define WDOG_STCTRLL_INTFLG_SHIFT 15
5935 /* TOVALH Bit Fields */
5936 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
5937 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
5938 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
5939 /* TOVALL Bit Fields */
5940 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
5941 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
5942 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
5943 /* WINH Bit Fields */
5944 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
5945 #define WDOG_WINH_WINHIGH_SHIFT 0
5946 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
5947 /* WINL Bit Fields */
5948 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
5949 #define WDOG_WINL_WINLOW_SHIFT 0
5950 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
5951 /* REFRESH Bit Fields */
5952 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
5953 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
5954 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
5955 /* UNLOCK Bit Fields */
5956 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
5957 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
5958 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
5959 /* TMROUTH Bit Fields */
5960 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
5961 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
5962 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
5963 /* TMROUTL Bit Fields */
5964 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
5965 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
5966 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
5967 /* RSTCNT Bit Fields */
5968 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
5969 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
5970 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
5971 /* PRESC Bit Fields */
5972 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
5973 #define WDOG_PRESC_PRESCVAL_SHIFT 8
5974 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
5975
5976 /**
5977 * @}
5978 */ /* end of group WDOG_Register_Masks */
5979
5980
5981 /* WDOG - Peripheral instance base addresses */
5982 /** Peripheral WDOG base address */
5983 #define WDOG_BASE (0x40052000u)
5984 /** Peripheral WDOG base pointer */
5985 #define WDOG ((WDOG_Type *)WDOG_BASE)
5986
5987 /**
5988 * @}
5989 */ /* end of group WDOG_Peripheral_Access_Layer */
5990
5991
5992 /*
5993 ** End of section using anonymous unions
5994 */
5995
5996 #if defined(__ARMCC_VERSION)
5997 #pragma pop
5998 #elif defined(__CWCC__)
5999 #pragma pop
6000 #elif defined(__GNUC__)
6001 /* leave anonymous unions enabled */
6002 #elif defined(__IAR_SYSTEMS_ICC__)
6003 #pragma language=default
6004 #else
6005 #error Not supported compiler type
6006 #endif
6007
6008 /**
6009 * @}
6010 */ /* end of group Peripheral_access_layer */
6011
6012
6013 /* ----------------------------------------------------------------------------
6014 -- Backward Compatibility
6015 ---------------------------------------------------------------------------- */
6016
6017 /**
6018 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
6019 * @{
6020 */
6021
6022 /* No backward compatibility issues. */
6023
6024 /**
6025 * @}
6026 */ /* end of group Backward_Compatibility_Symbols */
6027
6028
6029 #endif /* #if !defined(MK20D5_H_) */
6030
6031 /* MK20D5.h, eof. */
6032
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