tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f0xx.c
   4   * @author  MCD Application Team
   5   * @version V2.1.0
   6   * @date    03-Oct-2014
   7   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   8   *
   9   * 1.  This file provides two functions and one global variable to be called from
  10   *     user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32f0xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24   *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
  25   *    configure the system clock before to branch to main program.
  26   *
  27   * 3. This file configures the system clock as follows:
  28   *=============================================================================
  29   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  30   *                                    | (external 8 MHz clock) | (internal 48 MHz)
  31   *                                    | 2- PLL_HSE_XTAL        |
  32   *                                    | (external 8 MHz xtal)  |
  33   *-----------------------------------------------------------------------------
  34   * SYSCLK(MHz)                        | 48                     | 48
  35   *-----------------------------------------------------------------------------
  36   * AHBCLK (MHz)                       | 48                     | 48
  37   *-----------------------------------------------------------------------------
  38   * APB1CLK (MHz)                      | 48                     | 48
  39   *-----------------------------------------------------------------------------
  40   * USB capable (48 MHz precise clock) | YES                    | YES
  41   *=============================================================================
  42   ******************************************************************************
  43   * @attention
  44   *
  45   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  46   *
  47   * Redistribution and use in source and binary forms, with or without modification,
  48   * are permitted provided that the following conditions are met:
  49   *   1. Redistributions of source code must retain the above copyright notice,
  50   *      this list of conditions and the following disclaimer.
  51   *   2. Redistributions in binary form must reproduce the above copyright notice,
  52   *      this list of conditions and the following disclaimer in the documentation
  53   *      and/or other materials provided with the distribution.
  54   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  55   *      may be used to endorse or promote products derived from this software
  56   *      without specific prior written permission.
  57   *
  58   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  59   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  60   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  61   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  62   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  63   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  64   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  65   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  66   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  67   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  68   *
  69   ******************************************************************************
  70   */
  71
  72 /** @addtogroup CMSIS
  73   * @{
  74   */
  75
  76 /** @addtogroup stm32f0xx_system
  77   * @{
  78   */
  79
  80 /** @addtogroup STM32F0xx_System_Private_Includes
  81   * @{
  82   */
  83
  84 #include "stm32f0xx.h"
  85
  86 /**
  87   * @}
  88   */
  89
  90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
  91   * @{
  92   */
  93
  94 /**
  95   * @}
  96   */
  97
  98 /** @addtogroup STM32F0xx_System_Private_Defines
  99   * @{
 100   */
 101 #if !defined  (HSE_VALUE)
 102   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
 103                                                 This value can be provided and adapted by the user application. */
 104 #endif /* HSE_VALUE */
 105
 106 #if !defined  (HSI_VALUE)
 107   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
 108                                                 This value can be provided and adapted by the user application. */
 109 #endif /* HSI_VALUE */
 110 /**
 111   * @}
 112   */
 113
 114 /** @addtogroup STM32F0xx_System_Private_Macros
 115   * @{
 116   */
 117
 118 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 119 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 120 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 121
 122 /**
 123   * @}
 124   */
 125
 126 /** @addtogroup STM32F0xx_System_Private_Variables
 127   * @{
 128   */
 129   /* This variable is updated in three ways:
 130       1) by calling CMSIS function SystemCoreClockUpdate()
 131       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 132       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 133          Note: If you use this function to configure the system clock there is no need to
 134                call the 2 first functions listed above, since SystemCoreClock variable is
 135                updated automatically.
 136   */
 137 uint32_t SystemCoreClock    = 48000000;
 138 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 139
 140 /**
 141   * @}
 142   */
 143
 144 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
 145   * @{
 146   */
 147
 148 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 150 #endif
 151
 152 uint8_t SetSysClock_PLL_HSI(void);
 153
 154 /**
 155   * @}
 156   */
 157
 158 /** @addtogroup STM32F0xx_System_Private_Functions
 159   * @{
 160   */
 161
 162 /**
 163   * @brief  Setup the microcontroller system.
 164   *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
 165   * @param  None
 166   * @retval None
 167   */
 168 void SystemInit(void)
 169 {
 170   /* Reset the RCC clock configuration to the default reset state ------------*/
 171   /* Set HSION bit */
 172   RCC->CR |= (uint32_t)0x00000001;
 173
 174 #if defined (STM32F051x8) || defined (STM32F058x8)
 175   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
 176   RCC->CFGR &= (uint32_t)0xF8FFB80C;
 177 #else
 178   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
 179   RCC->CFGR &= (uint32_t)0x08FFB80C;
 180 #endif /* STM32F051x8 or STM32F058x8 */
 181
 182   /* Reset HSEON, CSSON and PLLON bits */
 183   RCC->CR &= (uint32_t)0xFEF6FFFF;
 184
 185   /* Reset HSEBYP bit */
 186   RCC->CR &= (uint32_t)0xFFFBFFFF;
 187
 188   /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
 189   RCC->CFGR &= (uint32_t)0xFFC0FFFF;
 190
 191   /* Reset PREDIV[3:0] bits */
 192   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 193
 194 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
 195   /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
 196   RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
 197 #elif defined (STM32F091xC) || defined (STM32F098xx)
 198   /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
 199   RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
 200 #else
 201   /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW  and ADCSW bits */
 202   RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
 203 #endif
 204
 205   /* Reset HSI14 bit */
 206   RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 207
 208   /* Disable all interrupts */
 209   RCC->CIR = 0x00000000;
 210
 211   /* Configure the Cube driver */
 212   SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
 213   HAL_Init();
 214
 215   /* Configure the System clock source, PLL Multiplier and Divider factors,
 216    AHB/APBx prescalers and Flash settings */
 217   SetSysClock();
 218 }
 219
 220 /**
 221    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 222   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 223   *         be used by the user application to setup the SysTick timer or configure
 224   *         other parameters.
 225   *
 226   * @note   Each time the core clock (HCLK) changes, this function must be called
 227   *         to update SystemCoreClock variable value. Otherwise, any configuration
 228   *         based on this variable will be incorrect.
 229   *
 230   * @note   - The system frequency computed by this function is not the real
 231   *           frequency in the chip. It is calculated based on the predefined
 232   *           constant and the selected clock source:
 233   *
 234   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 235   *
 236   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 237   *
 238   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 239   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 240   *
 241   *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
 242   *             8 MHz) but the real value may vary depending on the variations
 243   *             in voltage and temperature.
 244   *
 245   *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
 246   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 247   *              frequency of the crystal used. Otherwise, this function may
 248   *              have wrong result.
 249   *
 250   *         - The result of this function could be not correct when using fractional
 251   *           value for HSE crystal.
 252   *
 253   * @param  None
 254   * @retval None
 255   */
 256 void SystemCoreClockUpdate (void)
 257 {
 258   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
 259
 260   /* Get SYSCLK source -------------------------------------------------------*/
 261   tmp = RCC->CFGR & RCC_CFGR_SWS;
 262
 263   switch (tmp)
 264   {
 265     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 266       SystemCoreClock = HSI_VALUE;
 267       break;
 268     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 269       SystemCoreClock = HSE_VALUE;
 270       break;
 271     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 272       /* Get PLL clock source and multiplication factor ----------------------*/
 273       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 274       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 275       pllmull = ( pllmull >> 18) + 2;
 276       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 277
 278       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 279       {
 280         /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
 281         SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
 282       }
 283 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 284       else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
 285       {
 286         /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
 287         SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
 288       }
 289 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
 290       else
 291       {
 292 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 293         /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
 294         SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
 295 #else
 296         /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
 297         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 298 #endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
 299       }
 300       break;
 301     default: /* HSI used as system clock */
 302       SystemCoreClock = HSI_VALUE;
 303       break;
 304   }
 305   /* Compute HCLK clock frequency ----------------*/
 306   /* Get HCLK prescaler */
 307   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 308   /* HCLK clock frequency */
 309   SystemCoreClock >>= tmp;
 310 }
 311
 312 /**
 313   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 314   *               AHB/APBx prescalers and Flash settings
 315   * @note   This function should be called only once the RCC clock configuration
 316   *         is reset to the default reset state (done in SystemInit() function).
 317   * @param  None
 318   * @retval None
 319   */
 320 void SetSysClock(void)
 321 {
 322   /* 1- Try to start with HSE and external clock */
 323 #if USE_PLL_HSE_EXTC != 0
 324   if (SetSysClock_PLL_HSE(1) == 0)
 325 #endif
 326   {
 327     /* 2- If fail try to start with HSE and external xtal */
 328     #if USE_PLL_HSE_XTAL != 0
 329     if (SetSysClock_PLL_HSE(0) == 0)
 330     #endif
 331     {
 332       /* 3- If fail start with HSI clock */
 333       if (SetSysClock_PLL_HSI() == 0)
 334       {
 335         while(1)
 336         {
 337           // [TODO] Put something here to tell the user that a problem occured...
 338         }
 339       }
 340     }
 341   }
 342
 343   // Output clock on MCO pin(PA8) for debugging purpose
 344   //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
 345 }
 346
 347 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 348 /******************************************************************************/
 349 /*            PLL (clocked by HSE) used as System clock source                */
 350 /******************************************************************************/
 351 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 352 {
 353   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 354   RCC_OscInitTypeDef RCC_OscInitStruct;
 355
 356   // Select HSE oscillator as PLL source
 357   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
 358   if (bypass == 0) {
 359       RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
 360   } else {
 361       RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
 362   }
 363   RCC_OscInitStruct.HSI48State     = 0; // not used
 364   RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
 365   RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
 366   RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
 367   RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
 368   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 369       return 0; // FAIL
 370     }
 371
 372   // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
 373   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
 374   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
 375   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
 376   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
 377   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
 378       return 0; // FAIL
 379     }
 380
 381     return 1; // OK
 382 }
 383 #endif
 384
 385 /******************************************************************************/
 386 /*            PLL (clocked by HSI) used as System clock source                */
 387 /******************************************************************************/
 388 uint8_t SetSysClock_PLL_HSI(void)
 389 {
 390   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 391   RCC_OscInitTypeDef RCC_OscInitStruct;
 392
 393   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
 394   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 395         RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
 396   RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
 397   RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
 398   RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
 399   RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
 400   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 401       return 0; // FAIL
 402   }
 403
 404   // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
 405   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
 406   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
 407   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
 408   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
 409   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
 410       return 0; // FAIL
 411   }
 412
 413   return 1; // OK
 414 }
 415
 416 /* Used for the different timeouts in the HAL */
 417 void SysTick_Handler(void)
 418 {
 419   HAL_IncTick();
 420 }
 421
 422 /**
 423   * @}
 424   */
 425
 426 /**
 427   * @}
 428   */
 429
 430 /**
 431   * @}
 432   */
 433
 434 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 435