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1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_pcd.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 11-December-2014
7 * @brief Header file of PCD HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F0xx_HAL_PCD_H
40 #define __STM32F0xx_HAL_PCD_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
47
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f0xx_hal_def.h"
50
51 /** @addtogroup STM32F0xx_HAL_Driver
52 * @{
53 */
54
55 /** @addtogroup PCD
56 * @{
57 */
58
59 /* Exported types ------------------------------------------------------------*/
60 /** @defgroup PCD_Exported_Types PCD Exported Types
61 * @{
62 */
63
64 /**
65 * @brief PCD State structures definition
66 */
67 typedef enum
68 {
69 PCD_READY = 0x00,
70 PCD_ERROR = 0x01,
71 PCD_BUSY = 0x02,
72 PCD_TIMEOUT = 0x03
73 } PCD_StateTypeDef;
74
75 typedef enum
76 {
77 /* double buffered endpoint direction */
78 PCD_EP_DBUF_OUT,
79 PCD_EP_DBUF_IN,
80 PCD_EP_DBUF_ERR,
81 }PCD_EP_DBUF_DIR;
82
83 /* endpoint buffer number */
84 typedef enum
85 {
86 PCD_EP_NOBUF,
87 PCD_EP_BUF0,
88 PCD_EP_BUF1
89 }PCD_EP_BUF_NUM;
90
91 /**
92 * @brief PCD Initialization Structure definition
93 */
94 typedef struct
95 {
96 uint32_t dev_endpoints; /*!< Device Endpoints number.
97 This parameter depends on the used USB core.
98 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
99
100 uint32_t speed; /*!< USB Core speed.
101 This parameter can be any value of @ref PCD_Core_Speed */
102
103 uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
104 This parameter can be any value of @ref PCD_EP0_MPS */
105
106 uint32_t phy_itface; /*!< Select the used PHY interface.
107 This parameter can be any value of @ref PCD_Core_PHY */
108
109 uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
110 This parameter can be set to ENABLE or DISABLE */
111
112 uint32_t low_power_enable; /*!< Enable or disable Low Power mode
113 This parameter can be set to ENABLE or DISABLE */
114
115 uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
116 This parameter can be set to ENABLE or DISABLE */
117
118 uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
119 This parameter can be set to ENABLE or DISABLE */
120
121 }PCD_InitTypeDef;
122
123 typedef struct
124 {
125 uint8_t num; /*!< Endpoint number
126 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
127
128 uint8_t is_in; /*!< Endpoint direction
129 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
130
131 uint8_t is_stall; /*!< Endpoint stall condition
132 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
133
134 uint8_t type; /*!< Endpoint type
135 This parameter can be any value of @ref PCD_EP_Type */
136
137 uint16_t pmaadress; /*!< PMA Address
138 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
139
140
141 uint16_t pmaaddr0; /*!< PMA Address0
142 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
143
144
145 uint16_t pmaaddr1; /*!< PMA Address1
146 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
147
148
149 uint8_t doublebuffer; /*!< Double buffer enable
150 This parameter can be 0 or 1 */
151
152 uint32_t maxpacket; /*!< Endpoint Max packet size
153 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
154
155 uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
156
157
158 uint32_t xfer_len; /*!< Current transfer length */
159
160 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
161
162 }PCD_EPTypeDef;
163
164 typedef USB_TypeDef PCD_TypeDef;
165
166 /**
167 * @brief PCD Handle Structure definition
168 */
169 typedef struct
170 {
171 PCD_TypeDef *Instance; /*!< Register base address */
172 PCD_InitTypeDef Init; /*!< PCD required parameters */
173 __IO uint8_t USB_Address; /*!< USB Address */
174 PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
175 PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
176 HAL_LockTypeDef Lock; /*!< PCD peripheral status */
177 __IO PCD_StateTypeDef State; /*!< PCD communication state */
178 uint32_t Setup[12]; /*!< Setup packet buffer */
179 void *pData; /*!< Pointer to upper stack Handler */
180
181 } PCD_HandleTypeDef;
182
183 /**
184 * @}
185 */
186
187 #include "stm32f0xx_hal_pcd_ex.h"
188 /* Exported constants --------------------------------------------------------*/
189 /** @defgroup PCD_Exported_Constants PCD Exported Constants
190 * @{
191 */
192
193 /** @defgroup PCD_Core_Speed PCD Core Speed
194 * @{
195 */
196 #define PCD_SPEED_HIGH 0 /* Not Supported */
197 #define PCD_SPEED_FULL 2
198 /**
199 * @}
200 */
201
202 /** @defgroup PCD_Core_PHY PCD Core PHY
203 * @{
204 */
205 #define PCD_PHY_EMBEDDED 2
206 /**
207 * @}
208 */
209
210 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
211 * @{
212 */
213 #define DEP0CTL_MPS_64 0
214 #define DEP0CTL_MPS_32 1
215 #define DEP0CTL_MPS_16 2
216 #define DEP0CTL_MPS_8 3
217
218 #define PCD_EP0MPS_64 DEP0CTL_MPS_64
219 #define PCD_EP0MPS_32 DEP0CTL_MPS_32
220 #define PCD_EP0MPS_16 DEP0CTL_MPS_16
221 #define PCD_EP0MPS_08 DEP0CTL_MPS_8
222 /**
223 * @}
224 */
225
226 /** @defgroup PCD_EP_Type PCD EP Type
227 * @{
228 */
229 #define PCD_EP_TYPE_CTRL 0
230 #define PCD_EP_TYPE_ISOC 1
231 #define PCD_EP_TYPE_BULK 2
232 #define PCD_EP_TYPE_INTR 3
233 /**
234 * @}
235 */
236
237 /** @defgroup PCD_ENDP_Type PCD_ENDP_Type
238 * @{
239 */
240
241 #define PCD_ENDP0 ((uint8_t)0)
242 #define PCD_ENDP1 ((uint8_t)1)
243 #define PCD_ENDP2 ((uint8_t)2)
244 #define PCD_ENDP3 ((uint8_t)3)
245 #define PCD_ENDP4 ((uint8_t)4)
246 #define PCD_ENDP5 ((uint8_t)5)
247 #define PCD_ENDP6 ((uint8_t)6)
248 #define PCD_ENDP7 ((uint8_t)7)
249
250 /* Endpoint Kind */
251 #define PCD_SNG_BUF 0
252 #define PCD_DBL_BUF 1
253
254 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
255 /**
256 * @}
257 */
258
259 /**
260 * @}
261 */
262
263 /* Exported macros -----------------------------------------------------------*/
264
265 /** @defgroup PCD_Exported_Macros PCD Exported Macros
266 * @brief macros to handle interrupts and specific clock configurations
267 * @{
268 */
269 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
270 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
271
272 #define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
273
274 #define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP
275 #define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP)
276 #define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
277
278 /**
279 * @}
280 */
281
282 /* Internal macros -----------------------------------------------------------*/
283
284 /** @defgroup PCD_Private_Macros PCD Private Macros
285 * @brief macros to handle interrupts and specific clock configurations
286 * @{
287 */
288
289 /* SetENDPOINT */
290 #define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
291
292 /* GetENDPOINT */
293 #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
294
295
296
297 /**
298 * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
299 * @param USBx: USB peripheral instance register address.
300 * @param bEpNum: Endpoint Number.
301 * @param wType: Endpoint Type.
302 * @retval None
303 */
304 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
305 ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
306
307 /**
308 * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
309 * @param USBx: USB peripheral instance register address.
310 * @param bEpNum: Endpoint Number.
311 * @retval Endpoint Type
312 */
313 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
314
315
316 /**
317 * @brief free buffer used from the application realizing it to the line
318 toggles bit SW_BUF in the double buffered endpoint register
319 * @param USBx: USB peripheral instance register address.
320 * @param bEpNum: Endpoint Number.
321 * @param bDir: Direction
322 * @retval None
323 */
324 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
325 {\
326 if ((bDir) == PCD_EP_DBUF_OUT)\
327 { /* OUT double buffered endpoint */\
328 PCD_TX_DTOG((USBx), (bEpNum));\
329 }\
330 else if ((bDir) == PCD_EP_DBUF_IN)\
331 { /* IN double buffered endpoint */\
332 PCD_RX_DTOG((USBx), (bEpNum));\
333 }\
334 }
335
336 /**
337 * @brief gets direction of the double buffered endpoint
338 * @param USBx: USB peripheral instance register address.
339 * @param bEpNum: Endpoint Number.
340 * @retval EP_DBUF_OUT, EP_DBUF_IN,
341 * EP_DBUF_ERR if the endpoint counter not yet programmed.
342 */
343 #define PCD_GET_DB_DIR(USBx, bEpNum)\
344 {\
345 if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
346 return(PCD_EP_DBUF_OUT);\
347 else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
348 return(PCD_EP_DBUF_IN);\
349 else\
350 return(PCD_EP_DBUF_ERR);\
351 }
352
353 /**
354 * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
355 * @param USBx: USB peripheral instance register address.
356 * @param bEpNum: Endpoint Number.
357 * @param wState: new state
358 * @retval None
359 */
360 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
361 register uint16_t _wRegVal; \
362 \
363 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
364 /* toggle first bit ? */ \
365 if((USB_EPTX_DTOG1 & (wState))!= 0) \
366 _wRegVal ^= USB_EPTX_DTOG1; \
367 /* toggle second bit ? */ \
368 if((USB_EPTX_DTOG2 & (wState))!= 0) \
369 _wRegVal ^= USB_EPTX_DTOG2; \
370 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
371 } /* PCD_SET_EP_TX_STATUS */
372
373 /**
374 * @brief sets the status for rx transfer (bits STAT_TX[1:0])
375 * @param USBx: USB peripheral instance register address.
376 * @param bEpNum: Endpoint Number.
377 * @param wState: new state
378 * @retval None
379 */
380 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
381 register uint16_t _wRegVal; \
382 \
383 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
384 /* toggle first bit ? */ \
385 if((USB_EPRX_DTOG1 & (wState))!= 0) \
386 _wRegVal ^= USB_EPRX_DTOG1; \
387 /* toggle second bit ? */ \
388 if((USB_EPRX_DTOG2 & (wState))!= 0) \
389 _wRegVal ^= USB_EPRX_DTOG2; \
390 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
391 } /* PCD_SET_EP_RX_STATUS */
392
393 /**
394 * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
395 * @param USBx: USB peripheral instance register address.
396 * @param bEpNum: Endpoint Number.
397 * @param wStaterx: new state.
398 * @param wStatetx: new state.
399 * @retval None
400 */
401 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
402 register uint32_t _wRegVal; \
403 \
404 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
405 /* toggle first bit ? */ \
406 if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
407 _wRegVal ^= USB_EPRX_DTOG1; \
408 /* toggle second bit ? */ \
409 if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
410 _wRegVal ^= USB_EPRX_DTOG2; \
411 /* toggle first bit ? */ \
412 if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
413 _wRegVal ^= USB_EPTX_DTOG1; \
414 /* toggle second bit ? */ \
415 if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
416 _wRegVal ^= USB_EPTX_DTOG2; \
417 PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
418 } /* PCD_SET_EP_TXRX_STATUS */
419
420 /**
421 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
422 * /STAT_RX[1:0])
423 * @param USBx: USB peripheral instance register address.
424 * @param bEpNum: Endpoint Number.
425 * @retval status
426 */
427 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
428
429 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
430
431 /**
432 * @brief sets directly the VALID tx/rx-status into the endpoint register
433 * @param USBx: USB peripheral instance register address.
434 * @param bEpNum: Endpoint Number.
435 * @retval None
436 */
437 #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
438
439 #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
440
441 /**
442 * @brief checks stall condition in an endpoint.
443 * @param USBx: USB peripheral instance register address.
444 * @param bEpNum: Endpoint Number.
445 * @retval TRUE = endpoint in stall condition.
446 */
447 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
448 == USB_EP_TX_STALL)
449 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
450 == USB_EP_RX_STALL)
451
452 /**
453 * @brief set & clear EP_KIND bit.
454 * @param USBx: USB peripheral instance register address.
455 * @param bEpNum: Endpoint Number.
456 * @retval None
457 */
458 #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
459 (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
460 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
461 (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
462
463 /**
464 * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
465 * @param USBx: USB peripheral instance register address.
466 * @param bEpNum: Endpoint Number.
467 * @retval None
468 */
469 #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
470 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
471
472 /**
473 * @brief Sets/clears directly EP_KIND bit in the endpoint register.
474 * @param USBx: USB peripheral instance register address.
475 * @param bEpNum: Endpoint Number.
476 * @retval None
477 */
478 #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
479 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
480
481 /**
482 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
483 * @param USBx: USB peripheral instance register address.
484 * @param bEpNum: Endpoint Number.
485 * @retval None
486 */
487 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
488 PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
489 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
490 PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
491
492 /**
493 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
494 * @param USBx: USB peripheral instance register address.
495 * @param bEpNum: Endpoint Number.
496 * @retval None
497 */
498 #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
499 USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
500 #define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
501 USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
502
503 /**
504 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
505 * @param USBx: USB peripheral instance register address.
506 * @param bEpNum: Endpoint Number.
507 * @retval None
508 */
509 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
510 PCD_RX_DTOG((USBx), (bEpNum))
511 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
512 PCD_TX_DTOG((USBx), (bEpNum))
513
514 /**
515 * @brief Sets address in an endpoint register.
516 * @param USBx: USB peripheral instance register address.
517 * @param bEpNum: Endpoint Number.
518 * @param bAddr: Address.
519 * @retval None
520 */
521 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
522 USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
523
524 /**
525 * @brief Gets address in an endpoint register.
526 * @param USBx: USB peripheral instance register address.
527 * @param bEpNum: Endpoint Number.
528 * @retval None
529 */
530 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
531
532 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400)))
533 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400)))
534 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400)))
535 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400)))
536
537 /**
538 * @brief sets address of the tx/rx buffer.
539 * @param USBx: USB peripheral instance register address.
540 * @param bEpNum: Endpoint Number.
541 * @param wAddr: address to be set (must be word aligned).
542 * @retval None
543 */
544 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
545 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
546
547 /**
548 * @brief Gets address of the tx/rx buffer.
549 * @param USBx: USB peripheral instance register address.
550 * @param bEpNum: Endpoint Number.
551 * @retval address of the buffer.
552 */
553 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
554 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
555
556 /**
557 * @brief Sets counter of rx buffer with no. of blocks.
558 * @param dwReg: Register
559 * @param wCount: Counter.
560 * @param wNBlocks: no. of Blocks.
561 * @retval None
562 */
563 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
564 (wNBlocks) = (wCount) >> 5;\
565 if(((wCount) & 0x1f) == 0)\
566 (wNBlocks)--;\
567 *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\
568 }/* PCD_CALC_BLK32 */
569
570 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
571 (wNBlocks) = (wCount) >> 1;\
572 if(((wCount) & 0x1) != 0)\
573 (wNBlocks)++;\
574 *pdwReg = (uint16_t)((wNBlocks) << 10);\
575 }/* PCD_CALC_BLK2 */
576
577 #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
578 uint16_t wNBlocks;\
579 if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\
580 else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\
581 }/* PCD_SET_EP_CNT_RX_REG */
582
583 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
584 uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
585 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
586 }
587 /**
588 * @brief sets counter for the tx/rx buffer.
589 * @param USBx: USB peripheral instance register address.
590 * @param bEpNum: Endpoint Number.
591 * @param wCount: Counter value.
592 * @retval None
593 */
594 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
595 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
596 uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
597 PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
598 }
599
600 /**
601 * @brief gets counter of the tx buffer.
602 * @param USBx: USB peripheral instance register address.
603 * @param bEpNum: Endpoint Number.
604 * @retval Counter value
605 */
606 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
607 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
608
609 /**
610 * @brief Sets buffer 0/1 address in a double buffer endpoint.
611 * @param USBx: USB peripheral instance register address.
612 * @param bEpNum: Endpoint Number.
613 * @param wBuf0Addr: buffer 0 address.
614 * @retval Counter value
615 */
616 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
617 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
618
619 /**
620 * @brief Sets addresses in a double buffer endpoint.
621 * @param USBx: USB peripheral instance register address.
622 * @param bEpNum: Endpoint Number.
623 * @param wBuf0Addr: buffer 0 address.
624 * @param wBuf1Addr = buffer 1 address.
625 * @retval None
626 */
627 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
628 PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
629 PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
630 } /* PCD_SET_EP_DBUF_ADDR */
631
632 /**
633 * @brief Gets buffer 0/1 address of a double buffer endpoint.
634 * @param USBx: USB peripheral instance register address.
635 * @param bEpNum: Endpoint Number.
636 * @retval None
637 */
638 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
639 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
640
641 /**
642 * @brief Gets buffer 0/1 address of a double buffer endpoint.
643 * @param USBx: USB peripheral instance register address.
644 * @param bEpNum: Endpoint Number.
645 * @param bDir: endpoint dir EP_DBUF_OUT = OUT
646 * EP_DBUF_IN = IN
647 * @param wCount: Counter value
648 * @retval None
649 */
650 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
651 if((bDir) == PCD_EP_DBUF_OUT)\
652 /* OUT endpoint */ \
653 {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
654 else if((bDir) == PCD_EP_DBUF_IN)\
655 /* IN endpoint */ \
656 *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
657 } /* SetEPDblBuf0Count*/
658
659 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
660 if((bDir) == PCD_EP_DBUF_OUT)\
661 /* OUT endpoint */ \
662 {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\
663 else if((bDir) == PCD_EP_DBUF_IN)\
664 /* IN endpoint */\
665 *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
666 } /* SetEPDblBuf1Count */
667
668 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
669 PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
670 PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
671 } /* PCD_SET_EP_DBUF_CNT */
672
673 /**
674 * @brief Gets buffer 0/1 rx/tx counter for double buffering.
675 * @param USBx: USB peripheral instance register address.
676 * @param bEpNum: Endpoint Number.
677 * @retval None
678 */
679 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
680 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
681
682
683 /**
684 * @}
685 */
686
687 /* Exported functions --------------------------------------------------------*/
688
689 /** @addtogroup PCD_Exported_Functions
690 * @{
691 */
692
693 /** @addtogroup PCD_Exported_Functions_Group1
694 * @{
695 */
696 /* Initialization and de-initialization functions **********************************/
697 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
698 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
699 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
700 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
701
702 /**
703 * @}
704 */
705
706 /** @addtogroup PCD_Exported_Functions_Group2
707 * @{
708 */
709 /* IO operation functions *****************************************************/
710 /* Non Blocking mode: Interrupt */
711 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
712 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
713 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
714
715 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
716 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
717 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
718 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
719 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
720 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
721 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
722 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
723 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
724 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
725 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
726
727 /**
728 * @}
729 */
730
731 /** @addtogroup PCD_Exported_Functions_Group3
732 * @{
733 */
734 /* Peripheral Control functions ************************************************/
735 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
736 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
737 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
738 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
739 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
740 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
741 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
742 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
743 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
744 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
745 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
746 HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
747 HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
748 /**
749 * @}
750 */
751
752 /** @addtogroup PCD_Exported_Functions_Group4
753 * @{
754 */
755 /* Peripheral State functions **************************************************/
756 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
757 /**
758 * @}
759 */
760
761 /**
762 * @}
763 */
764
765 /**
766 * @}
767 */
768
769 /**
770 * @}
771 */
772
773 #endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
774
775 #ifdef __cplusplus
776 }
777 #endif
778
779
780 #endif /* __STM32F0xx_HAL_PCD_H */
781
782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
783
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