Merge pull request #355 from papodaca/XT
[tmk_keyboard.git] / converter / ps2_usb / config.h
1 /*
2 Copyright 2012 Jun Wako <wakojun@gmail.com>
3
4 This program is free software: you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation, either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef CONFIG_H
19 #define CONFIG_H
20
21 #include <avr/interrupt.h>
22
23 #define VENDOR_ID 0xFEED
24 #define PRODUCT_ID 0x6512
25 #define DEVICE_VER 0x0001
26 #define MANUFACTURER t.m.k.
27 #define PRODUCT PS/2 keyboard converter
28 #define DESCRIPTION convert PS/2 keyboard to USB
29
30
31 /* matrix size */
32 #define MATRIX_ROWS 32 // keycode bit: 3-0
33 #define MATRIX_COLS 8 // keycode bit: 6-4
34
35
36 /* key combination for command */
37 #define IS_COMMAND() ( \
38 keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) || \
39 keyboard_report->mods == (MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RSHIFT)) \
40 )
41
42
43 //#define NO_SUSPEND_POWER_DOWN
44
45
46 /*
47 * PS/2 Busywait
48 */
49 #ifdef PS2_USE_BUSYWAIT
50 #define PS2_CLOCK_PORT PORTD
51 #define PS2_CLOCK_PIN PIND
52 #define PS2_CLOCK_DDR DDRD
53 #define PS2_CLOCK_BIT 1
54 #define PS2_DATA_PORT PORTD
55 #define PS2_DATA_PIN PIND
56 #define PS2_DATA_DDR DDRD
57 #define PS2_DATA_BIT 0
58 #endif
59
60 /*
61 * PS/2 Pin interrupt
62 */
63 #ifdef PS2_USE_INT
64 #if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__)
65 /* uses INT1 for clock line(ATMega32U4) */
66 #define PS2_CLOCK_PORT PORTD
67 #define PS2_CLOCK_PIN PIND
68 #define PS2_CLOCK_DDR DDRD
69 #define PS2_CLOCK_BIT 1
70 #define PS2_DATA_PORT PORTD
71 #define PS2_DATA_PIN PIND
72 #define PS2_DATA_DDR DDRD
73 #define PS2_DATA_BIT 0
74 #define PS2_INT_INIT() do { \
75 EICRA |= ((1<<ISC11) | \
76 (0<<ISC10)); \
77 } while (0)
78 #define PS2_INT_ON() do { \
79 EIMSK |= (1<<INT1); \
80 } while (0)
81 #define PS2_INT_OFF() do { \
82 EIMSK &= ~(1<<INT1); \
83 } while (0)
84 #define PS2_INT_VECT INT1_vect
85
86 #elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__)
87 /* uses PCINT17(PD1) for clock line. this doesn't work with VUSB */
88 #define PS2_CLOCK_PORT PORTD
89 #define PS2_CLOCK_PIN PIND
90 #define PS2_CLOCK_DDR DDRD
91 #define PS2_CLOCK_BIT 1
92 #define PS2_DATA_PORT PORTD
93 #define PS2_DATA_PIN PIND
94 #define PS2_DATA_DDR DDRD
95 #define PS2_DATA_BIT 0
96 #define PS2_INT_INIT() do { \
97 PCICR |= (1<<PCIE2); \
98 } while (0)
99 #define PS2_INT_ON() do { \
100 PCMSK2 |= (1<<PCINT17); \
101 } while (0)
102 #define PS2_INT_OFF() do { \
103 PCMSK2 &= ~(1<<PCINT17); \
104 } while (0)
105 #define PS2_INT_VECT PCINT2_vect
106 #endif
107 #endif
108
109 /*
110 * PS/2 USART
111 */
112 #ifdef PS2_USE_USART
113 #if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__)
114 /* XCK for clock line and RXD for data line */
115 #define PS2_CLOCK_PORT PORTD
116 #define PS2_CLOCK_PIN PIND
117 #define PS2_CLOCK_DDR DDRD
118 #define PS2_CLOCK_BIT 5
119 #define PS2_DATA_PORT PORTD
120 #define PS2_DATA_PIN PIND
121 #define PS2_DATA_DDR DDRD
122 #define PS2_DATA_BIT 2
123 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
124 /* set DDR of CLOCK as input to be slave */
125 #define PS2_USART_INIT() do { \
126 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
127 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
128 UCSR1C = ((1 << UMSEL10) | \
129 (3 << UPM10) | \
130 (0 << USBS1) | \
131 (3 << UCSZ10) | \
132 (0 << UCPOL1)); \
133 UCSR1A = 0; \
134 UBRR1H = 0; \
135 UBRR1L = 0; \
136 } while (0)
137 #define PS2_USART_RX_INT_ON() do { \
138 UCSR1B = ((1 << RXCIE1) | \
139 (1 << RXEN1)); \
140 } while (0)
141 #define PS2_USART_RX_POLL_ON() do { \
142 UCSR1B = (1 << RXEN1); \
143 } while (0)
144 #define PS2_USART_OFF() do { \
145 UCSR1C = 0; \
146 UCSR1B &= ~((1 << RXEN1) | \
147 (1 << TXEN1)); \
148 } while (0)
149 #define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
150 #define PS2_USART_RX_DATA UDR1
151 #define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
152 #define PS2_USART_RX_VECT USART1_RX_vect
153 #elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__)
154 /* XCK for clock line and RXD for data line */
155 #define PS2_CLOCK_PORT PORTD
156 #define PS2_CLOCK_PIN PIND
157 #define PS2_CLOCK_DDR DDRD
158 #define PS2_CLOCK_BIT 4
159 #define PS2_DATA_PORT PORTD
160 #define PS2_DATA_PIN PIND
161 #define PS2_DATA_DDR DDRD
162 #define PS2_DATA_BIT 0
163 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
164 /* set DDR of CLOCK as input to be slave */
165 #define PS2_USART_INIT() do { \
166 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
167 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
168 UCSR0C = ((1 << UMSEL00) | \
169 (3 << UPM00) | \
170 (0 << USBS0) | \
171 (3 << UCSZ00) | \
172 (0 << UCPOL0)); \
173 UCSR0A = 0; \
174 UBRR0H = 0; \
175 UBRR0L = 0; \
176 } while (0)
177 #define PS2_USART_RX_INT_ON() do { \
178 UCSR0B = ((1 << RXCIE0) | \
179 (1 << RXEN0)); \
180 } while (0)
181 #define PS2_USART_RX_POLL_ON() do { \
182 UCSR0B = (1 << RXEN0); \
183 } while (0)
184 #define PS2_USART_OFF() do { \
185 UCSR0C = 0; \
186 UCSR0B &= ~((1 << RXEN0) | \
187 (1 << TXEN0)); \
188 } while (0)
189 #define PS2_USART_RX_READY (UCSR0A & (1<<RXC0))
190 #define PS2_USART_RX_DATA UDR0
191 #define PS2_USART_ERROR (UCSR0A & ((1<<FE0) | (1<<DOR0) | (1<<UPE0)))
192 #define PS2_USART_RX_VECT USART_RX_vect
193 #endif
194 #endif
195
196 #endif
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