2 ******************************************************************************
3 * @file stm32f30x_tim.c
4 * @author MCD Application Team
6 * @date 27-February-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the TIM peripheral:
9 * + TimeBase management
10 * + Output Compare management
11 * + Input Capture management
12 * + Advanced-control timers (TIM1 and TIM8) specific features
13 * + Interrupts, DMA and flags management
15 * + Synchronization management
16 * + Specific interface management
17 * + Specific remapping management
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..] This driver provides functions to configure and program the TIM
25 of all stm32f30x devices.
26 These functions are split in 9 groups:
28 (#) TIM TimeBase management: this group includes all needed functions
29 to configure the TM Timebase unit:
30 (++) Set/Get Prescaler
31 (++) Set/Get Autoreload
32 (++) Counter modes configuration
33 (++) Set Clock division
34 (++) Select the One Pulse mode
35 (++) Update Request Configuration
36 (++) Update Disable Configuration
37 (++) Auto-Preload Configuration
38 (++) Enable/Disable the counter
40 (#) TIM Output Compare management: this group includes all needed
41 functions to configure the Capture/Compare unit used in Output
43 (++) Configure each channel, independently, in Output Compare mode
44 (++) Select the output compare modes
45 (++) Select the Polarities of each channel
46 (++) Set/Get the Capture/Compare register values
47 (++) Select the Output Compare Fast mode
48 (++) Select the Output Compare Forced mode
49 (++) Output Compare-Preload Configuration
50 (++) Clear Output Compare Reference
51 (++) Select the OCREF Clear signal
52 (++) Enable/Disable the Capture/Compare Channels
54 (#) TIM Input Capture management: this group includes all needed
55 functions to configure the Capture/Compare unit used in
57 (++) Configure each channel in input capture mode
58 (++) Configure Channel1/2 in PWM Input mode
59 (++) Set the Input Capture Prescaler
60 (++) Get the Capture/Compare values
62 (#) Advanced-control timers (TIM1 and TIM8) specific features
63 (++) Configures the Break input, dead time, Lock level, the OSSI,
64 the OSSR State and the AOE(automatic output enable)
65 (++) Enable/Disable the TIM peripheral Main Outputs
66 (++) Select the Commutation event
67 (++) Set/Reset the Capture Compare Preload Control bit
69 (#) TIM interrupts, DMA and flags management
70 (++) Enable/Disable interrupt sources
72 (++) Clear flags/ Pending bits
73 (++) Enable/Disable DMA requests
74 (++) Configure DMA burst mode
75 (++) Select CaptureCompare DMA request
77 (#) TIM clocks management: this group includes all needed functions
78 to configure the clock controller unit:
79 (++) Select internal/External clock
80 (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
82 (#) TIM synchronization management: this group includes all needed
83 functions to configure the Synchronization unit:
84 (++) Select Input Trigger
85 (++) Select Output Trigger
86 (++) Select Master Slave Mode
87 (++) ETR Configuration when used as external trigger
89 (#) TIM specific interface management, this group includes all
90 needed functions to use the specific TIM interface:
91 (++) Encoder Interface Configuration
92 (++) Select Hall Sensor
94 (#) TIM specific remapping management includes the Remapping
95 configuration of specific timers
99 ******************************************************************************
102 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
104 * Redistribution and use in source and binary forms, with or without modification,
105 * are permitted provided that the following conditions are met:
106 * 1. Redistributions of source code must retain the above copyright notice,
107 * this list of conditions and the following disclaimer.
108 * 2. Redistributions in binary form must reproduce the above copyright notice,
109 * this list of conditions and the following disclaimer in the documentation
110 * and/or other materials provided with the distribution.
111 * 3. Neither the name of STMicroelectronics nor the names of its contributors
112 * may be used to endorse or promote products derived from this software
113 * without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
116 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
117 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
118 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
119 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
120 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
121 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
122 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
123 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
124 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
126 ******************************************************************************
129 /* Includes ------------------------------------------------------------------*/
130 #include "stm32f30x_tim.h"
131 #include "stm32f30x_rcc.h"
133 /** @addtogroup STM32F30x_StdPeriph_Driver
138 * @brief TIM driver modules
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
145 /* ---------------------- TIM registers bit mask ------------------------ */
146 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
147 #define CCMR_OFFSET ((uint16_t)0x0018)
148 #define CCER_CCE_SET ((uint16_t)0x0001)
149 #define CCER_CCNE_SET ((uint16_t)0x0004)
150 #define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F)
151 #define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF)
153 /* Private macro -------------------------------------------------------------*/
154 /* Private variables ---------------------------------------------------------*/
155 /* Private function prototypes -----------------------------------------------*/
156 static void TI1_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
157 uint16_t TIM_ICFilter
);
158 static void TI2_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
159 uint16_t TIM_ICFilter
);
160 static void TI3_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
161 uint16_t TIM_ICFilter
);
162 static void TI4_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
163 uint16_t TIM_ICFilter
);
165 /* Private functions ---------------------------------------------------------*/
167 /** @defgroup TIM_Private_Functions
171 /** @defgroup TIM_Group1 TimeBase management functions
172 * @brief TimeBase management functions
175 ===============================================================================
176 ##### TimeBase management functions #####
177 ===============================================================================
180 *** TIM Driver: how to use it in Timing(Time base) Mode ***
181 ============================================================
183 To use the Timer in Timing(Time base) mode, the following steps are mandatory:
185 (#) Enable TIM clock using
186 RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
187 (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
188 (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
190 with the corresponding configuration
191 (#) Enable the NVIC if you need to generate the update interrupt.
192 (#) Enable the corresponding interrupt using the function
193 TIM_ITConfig(TIMx, TIM_IT_Update)
194 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
196 (@) All other functions can be used separately to modify, if needed,
197 a specific feature of the Timer.
204 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
205 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
209 void TIM_DeInit(TIM_TypeDef
* TIMx
)
211 /* Check the parameters */
212 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
216 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1
, ENABLE
);
217 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1
, DISABLE
);
219 else if (TIMx
== TIM2
)
221 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2
, ENABLE
);
222 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2
, DISABLE
);
224 else if (TIMx
== TIM3
)
226 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3
, ENABLE
);
227 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3
, DISABLE
);
229 else if (TIMx
== TIM4
)
231 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4
, ENABLE
);
232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4
, DISABLE
);
234 else if (TIMx
== TIM6
)
236 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6
, ENABLE
);
237 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6
, DISABLE
);
239 else if (TIMx
== TIM7
)
241 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7
, ENABLE
);
242 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7
, DISABLE
);
244 else if (TIMx
== TIM8
)
246 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8
, ENABLE
);
247 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8
, DISABLE
);
249 else if (TIMx
== TIM15
)
251 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15
, ENABLE
);
252 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15
, DISABLE
);
254 else if (TIMx
== TIM16
)
256 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16
, ENABLE
);
257 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16
, DISABLE
);
263 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17
, ENABLE
);
264 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17
, DISABLE
);
270 * @brief Initializes the TIMx Time Base Unit peripheral according to
271 * the specified parameters in the TIM_TimeBaseInitStruct.
272 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
273 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
274 * that contains the configuration information for the specified TIM peripheral.
277 void TIM_TimeBaseInit(TIM_TypeDef
* TIMx
, TIM_TimeBaseInitTypeDef
* TIM_TimeBaseInitStruct
)
281 /* Check the parameters */
282 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
283 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct
->TIM_CounterMode
));
284 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct
->TIM_ClockDivision
));
288 if((TIMx
== TIM1
) || (TIMx
== TIM8
)|| (TIMx
== TIM2
) ||
289 (TIMx
== TIM3
)|| (TIMx
== TIM4
))
291 /* Select the Counter Mode */
292 tmpcr1
&= (uint16_t)(~(TIM_CR1_DIR
| TIM_CR1_CMS
));
293 tmpcr1
|= (uint32_t)TIM_TimeBaseInitStruct
->TIM_CounterMode
;
296 if((TIMx
!= TIM6
) && (TIMx
!= TIM7
))
298 /* Set the clock division */
299 tmpcr1
&= (uint16_t)(~TIM_CR1_CKD
);
300 tmpcr1
|= (uint32_t)TIM_TimeBaseInitStruct
->TIM_ClockDivision
;
305 /* Set the Autoreload value */
306 TIMx
->ARR
= TIM_TimeBaseInitStruct
->TIM_Period
;
308 /* Set the Prescaler value */
309 TIMx
->PSC
= TIM_TimeBaseInitStruct
->TIM_Prescaler
;
311 if ((TIMx
== TIM1
) || (TIMx
== TIM8
)|| (TIMx
== TIM15
) ||
312 (TIMx
== TIM16
) || (TIMx
== TIM17
))
314 /* Set the Repetition Counter value */
315 TIMx
->RCR
= TIM_TimeBaseInitStruct
->TIM_RepetitionCounter
;
318 /* Generate an update event to reload the Prescaler
319 and the repetition counter(only for TIM1 and TIM8) value immediatly */
320 TIMx
->EGR
= TIM_PSCReloadMode_Immediate
;
324 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
325 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
326 * structure which will be initialized.
329 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef
* TIM_TimeBaseInitStruct
)
331 /* Set the default configuration */
332 TIM_TimeBaseInitStruct
->TIM_Period
= 0xFFFFFFFF;
333 TIM_TimeBaseInitStruct
->TIM_Prescaler
= 0x0000;
334 TIM_TimeBaseInitStruct
->TIM_ClockDivision
= TIM_CKD_DIV1
;
335 TIM_TimeBaseInitStruct
->TIM_CounterMode
= TIM_CounterMode_Up
;
336 TIM_TimeBaseInitStruct
->TIM_RepetitionCounter
= 0x0000;
340 * @brief Configures the TIMx Prescaler.
341 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
342 * @param Prescaler: specifies the Prescaler Register value
343 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
344 * This parameter can be one of the following values:
345 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
346 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
349 void TIM_PrescalerConfig(TIM_TypeDef
* TIMx
, uint16_t Prescaler
, uint16_t TIM_PSCReloadMode
)
351 /* Check the parameters */
352 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
353 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode
));
354 /* Set the Prescaler value */
355 TIMx
->PSC
= Prescaler
;
356 /* Set or reset the UG Bit */
357 TIMx
->EGR
= TIM_PSCReloadMode
;
361 * @brief Specifies the TIMx Counter Mode to be used.
362 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
363 * @param TIM_CounterMode: specifies the Counter Mode to be used
364 * This parameter can be one of the following values:
365 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
366 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
367 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
368 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
369 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
372 void TIM_CounterModeConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_CounterMode
)
376 /* Check the parameters */
377 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
378 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode
));
382 /* Reset the CMS and DIR Bits */
383 tmpcr1
&= (uint16_t)~(TIM_CR1_DIR
| TIM_CR1_CMS
);
385 /* Set the Counter Mode */
386 tmpcr1
|= TIM_CounterMode
;
388 /* Write to TIMx CR1 register */
393 * @brief Sets the TIMx Counter Register value
394 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
395 * @param Counter: specifies the Counter register new value.
398 void TIM_SetCounter(TIM_TypeDef
* TIMx
, uint32_t Counter
)
400 /* Check the parameters */
401 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
403 /* Set the Counter Register value */
408 * @brief Sets the TIMx Autoreload Register value
409 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
410 * @param Autoreload: specifies the Autoreload register new value.
413 void TIM_SetAutoreload(TIM_TypeDef
* TIMx
, uint32_t Autoreload
)
415 /* Check the parameters */
416 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
418 /* Set the Autoreload Register value */
419 TIMx
->ARR
= Autoreload
;
423 * @brief Gets the TIMx Counter value.
424 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
425 * @retval Counter Register value
427 uint32_t TIM_GetCounter(TIM_TypeDef
* TIMx
)
429 /* Check the parameters */
430 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
432 /* Get the Counter Register value */
437 * @brief Gets the TIMx Prescaler value.
438 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
439 * @retval Prescaler Register value.
441 uint16_t TIM_GetPrescaler(TIM_TypeDef
* TIMx
)
443 /* Check the parameters */
444 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
446 /* Get the Prescaler Register value */
451 * @brief Enables or Disables the TIMx Update event.
452 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
453 * @param NewState: new state of the TIMx UDIS bit
454 * This parameter can be: ENABLE or DISABLE.
457 void TIM_UpdateDisableConfig(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
459 /* Check the parameters */
460 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
461 assert_param(IS_FUNCTIONAL_STATE(NewState
));
463 if (NewState
!= DISABLE
)
465 /* Set the Update Disable Bit */
466 TIMx
->CR1
|= TIM_CR1_UDIS
;
470 /* Reset the Update Disable Bit */
471 TIMx
->CR1
&= (uint16_t)~TIM_CR1_UDIS
;
476 * @brief Configures the TIMx Update Request Interrupt source.
477 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
478 * @param TIM_UpdateSource: specifies the Update source.
479 * This parameter can be one of the following values:
480 * @arg TIM_UpdateSource_Regular: Source of update is the counter
481 * overflow/underflow or the setting of UG bit, or an update
482 * generation through the slave mode controller.
483 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
486 void TIM_UpdateRequestConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_UpdateSource
)
488 /* Check the parameters */
489 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
490 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource
));
492 if (TIM_UpdateSource
!= TIM_UpdateSource_Global
)
494 /* Set the URS Bit */
495 TIMx
->CR1
|= TIM_CR1_URS
;
499 /* Reset the URS Bit */
500 TIMx
->CR1
&= (uint16_t)~TIM_CR1_URS
;
505 * @brief Sets or resets the update interrupt flag (UIF)status bit Remapping.
506 * when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]
507 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
508 * @param NewState: new state of the UIFREMAP bit.
509 * This parameter can be: ENABLE or DISABLE.
512 void TIM_UIFRemap(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
514 /* Check the parameters */
515 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
516 assert_param(IS_FUNCTIONAL_STATE(NewState
));
518 if (NewState
!= DISABLE
)
520 /* Enable the TIM Counter */
521 TIMx
->CR1
|= TIM_CR1_UIFREMAP
;
525 /* Disable the TIM Counter */
526 TIMx
->CR1
&= (uint16_t)~TIM_CR1_UIFREMAP
;
531 * @brief Enables or disables TIMx peripheral Preload register on ARR.
532 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
533 * @param NewState: new state of the TIMx peripheral Preload register
534 * This parameter can be: ENABLE or DISABLE.
537 void TIM_ARRPreloadConfig(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
539 /* Check the parameters */
540 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
541 assert_param(IS_FUNCTIONAL_STATE(NewState
));
543 if (NewState
!= DISABLE
)
545 /* Set the ARR Preload Bit */
546 TIMx
->CR1
|= TIM_CR1_ARPE
;
550 /* Reset the ARR Preload Bit */
551 TIMx
->CR1
&= (uint16_t)~TIM_CR1_ARPE
;
556 * @brief Selects the TIMx's One Pulse Mode.
557 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
558 * @param TIM_OPMode: specifies the OPM Mode to be used.
559 * This parameter can be one of the following values:
560 * @arg TIM_OPMode_Single
561 * @arg TIM_OPMode_Repetitive
564 void TIM_SelectOnePulseMode(TIM_TypeDef
* TIMx
, uint16_t TIM_OPMode
)
566 /* Check the parameters */
567 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
568 assert_param(IS_TIM_OPM_MODE(TIM_OPMode
));
570 /* Reset the OPM Bit */
571 TIMx
->CR1
&= (uint16_t)~TIM_CR1_OPM
;
573 /* Configure the OPM Mode */
574 TIMx
->CR1
|= TIM_OPMode
;
578 * @brief Sets the TIMx Clock Division value.
579 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
580 * @param TIM_CKD: specifies the clock division value.
581 * This parameter can be one of the following value:
582 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
583 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
584 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
587 void TIM_SetClockDivision(TIM_TypeDef
* TIMx
, uint16_t TIM_CKD
)
589 /* Check the parameters */
590 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
591 assert_param(IS_TIM_CKD_DIV(TIM_CKD
));
593 /* Reset the CKD Bits */
594 TIMx
->CR1
&= (uint16_t)(~TIM_CR1_CKD
);
596 /* Set the CKD value */
597 TIMx
->CR1
|= TIM_CKD
;
601 * @brief Enables or disables the specified TIM peripheral.
602 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select
603 * the TIMx peripheral.
604 * @param NewState: new state of the TIMx peripheral.
605 * This parameter can be: ENABLE or DISABLE.
608 void TIM_Cmd(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
610 /* Check the parameters */
611 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
612 assert_param(IS_FUNCTIONAL_STATE(NewState
));
614 if (NewState
!= DISABLE
)
616 /* Enable the TIM Counter */
617 TIMx
->CR1
|= TIM_CR1_CEN
;
621 /* Disable the TIM Counter */
622 TIMx
->CR1
&= (uint16_t)~TIM_CR1_CEN
;
629 /** @defgroup TIM_Group2 Output Compare management functions
630 * @brief Output Compare management functions
633 ===============================================================================
634 ##### Output Compare management functions #####
635 ===============================================================================
637 *** TIM Driver: how to use it in Output Compare Mode ***
638 ========================================================
640 To use the Timer in Output Compare mode, the following steps are mandatory:
642 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
644 (#) Configure the TIM pins by configuring the corresponding GPIO pins
646 (#) Configure the Time base unit as described in the first part of this driver,
647 if needed, else the Timer will run with the default configuration:
648 (++) Autoreload value = 0xFFFF
649 (++) Prescaler value = 0x0000
650 (++) Counter mode = Up counting
651 (++) Clock Division = TIM_CKD_DIV1
652 (#) Fill the TIM_OCInitStruct with the desired parameters including:
653 (++) The TIM Output Compare mode: TIM_OCMode
654 (++) TIM Output State: TIM_OutputState
655 (++) TIM Pulse value: TIM_Pulse
656 (++) TIM Output Compare Polarity : TIM_OCPolarity
658 (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
659 corresponding configuration
661 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
663 (@) All other functions can be used separately to modify, if needed,
664 a specific feature of the Timer.
666 (@) In case of PWM mode, this function is mandatory:
667 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
669 (@) If the corresponding interrupt or DMA request are needed, the user should:
670 (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
671 (#@) Enable the corresponding interrupt (or DMA request) using the function
672 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
679 * @brief Initializes the TIMx Channel1 according to the specified parameters in
680 * the TIM_OCInitStruct.
681 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
682 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
683 * the configuration information for the specified TIM peripheral.
686 void TIM_OC1Init(TIM_TypeDef
* TIMx
, TIM_OCInitTypeDef
* TIM_OCInitStruct
)
688 uint32_t tmpccmrx
= 0, tmpccer
= 0, tmpcr2
= 0;
690 /* Check the parameters */
691 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
692 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct
->TIM_OCMode
));
693 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct
->TIM_OutputState
));
694 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct
->TIM_OCPolarity
));
696 /* Disable the Channel 1: Reset the CC1E Bit */
697 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC1E
;
699 /* Get the TIMx CCER register value */
700 tmpccer
= TIMx
->CCER
;
701 /* Get the TIMx CR2 register value */
704 /* Get the TIMx CCMR1 register value */
705 tmpccmrx
= TIMx
->CCMR1
;
707 /* Reset the Output Compare Mode Bits */
708 tmpccmrx
&= (uint32_t)~TIM_CCMR1_OC1M
;
709 tmpccmrx
&= (uint32_t)~TIM_CCMR1_CC1S
;
710 /* Select the Output Compare Mode */
711 tmpccmrx
|= TIM_OCInitStruct
->TIM_OCMode
;
713 /* Reset the Output Polarity level */
714 tmpccer
&= (uint32_t)~TIM_CCER_CC1P
;
715 /* Set the Output Compare Polarity */
716 tmpccer
|= TIM_OCInitStruct
->TIM_OCPolarity
;
718 /* Set the Output State */
719 tmpccer
|= TIM_OCInitStruct
->TIM_OutputState
;
721 if((TIMx
== TIM1
) || (TIMx
== TIM8
) || (TIMx
== TIM15
) || (TIMx
== TIM16
) || (TIMx
== TIM17
))
723 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct
->TIM_OutputNState
));
724 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct
->TIM_OCNPolarity
));
725 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct
->TIM_OCNIdleState
));
726 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct
->TIM_OCIdleState
));
728 /* Reset the Output N Polarity level */
729 tmpccer
&= (uint32_t)~TIM_CCER_CC1NP
;
730 /* Set the Output N Polarity */
731 tmpccer
|= TIM_OCInitStruct
->TIM_OCNPolarity
;
732 /* Reset the Output N State */
733 tmpccer
&= (uint32_t)~TIM_CCER_CC1NE
;
735 /* Set the Output N State */
736 tmpccer
|= TIM_OCInitStruct
->TIM_OutputNState
;
737 /* Reset the Output Compare and Output Compare N IDLE State */
738 tmpcr2
&= (uint32_t)~TIM_CR2_OIS1
;
739 tmpcr2
&= (uint32_t)~TIM_CR2_OIS1N
;
740 /* Set the Output Idle state */
741 tmpcr2
|= TIM_OCInitStruct
->TIM_OCIdleState
;
742 /* Set the Output N Idle state */
743 tmpcr2
|= TIM_OCInitStruct
->TIM_OCNIdleState
;
745 /* Write to TIMx CR2 */
748 /* Write to TIMx CCMR1 */
749 TIMx
->CCMR1
= tmpccmrx
;
751 /* Set the Capture Compare Register value */
752 TIMx
->CCR1
= TIM_OCInitStruct
->TIM_Pulse
;
754 /* Write to TIMx CCER */
755 TIMx
->CCER
= tmpccer
;
759 * @brief Initializes the TIMx Channel2 according to the specified parameters
760 * in the TIM_OCInitStruct.
761 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
762 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
763 * the configuration information for the specified TIM peripheral.
766 void TIM_OC2Init(TIM_TypeDef
* TIMx
, TIM_OCInitTypeDef
* TIM_OCInitStruct
)
768 uint32_t tmpccmrx
= 0, tmpccer
= 0, tmpcr2
= 0;
770 /* Check the parameters */
771 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
772 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct
->TIM_OCMode
));
773 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct
->TIM_OutputState
));
774 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct
->TIM_OCPolarity
));
776 /* Disable the Channel 2: Reset the CC2E Bit */
777 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC2E
;
779 /* Get the TIMx CCER register value */
780 tmpccer
= TIMx
->CCER
;
781 /* Get the TIMx CR2 register value */
784 /* Get the TIMx CCMR1 register value */
785 tmpccmrx
= TIMx
->CCMR1
;
787 /* Reset the Output Compare mode and Capture/Compare selection Bits */
788 tmpccmrx
&= (uint32_t)~TIM_CCMR1_OC2M
;
789 tmpccmrx
&= (uint32_t)~TIM_CCMR1_CC2S
;
791 /* Select the Output Compare Mode */
792 tmpccmrx
|= (uint32_t)(TIM_OCInitStruct
->TIM_OCMode
<< 8);
794 /* Reset the Output Polarity level */
795 tmpccer
&= (uint32_t)~TIM_CCER_CC2P
;
796 /* Set the Output Compare Polarity */
797 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCPolarity
<< 4);
799 /* Set the Output State */
800 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputState
<< 4);
802 if((TIMx
== TIM1
) || (TIMx
== TIM8
))
804 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct
->TIM_OutputNState
));
805 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct
->TIM_OCNPolarity
));
806 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct
->TIM_OCNIdleState
));
807 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct
->TIM_OCIdleState
));
809 /* Reset the Output N Polarity level */
810 tmpccer
&= (uint32_t)~TIM_CCER_CC2NP
;
811 /* Set the Output N Polarity */
812 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCNPolarity
<< 4);
813 /* Reset the Output N State */
814 tmpccer
&= (uint32_t)~TIM_CCER_CC2NE
;
816 /* Set the Output N State */
817 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputNState
<< 4);
818 /* Reset the Output Compare and Output Compare N IDLE State */
819 tmpcr2
&= (uint32_t)~TIM_CR2_OIS2
;
820 tmpcr2
&= (uint32_t)~TIM_CR2_OIS2N
;
821 /* Set the Output Idle state */
822 tmpcr2
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCIdleState
<< 2);
823 /* Set the Output N Idle state */
824 tmpcr2
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCNIdleState
<< 2);
826 /* Write to TIMx CR2 */
829 /* Write to TIMx CCMR1 */
830 TIMx
->CCMR1
= tmpccmrx
;
832 /* Set the Capture Compare Register value */
833 TIMx
->CCR2
= TIM_OCInitStruct
->TIM_Pulse
;
835 /* Write to TIMx CCER */
836 TIMx
->CCER
= tmpccer
;
840 * @brief Initializes the TIMx Channel3 according to the specified parameters
841 * in the TIM_OCInitStruct.
842 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
843 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
844 * the configuration information for the specified TIM peripheral.
847 void TIM_OC3Init(TIM_TypeDef
* TIMx
, TIM_OCInitTypeDef
* TIM_OCInitStruct
)
849 uint32_t tmpccmrx
= 0, tmpccer
= 0, tmpcr2
= 0;
851 /* Check the parameters */
852 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
853 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct
->TIM_OCMode
));
854 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct
->TIM_OutputState
));
855 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct
->TIM_OCPolarity
));
857 /* Disable the Channel 3: Reset the CC2E Bit */
858 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC3E
;
860 /* Get the TIMx CCER register value */
861 tmpccer
= TIMx
->CCER
;
862 /* Get the TIMx CR2 register value */
865 /* Get the TIMx CCMR2 register value */
866 tmpccmrx
= TIMx
->CCMR2
;
868 /* Reset the Output Compare mode and Capture/Compare selection Bits */
869 tmpccmrx
&= (uint32_t)~TIM_CCMR2_OC3M
;
870 tmpccmrx
&= (uint32_t)~TIM_CCMR2_CC3S
;
871 /* Select the Output Compare Mode */
872 tmpccmrx
|= TIM_OCInitStruct
->TIM_OCMode
;
874 /* Reset the Output Polarity level */
875 tmpccer
&= (uint32_t)~TIM_CCER_CC3P
;
876 /* Set the Output Compare Polarity */
877 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCPolarity
<< 8);
879 /* Set the Output State */
880 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputState
<< 8);
882 if((TIMx
== TIM1
) || (TIMx
== TIM8
))
884 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct
->TIM_OutputNState
));
885 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct
->TIM_OCNPolarity
));
886 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct
->TIM_OCNIdleState
));
887 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct
->TIM_OCIdleState
));
889 /* Reset the Output N Polarity level */
890 tmpccer
&= (uint32_t)~TIM_CCER_CC3NP
;
891 /* Set the Output N Polarity */
892 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCNPolarity
<< 8);
893 /* Reset the Output N State */
894 tmpccer
&= (uint32_t)~TIM_CCER_CC3NE
;
896 /* Set the Output N State */
897 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputNState
<< 8);
898 /* Reset the Output Compare and Output Compare N IDLE State */
899 tmpcr2
&= (uint32_t)~TIM_CR2_OIS3
;
900 tmpcr2
&= (uint32_t)~TIM_CR2_OIS3N
;
901 /* Set the Output Idle state */
902 tmpcr2
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCIdleState
<< 4);
903 /* Set the Output N Idle state */
904 tmpcr2
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCNIdleState
<< 4);
906 /* Write to TIMx CR2 */
909 /* Write to TIMx CCMR2 */
910 TIMx
->CCMR2
= tmpccmrx
;
912 /* Set the Capture Compare Register value */
913 TIMx
->CCR3
= TIM_OCInitStruct
->TIM_Pulse
;
915 /* Write to TIMx CCER */
916 TIMx
->CCER
= tmpccer
;
920 * @brief Initializes the TIMx Channel4 according to the specified parameters
921 * in the TIM_OCInitStruct.
922 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
923 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
924 * the configuration information for the specified TIM peripheral.
927 void TIM_OC4Init(TIM_TypeDef
* TIMx
, TIM_OCInitTypeDef
* TIM_OCInitStruct
)
929 uint32_t tmpccmrx
= 0, tmpccer
= 0, tmpcr2
= 0;
931 /* Check the parameters */
932 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
933 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct
->TIM_OCMode
));
934 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct
->TIM_OutputState
));
935 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct
->TIM_OCPolarity
));
937 /* Disable the Channel 4: Reset the CC4E Bit */
938 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC4E
;
940 /* Get the TIMx CCER register value */
941 tmpccer
= TIMx
->CCER
;
942 /* Get the TIMx CR2 register value */
945 /* Get the TIMx CCMR2 register value */
946 tmpccmrx
= TIMx
->CCMR2
;
948 /* Reset the Output Compare mode and Capture/Compare selection Bits */
949 tmpccmrx
&= (uint32_t)~TIM_CCMR2_OC4M
;
950 tmpccmrx
&= (uint32_t)~TIM_CCMR2_CC4S
;
952 /* Select the Output Compare Mode */
953 tmpccmrx
|= (uint32_t)(TIM_OCInitStruct
->TIM_OCMode
<< 8);
955 /* Reset the Output Polarity level */
956 tmpccer
&= (uint32_t)~TIM_CCER_CC4P
;
957 /* Set the Output Compare Polarity */
958 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCPolarity
<< 12);
960 /* Set the Output State */
961 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputState
<< 12);
963 if((TIMx
== TIM1
) || (TIMx
== TIM8
))
965 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct
->TIM_OCIdleState
));
966 /* Reset the Output Compare IDLE State */
967 tmpcr2
&=(uint32_t) ~TIM_CR2_OIS4
;
968 /* Set the Output Idle state */
969 tmpcr2
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCIdleState
<< 6);
971 /* Write to TIMx CR2 */
974 /* Write to TIMx CCMR2 */
975 TIMx
->CCMR2
= tmpccmrx
;
977 /* Set the Capture Compare Register value */
978 TIMx
->CCR4
= TIM_OCInitStruct
->TIM_Pulse
;
980 /* Write to TIMx CCER */
981 TIMx
->CCER
= tmpccer
;
985 * @brief Initializes the TIMx Channel5 according to the specified parameters
986 * in the TIM_OCInitStruct.
987 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
988 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
989 * the configuration information for the specified TIM peripheral.
992 void TIM_OC5Init(TIM_TypeDef
* TIMx
, TIM_OCInitTypeDef
* TIM_OCInitStruct
)
994 uint32_t tmpccmrx
= 0, tmpccer
= 0, tmpcr2
= 0;
996 /* Check the parameters */
997 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
998 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct
->TIM_OCMode
));
999 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct
->TIM_OutputState
));
1000 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct
->TIM_OCPolarity
));
1002 /* Disable the Channel 5: Reset the CC5E Bit */
1003 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC5E
; /* to be verified*/
1005 /* Get the TIMx CCER register value */
1006 tmpccer
= TIMx
->CCER
;
1007 /* Get the TIMx CR2 register value */
1010 /* Get the TIMx CCMR3 register value */
1011 tmpccmrx
= TIMx
->CCMR3
;
1013 /* Reset the Output Compare mode and Capture/Compare selection Bits */
1014 tmpccmrx
&= (uint32_t)~TIM_CCMR3_OC5M
;
1016 /* Select the Output Compare Mode */
1017 tmpccmrx
|= (uint32_t)(TIM_OCInitStruct
->TIM_OCMode
);
1019 /* Reset the Output Polarity level */
1020 tmpccer
&= (uint32_t)~TIM_CCER_CC5P
;
1021 /* Set the Output Compare Polarity */
1022 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCPolarity
<< 16);
1024 /* Set the Output State */
1025 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputState
<< 16);
1027 if((TIMx
== TIM1
) || (TIMx
== TIM8
))
1029 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct
->TIM_OCIdleState
));
1030 /* Reset the Output Compare IDLE State */
1031 tmpcr2
&=(uint32_t) ~TIM_CR2_OIS5
;
1032 /* Set the Output Idle state */
1033 tmpcr2
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCIdleState
<< 16);
1035 /* Write to TIMx CR2 */
1038 /* Write to TIMx CCMR2 */
1039 TIMx
->CCMR3
= tmpccmrx
;
1041 /* Set the Capture Compare Register value */
1042 TIMx
->CCR5
= TIM_OCInitStruct
->TIM_Pulse
;
1044 /* Write to TIMx CCER */
1045 TIMx
->CCER
= tmpccer
;
1049 * @brief Initializes the TIMx Channel6 according to the specified parameters
1050 * in the TIM_OCInitStruct.
1051 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1052 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
1053 * the configuration information for the specified TIM peripheral.
1056 void TIM_OC6Init(TIM_TypeDef
* TIMx
, TIM_OCInitTypeDef
* TIM_OCInitStruct
)
1058 uint32_t tmpccmrx
= 0, tmpccer
= 0, tmpcr2
= 0;
1060 /* Check the parameters */
1061 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1062 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct
->TIM_OCMode
));
1063 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct
->TIM_OutputState
));
1064 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct
->TIM_OCPolarity
));
1066 /* Disable the Channel 5: Reset the CC5E Bit */
1067 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC6E
; /* to be verified*/
1069 /* Get the TIMx CCER register value */
1070 tmpccer
= TIMx
->CCER
;
1071 /* Get the TIMx CR2 register value */
1074 /* Get the TIMx CCMR3 register value */
1075 tmpccmrx
= TIMx
->CCMR3
;
1077 /* Reset the Output Compare mode and Capture/Compare selection Bits */
1078 tmpccmrx
&= (uint32_t)~TIM_CCMR3_OC6M
;
1080 /* Select the Output Compare Mode */
1081 tmpccmrx
|= (uint32_t)(TIM_OCInitStruct
->TIM_OCMode
<< 8);
1083 /* Reset the Output Polarity level */
1084 tmpccer
&= (uint32_t)~TIM_CCER_CC6P
;
1085 /* Set the Output Compare Polarity */
1086 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OCPolarity
<< 20);
1088 /* Set the Output State */
1089 tmpccer
|= (uint32_t)((uint32_t)TIM_OCInitStruct
->TIM_OutputState
<< 20);
1091 if((TIMx
== TIM1
) || (TIMx
== TIM8
))
1093 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct
->TIM_OCIdleState
));
1094 /* Reset the Output Compare IDLE State */
1095 tmpcr2
&=(uint32_t) ~TIM_CR2_OIS6
;
1096 /* Set the Output Idle state */
1097 tmpcr2
|= (uint16_t)(TIM_OCInitStruct
->TIM_OCIdleState
<< 18);
1099 /* Write to TIMx CR2 */
1102 /* Write to TIMx CCMR2 */
1103 TIMx
->CCMR3
= tmpccmrx
;
1105 /* Set the Capture Compare Register value */
1106 TIMx
->CCR6
= TIM_OCInitStruct
->TIM_Pulse
;
1108 /* Write to TIMx CCER */
1109 TIMx
->CCER
= tmpccer
;
1113 * @brief Selects the TIM Group Channel 5 and Channel 1,
1114 OC1REFC is the logical AND of OC1REFC and OC5REF.
1115 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
1116 * @param NewState: new state of the Commutation event.
1117 * This parameter can be: ENABLE or DISABLE.
1120 void TIM_SelectGC5C1(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
1122 /* Check the parameters */
1123 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1124 assert_param(IS_FUNCTIONAL_STATE(NewState
));
1126 if (NewState
!= DISABLE
)
1128 /* Set the GC5C1 Bit */
1129 TIMx
->CCR5
|= TIM_CCR5_GC5C1
;
1133 /* Reset the GC5C1 Bit */
1134 TIMx
->CCR5
&= (uint32_t)~TIM_CCR5_GC5C1
;
1139 * @brief Selects the TIM Group Channel 5 and Channel 2,
1140 OC2REFC is the logical AND of OC2REFC and OC5REF.
1141 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
1142 * @param NewState: new state of the Commutation event.
1143 * This parameter can be: ENABLE or DISABLE.
1146 void TIM_SelectGC5C2(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
1148 /* Check the parameters */
1149 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1150 assert_param(IS_FUNCTIONAL_STATE(NewState
));
1152 if (NewState
!= DISABLE
)
1154 /* Set the GC5C2 Bit */
1155 TIMx
->CCR5
|= TIM_CCR5_GC5C2
;
1159 /* Reset the GC5C2 Bit */
1160 TIMx
->CCR5
&= (uint32_t)~TIM_CCR5_GC5C2
;
1166 * @brief Selects the TIM Group Channel 5 and Channel 3,
1167 OC3REFC is the logical AND of OC3REFC and OC5REF.
1168 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
1169 * @param NewState: new state of the Commutation event.
1170 * This parameter can be: ENABLE or DISABLE.
1173 void TIM_SelectGC5C3(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
1175 /* Check the parameters */
1176 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1177 assert_param(IS_FUNCTIONAL_STATE(NewState
));
1179 if (NewState
!= DISABLE
)
1181 /* Set the GC5C3 Bit */
1182 TIMx
->CCR5
|= TIM_CCR5_GC5C3
;
1186 /* Reset the GC5C3 Bit */
1187 TIMx
->CCR5
&= (uint32_t)~TIM_CCR5_GC5C3
;
1192 * @brief Fills each TIM_OCInitStruct member with its default value.
1193 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
1197 void TIM_OCStructInit(TIM_OCInitTypeDef
* TIM_OCInitStruct
)
1199 /* Set the default configuration */
1200 TIM_OCInitStruct
->TIM_OCMode
= TIM_OCMode_Timing
;
1201 TIM_OCInitStruct
->TIM_OutputState
= TIM_OutputState_Disable
;
1202 TIM_OCInitStruct
->TIM_OutputNState
= TIM_OutputNState_Disable
;
1203 TIM_OCInitStruct
->TIM_Pulse
= 0x00000000;
1204 TIM_OCInitStruct
->TIM_OCPolarity
= TIM_OCPolarity_High
;
1205 TIM_OCInitStruct
->TIM_OCNPolarity
= TIM_OCPolarity_High
;
1206 TIM_OCInitStruct
->TIM_OCIdleState
= TIM_OCIdleState_Reset
;
1207 TIM_OCInitStruct
->TIM_OCNIdleState
= TIM_OCNIdleState_Reset
;
1211 * @brief Selects the TIM Output Compare Mode.
1212 * @note This function disables the selected channel before changing the Output
1213 * Compare Mode. If needed, user has to enable this channel using
1214 * TIM_CCxCmd() and TIM_CCxNCmd() functions.
1215 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
1216 * @param TIM_Channel: specifies the TIM Channel
1217 * This parameter can be one of the following values:
1218 * @arg TIM_Channel_1: TIM Channel 1
1219 * @arg TIM_Channel_2: TIM Channel 2
1220 * @arg TIM_Channel_3: TIM Channel 3
1221 * @arg TIM_Channel_4: TIM Channel 4
1222 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
1223 * This parameter can be one of the following values:
1224 * @arg TIM_OCMode_Timing
1225 * @arg TIM_OCMode_Active
1226 * @arg TIM_OCMode_Toggle
1227 * @arg TIM_OCMode_PWM1
1228 * @arg TIM_OCMode_PWM2
1229 * @arg TIM_ForcedAction_Active
1230 * @arg TIM_ForcedAction_InActive
1231 * @arg TIM_OCMode_Retrigerrable_OPM1
1232 * @arg TIM_OCMode_Retrigerrable_OPM2
1233 * @arg TIM_OCMode_Combined_PWM1
1234 * @arg TIM_OCMode_Combined_PWM2
1235 * @arg TIM_OCMode_Asymmetric_PWM1
1236 * @arg TIM_OCMode_Asymmetric_PWM2
1239 void TIM_SelectOCxM(TIM_TypeDef
* TIMx
, uint16_t TIM_Channel
, uint32_t TIM_OCMode
)
1244 /* Check the parameters */
1245 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
1246 assert_param(IS_TIM_CHANNEL(TIM_Channel
));
1247 assert_param(IS_TIM_OCM(TIM_OCMode
));
1249 tmp
= (uint32_t) TIMx
;
1252 tmp1
= CCER_CCE_SET
<< (uint16_t)TIM_Channel
;
1254 /* Disable the Channel: Reset the CCxE Bit */
1255 TIMx
->CCER
&= (uint16_t) ~tmp1
;
1257 if((TIM_Channel
== TIM_Channel_1
) ||(TIM_Channel
== TIM_Channel_3
))
1259 tmp
+= (TIM_Channel
>>1);
1261 /* Reset the OCxM bits in the CCMRx register */
1262 *(__IO
uint32_t *) tmp
&= CCMR_OC13M_MASK
;
1264 /* Configure the OCxM bits in the CCMRx register */
1265 *(__IO
uint32_t *) tmp
|= TIM_OCMode
;
1269 tmp
+= (uint32_t)(TIM_Channel
- (uint32_t)4)>> (uint32_t)1;
1271 /* Reset the OCxM bits in the CCMRx register */
1272 *(__IO
uint32_t *) tmp
&= CCMR_OC24M_MASK
;
1274 /* Configure the OCxM bits in the CCMRx register */
1275 *(__IO
uint32_t *) tmp
|= (uint32_t)(TIM_OCMode
<< 8);
1280 * @brief Sets the TIMx Capture Compare1 Register value
1281 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
1282 * @param Compare1: specifies the Capture Compare1 register new value.
1285 void TIM_SetCompare1(TIM_TypeDef
* TIMx
, uint32_t Compare1
)
1287 /* Check the parameters */
1288 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
1290 /* Set the Capture Compare1 Register value */
1291 TIMx
->CCR1
= Compare1
;
1295 * @brief Sets the TIMx Capture Compare2 Register value
1296 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
1298 * @param Compare2: specifies the Capture Compare2 register new value.
1301 void TIM_SetCompare2(TIM_TypeDef
* TIMx
, uint32_t Compare2
)
1303 /* Check the parameters */
1304 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
1306 /* Set the Capture Compare2 Register value */
1307 TIMx
->CCR2
= Compare2
;
1311 * @brief Sets the TIMx Capture Compare3 Register value
1312 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1313 * @param Compare3: specifies the Capture Compare3 register new value.
1316 void TIM_SetCompare3(TIM_TypeDef
* TIMx
, uint32_t Compare3
)
1318 /* Check the parameters */
1319 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1321 /* Set the Capture Compare3 Register value */
1322 TIMx
->CCR3
= Compare3
;
1326 * @brief Sets the TIMx Capture Compare4 Register value
1327 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1328 * @param Compare4: specifies the Capture Compare4 register new value.
1331 void TIM_SetCompare4(TIM_TypeDef
* TIMx
, uint32_t Compare4
)
1333 /* Check the parameters */
1334 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1336 /* Set the Capture Compare4 Register value */
1337 TIMx
->CCR4
= Compare4
;
1341 * @brief Sets the TIMx Capture Compare5 Register value
1342 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1343 * @param Compare5: specifies the Capture Compare5 register new value.
1346 void TIM_SetCompare5(TIM_TypeDef
* TIMx
, uint32_t Compare5
)
1348 /* Check the parameters */
1349 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1351 /* Set the Capture Compare5 Register value */
1352 TIMx
->CCR5
= Compare5
;
1356 * @brief Sets the TIMx Capture Compare6 Register value
1357 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1358 * @param Compare6: specifies the Capture Compare5 register new value.
1361 void TIM_SetCompare6(TIM_TypeDef
* TIMx
, uint32_t Compare6
)
1363 /* Check the parameters */
1364 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1366 /* Set the Capture Compare6 Register value */
1367 TIMx
->CCR6
= Compare6
;
1371 * @brief Forces the TIMx output 1 waveform to active or inactive level.
1372 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
1373 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1374 * This parameter can be one of the following values:
1375 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
1376 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
1379 void TIM_ForcedOC1Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ForcedAction
)
1381 uint32_t tmpccmr1
= 0;
1383 /* Check the parameters */
1384 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
1385 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction
));
1386 tmpccmr1
= TIMx
->CCMR1
;
1388 /* Reset the OC1M Bits */
1389 tmpccmr1
&= (uint32_t)~TIM_CCMR1_OC1M
;
1391 /* Configure The Forced output Mode */
1392 tmpccmr1
|= TIM_ForcedAction
;
1394 /* Write to TIMx CCMR1 register */
1395 TIMx
->CCMR1
= tmpccmr1
;
1399 * @brief Forces the TIMx output 2 waveform to active or inactive level.
1400 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
1402 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1403 * This parameter can be one of the following values:
1404 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
1405 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
1408 void TIM_ForcedOC2Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ForcedAction
)
1410 uint32_t tmpccmr1
= 0;
1412 /* Check the parameters */
1413 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
1414 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction
));
1415 tmpccmr1
= TIMx
->CCMR1
;
1417 /* Reset the OC2M Bits */
1418 tmpccmr1
&= (uint32_t)~TIM_CCMR1_OC2M
;
1420 /* Configure The Forced output Mode */
1421 tmpccmr1
|= ((uint32_t)TIM_ForcedAction
<< 8);
1423 /* Write to TIMx CCMR1 register */
1424 TIMx
->CCMR1
= tmpccmr1
;
1428 * @brief Forces the TIMx output 3 waveform to active or inactive level.
1429 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1430 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1431 * This parameter can be one of the following values:
1432 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
1433 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
1436 void TIM_ForcedOC3Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ForcedAction
)
1438 uint32_t tmpccmr2
= 0;
1440 /* Check the parameters */
1441 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1442 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction
));
1444 tmpccmr2
= TIMx
->CCMR2
;
1446 /* Reset the OC1M Bits */
1447 tmpccmr2
&= (uint32_t)~TIM_CCMR2_OC3M
;
1449 /* Configure The Forced output Mode */
1450 tmpccmr2
|= TIM_ForcedAction
;
1452 /* Write to TIMx CCMR2 register */
1453 TIMx
->CCMR2
= tmpccmr2
;
1457 * @brief Forces the TIMx output 4 waveform to active or inactive level.
1458 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1459 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1460 * This parameter can be one of the following values:
1461 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
1462 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
1465 void TIM_ForcedOC4Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ForcedAction
)
1467 uint32_t tmpccmr2
= 0;
1469 /* Check the parameters */
1470 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1471 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction
));
1472 tmpccmr2
= TIMx
->CCMR2
;
1474 /* Reset the OC2M Bits */
1475 tmpccmr2
&= (uint32_t)~TIM_CCMR2_OC4M
;
1477 /* Configure The Forced output Mode */
1478 tmpccmr2
|= ((uint32_t)TIM_ForcedAction
<< 8);
1480 /* Write to TIMx CCMR2 register */
1481 TIMx
->CCMR2
= tmpccmr2
;
1485 * @brief Forces the TIMx output 5 waveform to active or inactive level.
1486 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1487 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1488 * This parameter can be one of the following values:
1489 * @arg TIM_ForcedAction_Active: Force active level on OC5REF
1490 * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
1493 void TIM_ForcedOC5Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ForcedAction
)
1495 uint32_t tmpccmr3
= 0;
1497 /* Check the parameters */
1498 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1499 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction
));
1500 tmpccmr3
= TIMx
->CCMR3
;
1502 /* Reset the OC5M Bits */
1503 tmpccmr3
&= (uint32_t)~TIM_CCMR3_OC5M
;
1505 /* Configure The Forced output Mode */
1506 tmpccmr3
|= (uint32_t)(TIM_ForcedAction
);
1508 /* Write to TIMx CCMR3 register */
1509 TIMx
->CCMR3
= tmpccmr3
;
1513 * @brief Forces the TIMx output 6 waveform to active or inactive level.
1514 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1515 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1516 * This parameter can be one of the following values:
1517 * @arg TIM_ForcedAction_Active: Force active level on OC5REF
1518 * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
1521 void TIM_ForcedOC6Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ForcedAction
)
1523 uint32_t tmpccmr3
= 0;
1525 /* Check the parameters */
1526 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1527 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction
));
1528 tmpccmr3
= TIMx
->CCMR3
;
1530 /* Reset the OC6M Bits */
1531 tmpccmr3
&= (uint32_t)~TIM_CCMR3_OC6M
;
1533 /* Configure The Forced output Mode */
1534 tmpccmr3
|= ((uint32_t)TIM_ForcedAction
<< 8);
1536 /* Write to TIMx CCMR3 register */
1537 TIMx
->CCMR3
= tmpccmr3
;
1541 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
1542 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
1543 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1544 * This parameter can be one of the following values:
1545 * @arg TIM_OCPreload_Enable
1546 * @arg TIM_OCPreload_Disable
1549 void TIM_OC1PreloadConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPreload
)
1551 uint32_t tmpccmr1
= 0;
1553 /* Check the parameters */
1554 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
1555 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload
));
1557 tmpccmr1
= TIMx
->CCMR1
;
1559 /* Reset the OC1PE Bit */
1560 tmpccmr1
&= (uint32_t)(~TIM_CCMR1_OC1PE
);
1562 /* Enable or Disable the Output Compare Preload feature */
1563 tmpccmr1
|= TIM_OCPreload
;
1565 /* Write to TIMx CCMR1 register */
1566 TIMx
->CCMR1
= tmpccmr1
;
1570 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
1571 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
1573 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1574 * This parameter can be one of the following values:
1575 * @arg TIM_OCPreload_Enable
1576 * @arg TIM_OCPreload_Disable
1579 void TIM_OC2PreloadConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPreload
)
1581 uint32_t tmpccmr1
= 0;
1583 /* Check the parameters */
1584 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
1585 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload
));
1587 tmpccmr1
= TIMx
->CCMR1
;
1589 /* Reset the OC2PE Bit */
1590 tmpccmr1
&= (uint32_t)(~TIM_CCMR1_OC2PE
);
1592 /* Enable or Disable the Output Compare Preload feature */
1593 tmpccmr1
|= ((uint32_t)TIM_OCPreload
<< 8);
1595 /* Write to TIMx CCMR1 register */
1596 TIMx
->CCMR1
= tmpccmr1
;
1600 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
1601 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1602 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1603 * This parameter can be one of the following values:
1604 * @arg TIM_OCPreload_Enable
1605 * @arg TIM_OCPreload_Disable
1608 void TIM_OC3PreloadConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPreload
)
1610 uint32_t tmpccmr2
= 0;
1612 /* Check the parameters */
1613 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1614 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload
));
1616 tmpccmr2
= TIMx
->CCMR2
;
1618 /* Reset the OC3PE Bit */
1619 tmpccmr2
&= (uint32_t)(~TIM_CCMR2_OC3PE
);
1621 /* Enable or Disable the Output Compare Preload feature */
1622 tmpccmr2
|= TIM_OCPreload
;
1624 /* Write to TIMx CCMR2 register */
1625 TIMx
->CCMR2
= tmpccmr2
;
1629 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
1630 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1631 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1632 * This parameter can be one of the following values:
1633 * @arg TIM_OCPreload_Enable
1634 * @arg TIM_OCPreload_Disable
1637 void TIM_OC4PreloadConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPreload
)
1639 uint32_t tmpccmr2
= 0;
1641 /* Check the parameters */
1642 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1643 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload
));
1645 tmpccmr2
= TIMx
->CCMR2
;
1647 /* Reset the OC4PE Bit */
1648 tmpccmr2
&= (uint32_t)(~TIM_CCMR2_OC4PE
);
1650 /* Enable or Disable the Output Compare Preload feature */
1651 tmpccmr2
|= ((uint32_t)TIM_OCPreload
<< 8);
1653 /* Write to TIMx CCMR2 register */
1654 TIMx
->CCMR2
= tmpccmr2
;
1658 * @brief Enables or disables the TIMx peripheral Preload register on CCR5.
1659 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1660 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1661 * This parameter can be one of the following values:
1662 * @arg TIM_OCPreload_Enable
1663 * @arg TIM_OCPreload_Disable
1666 void TIM_OC5PreloadConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPreload
)
1668 uint32_t tmpccmr3
= 0;
1670 /* Check the parameters */
1671 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1672 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload
));
1674 tmpccmr3
= TIMx
->CCMR3
;
1676 /* Reset the OC5PE Bit */
1677 tmpccmr3
&= (uint32_t)(~TIM_CCMR3_OC5PE
);
1679 /* Enable or Disable the Output Compare Preload feature */
1680 tmpccmr3
|= (uint32_t)(TIM_OCPreload
);
1682 /* Write to TIMx CCMR3 register */
1683 TIMx
->CCMR3
= tmpccmr3
;
1687 * @brief Enables or disables the TIMx peripheral Preload register on CCR6.
1688 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1689 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1690 * This parameter can be one of the following values:
1691 * @arg TIM_OCPreload_Enable
1692 * @arg TIM_OCPreload_Disable
1695 void TIM_OC6PreloadConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPreload
)
1697 uint32_t tmpccmr3
= 0;
1699 /* Check the parameters */
1700 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1701 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload
));
1703 tmpccmr3
= TIMx
->CCMR3
;
1705 /* Reset the OC5PE Bit */
1706 tmpccmr3
&= (uint32_t)(~TIM_CCMR3_OC6PE
);
1708 /* Enable or Disable the Output Compare Preload feature */
1709 tmpccmr3
|= ((uint32_t)TIM_OCPreload
<< 8);
1711 /* Write to TIMx CCMR3 register */
1712 TIMx
->CCMR3
= tmpccmr3
;
1716 * @brief Configures the TIMx Output Compare 1 Fast feature.
1717 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
1718 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1719 * This parameter can be one of the following values:
1720 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1721 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1724 void TIM_OC1FastConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCFast
)
1726 uint32_t tmpccmr1
= 0;
1728 /* Check the parameters */
1729 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
1730 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast
));
1732 /* Get the TIMx CCMR1 register value */
1733 tmpccmr1
= TIMx
->CCMR1
;
1735 /* Reset the OC1FE Bit */
1736 tmpccmr1
&= (uint32_t)~TIM_CCMR1_OC1FE
;
1738 /* Enable or Disable the Output Compare Fast Bit */
1739 tmpccmr1
|= TIM_OCFast
;
1741 /* Write to TIMx CCMR1 */
1742 TIMx
->CCMR1
= tmpccmr1
;
1746 * @brief Configures the TIMx Output Compare 2 Fast feature.
1747 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
1749 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1750 * This parameter can be one of the following values:
1751 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1752 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1755 void TIM_OC2FastConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCFast
)
1757 uint32_t tmpccmr1
= 0;
1759 /* Check the parameters */
1760 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
1761 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast
));
1763 /* Get the TIMx CCMR1 register value */
1764 tmpccmr1
= TIMx
->CCMR1
;
1766 /* Reset the OC2FE Bit */
1767 tmpccmr1
&= (uint32_t)(~TIM_CCMR1_OC2FE
);
1769 /* Enable or Disable the Output Compare Fast Bit */
1770 tmpccmr1
|= ((uint32_t)TIM_OCFast
<< 8);
1772 /* Write to TIMx CCMR1 */
1773 TIMx
->CCMR1
= tmpccmr1
;
1777 * @brief Configures the TIMx Output Compare 3 Fast feature.
1778 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1779 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1780 * This parameter can be one of the following values:
1781 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1782 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1785 void TIM_OC3FastConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCFast
)
1787 uint32_t tmpccmr2
= 0;
1789 /* Check the parameters */
1790 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1791 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast
));
1793 /* Get the TIMx CCMR2 register value */
1794 tmpccmr2
= TIMx
->CCMR2
;
1796 /* Reset the OC3FE Bit */
1797 tmpccmr2
&= (uint32_t)~TIM_CCMR2_OC3FE
;
1799 /* Enable or Disable the Output Compare Fast Bit */
1800 tmpccmr2
|= TIM_OCFast
;
1802 /* Write to TIMx CCMR2 */
1803 TIMx
->CCMR2
= tmpccmr2
;
1807 * @brief Configures the TIMx Output Compare 4 Fast feature.
1808 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1809 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1810 * This parameter can be one of the following values:
1811 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1812 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1815 void TIM_OC4FastConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCFast
)
1817 uint32_t tmpccmr2
= 0;
1819 /* Check the parameters */
1820 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1821 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast
));
1823 /* Get the TIMx CCMR2 register value */
1824 tmpccmr2
= TIMx
->CCMR2
;
1826 /* Reset the OC4FE Bit */
1827 tmpccmr2
&= (uint32_t)(~TIM_CCMR2_OC4FE
);
1829 /* Enable or Disable the Output Compare Fast Bit */
1830 tmpccmr2
|= ((uint32_t)TIM_OCFast
<< 8);
1832 /* Write to TIMx CCMR2 */
1833 TIMx
->CCMR2
= tmpccmr2
;
1837 * @brief Clears or safeguards the OCREF1 signal on an external event
1838 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
1839 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1840 * This parameter can be one of the following values:
1841 * @arg TIM_OCClear_Enable: TIM Output clear enable
1842 * @arg TIM_OCClear_Disable: TIM Output clear disable
1845 void TIM_ClearOC1Ref(TIM_TypeDef
* TIMx
, uint16_t TIM_OCClear
)
1847 uint32_t tmpccmr1
= 0;
1849 /* Check the parameters */
1850 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
1851 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear
));
1853 tmpccmr1
= TIMx
->CCMR1
;
1855 /* Reset the OC1CE Bit */
1856 tmpccmr1
&= (uint32_t)~TIM_CCMR1_OC1CE
;
1858 /* Enable or Disable the Output Compare Clear Bit */
1859 tmpccmr1
|= TIM_OCClear
;
1861 /* Write to TIMx CCMR1 register */
1862 TIMx
->CCMR1
= tmpccmr1
;
1866 * @brief Clears or safeguards the OCREF2 signal on an external event
1867 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
1869 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1870 * This parameter can be one of the following values:
1871 * @arg TIM_OCClear_Enable: TIM Output clear enable
1872 * @arg TIM_OCClear_Disable: TIM Output clear disable
1875 void TIM_ClearOC2Ref(TIM_TypeDef
* TIMx
, uint16_t TIM_OCClear
)
1877 uint32_t tmpccmr1
= 0;
1879 /* Check the parameters */
1880 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
1881 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear
));
1883 tmpccmr1
= TIMx
->CCMR1
;
1885 /* Reset the OC2CE Bit */
1886 tmpccmr1
&= (uint32_t)~TIM_CCMR1_OC2CE
;
1888 /* Enable or Disable the Output Compare Clear Bit */
1889 tmpccmr1
|= ((uint32_t)TIM_OCClear
<< 8);
1891 /* Write to TIMx CCMR1 register */
1892 TIMx
->CCMR1
= tmpccmr1
;
1896 * @brief Clears or safeguards the OCREF3 signal on an external event
1897 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1898 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1899 * This parameter can be one of the following values:
1900 * @arg TIM_OCClear_Enable: TIM Output clear enable
1901 * @arg TIM_OCClear_Disable: TIM Output clear disable
1904 void TIM_ClearOC3Ref(TIM_TypeDef
* TIMx
, uint16_t TIM_OCClear
)
1906 uint32_t tmpccmr2
= 0;
1908 /* Check the parameters */
1909 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1910 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear
));
1912 tmpccmr2
= TIMx
->CCMR2
;
1914 /* Reset the OC3CE Bit */
1915 tmpccmr2
&= (uint32_t)~TIM_CCMR2_OC3CE
;
1917 /* Enable or Disable the Output Compare Clear Bit */
1918 tmpccmr2
|= TIM_OCClear
;
1920 /* Write to TIMx CCMR2 register */
1921 TIMx
->CCMR2
= tmpccmr2
;
1925 * @brief Clears or safeguards the OCREF4 signal on an external event
1926 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
1927 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1928 * This parameter can be one of the following values:
1929 * @arg TIM_OCClear_Enable: TIM Output clear enable
1930 * @arg TIM_OCClear_Disable: TIM Output clear disable
1933 void TIM_ClearOC4Ref(TIM_TypeDef
* TIMx
, uint16_t TIM_OCClear
)
1935 uint32_t tmpccmr2
= 0;
1937 /* Check the parameters */
1938 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
1939 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear
));
1941 tmpccmr2
= TIMx
->CCMR2
;
1943 /* Reset the OC4CE Bit */
1944 tmpccmr2
&= (uint32_t)~TIM_CCMR2_OC4CE
;
1946 /* Enable or Disable the Output Compare Clear Bit */
1947 tmpccmr2
|= ((uint32_t)TIM_OCClear
<< 8);
1949 /* Write to TIMx CCMR2 register */
1950 TIMx
->CCMR2
= tmpccmr2
;
1954 * @brief Clears or safeguards the OCREF5 signal on an external event
1955 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1956 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1957 * This parameter can be one of the following values:
1958 * @arg TIM_OCClear_Enable: TIM Output clear enable
1959 * @arg TIM_OCClear_Disable: TIM Output clear disable
1962 void TIM_ClearOC5Ref(TIM_TypeDef
* TIMx
, uint16_t TIM_OCClear
)
1964 uint32_t tmpccmr3
= 0;
1966 /* Check the parameters */
1967 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1968 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear
));
1970 tmpccmr3
= TIMx
->CCMR3
;
1972 /* Reset the OC5CE Bit */
1973 tmpccmr3
&= (uint32_t)~TIM_CCMR3_OC5CE
;
1975 /* Enable or Disable the Output Compare Clear Bit */
1976 tmpccmr3
|= (uint32_t)(TIM_OCClear
);
1978 /* Write to TIMx CCMR3 register */
1979 TIMx
->CCMR3
= tmpccmr3
;
1983 * @brief Clears or safeguards the OCREF6 signal on an external event
1984 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1985 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1986 * This parameter can be one of the following values:
1987 * @arg TIM_OCClear_Enable: TIM Output clear enable
1988 * @arg TIM_OCClear_Disable: TIM Output clear disable
1991 void TIM_ClearOC6Ref(TIM_TypeDef
* TIMx
, uint16_t TIM_OCClear
)
1993 uint32_t tmpccmr3
= 0;
1995 /* Check the parameters */
1996 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
1997 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear
));
1999 tmpccmr3
= TIMx
->CCMR3
;
2001 /* Reset the OC5CE Bit */
2002 tmpccmr3
&= (uint32_t)~TIM_CCMR3_OC6CE
;
2004 /* Enable or Disable the Output Compare Clear Bit */
2005 tmpccmr3
|= ((uint32_t)TIM_OCClear
<< 8);
2007 /* Write to TIMx CCMR3 register */
2008 TIMx
->CCMR3
= tmpccmr3
;
2012 * @brief Selects the OCReference Clear source.
2013 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
2014 * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
2015 * This parameter can be one of the following values:
2016 * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
2017 * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
2020 void TIM_SelectOCREFClear(TIM_TypeDef
* TIMx
, uint16_t TIM_OCReferenceClear
)
2022 /* Check the parameters */
2023 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
2024 assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear
));
2026 /* Set the TIM_OCReferenceClear source */
2027 TIMx
->SMCR
&= (uint16_t)~((uint16_t)TIM_SMCR_OCCS
);
2028 TIMx
->SMCR
|= TIM_OCReferenceClear
;
2032 * @brief Configures the TIMx channel 1 polarity.
2033 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
2034 * @param TIM_OCPolarity: specifies the OC1 Polarity
2035 * This parameter can be one of the following values:
2036 * @arg TIM_OCPolarity_High: Output Compare active high
2037 * @arg TIM_OCPolarity_Low: Output Compare active low
2040 void TIM_OC1PolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPolarity
)
2042 uint32_t tmpccer
= 0;
2044 /* Check the parameters */
2045 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
2046 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity
));
2048 tmpccer
= TIMx
->CCER
;
2050 /* Set or Reset the CC1P Bit */
2051 tmpccer
&= (uint32_t)(~TIM_CCER_CC1P
);
2052 tmpccer
|= TIM_OCPolarity
;
2054 /* Write to TIMx CCER register */
2055 TIMx
->CCER
= tmpccer
;
2059 * @brief Configures the TIMx Channel 1N polarity.
2060 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
2061 * @param TIM_OCNPolarity: specifies the OC1N Polarity
2062 * This parameter can be one of the following values:
2063 * @arg TIM_OCNPolarity_High: Output Compare active high
2064 * @arg TIM_OCNPolarity_Low: Output Compare active low
2067 void TIM_OC1NPolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCNPolarity
)
2069 uint32_t tmpccer
= 0;
2070 /* Check the parameters */
2071 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2072 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity
));
2074 tmpccer
= TIMx
->CCER
;
2076 /* Set or Reset the CC1NP Bit */
2077 tmpccer
&= (uint32_t)~TIM_CCER_CC1NP
;
2078 tmpccer
|= TIM_OCNPolarity
;
2080 /* Write to TIMx CCER register */
2081 TIMx
->CCER
= tmpccer
;
2085 * @brief Configures the TIMx channel 2 polarity.
2086 * @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM
2088 * @param TIM_OCPolarity: specifies the OC2 Polarity
2089 * This parameter can be one of the following values:
2090 * @arg TIM_OCPolarity_High: Output Compare active high
2091 * @arg TIM_OCPolarity_Low: Output Compare active low
2094 void TIM_OC2PolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPolarity
)
2096 uint32_t tmpccer
= 0;
2098 /* Check the parameters */
2099 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
2100 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity
));
2102 tmpccer
= TIMx
->CCER
;
2104 /* Set or Reset the CC2P Bit */
2105 tmpccer
&= (uint32_t)(~TIM_CCER_CC2P
);
2106 tmpccer
|= ((uint32_t)TIM_OCPolarity
<< 4);
2108 /* Write to TIMx CCER register */
2109 TIMx
->CCER
= tmpccer
;
2113 * @brief Configures the TIMx Channel 2N polarity.
2114 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
2115 * @param TIM_OCNPolarity: specifies the OC2N Polarity
2116 * This parameter can be one of the following values:
2117 * @arg TIM_OCNPolarity_High: Output Compare active high
2118 * @arg TIM_OCNPolarity_Low: Output Compare active low
2121 void TIM_OC2NPolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCNPolarity
)
2123 uint32_t tmpccer
= 0;
2125 /* Check the parameters */
2126 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2127 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity
));
2129 tmpccer
= TIMx
->CCER
;
2131 /* Set or Reset the CC2NP Bit */
2132 tmpccer
&= (uint32_t)~TIM_CCER_CC2NP
;
2133 tmpccer
|= ((uint32_t)TIM_OCNPolarity
<< 4);
2135 /* Write to TIMx CCER register */
2136 TIMx
->CCER
= tmpccer
;
2140 * @brief Configures the TIMx channel 3 polarity.
2141 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
2142 * @param TIM_OCPolarity: specifies the OC3 Polarity
2143 * This parameter can be one of the following values:
2144 * @arg TIM_OCPolarity_High: Output Compare active high
2145 * @arg TIM_OCPolarity_Low: Output Compare active low
2148 void TIM_OC3PolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPolarity
)
2150 uint32_t tmpccer
= 0;
2152 /* Check the parameters */
2153 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
2154 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity
));
2156 tmpccer
= TIMx
->CCER
;
2158 /* Set or Reset the CC3P Bit */
2159 tmpccer
&= (uint32_t)~TIM_CCER_CC3P
;
2160 tmpccer
|= ((uint32_t)TIM_OCPolarity
<< 8);
2162 /* Write to TIMx CCER register */
2163 TIMx
->CCER
= tmpccer
;
2167 * @brief Configures the TIMx Channel 3N polarity.
2168 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
2169 * @param TIM_OCNPolarity: specifies the OC3N Polarity
2170 * This parameter can be one of the following values:
2171 * @arg TIM_OCNPolarity_High: Output Compare active high
2172 * @arg TIM_OCNPolarity_Low: Output Compare active low
2175 void TIM_OC3NPolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCNPolarity
)
2177 uint32_t tmpccer
= 0;
2179 /* Check the parameters */
2180 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2181 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity
));
2183 tmpccer
= TIMx
->CCER
;
2185 /* Set or Reset the CC3NP Bit */
2186 tmpccer
&= (uint32_t)~TIM_CCER_CC3NP
;
2187 tmpccer
|= ((uint32_t)TIM_OCNPolarity
<< 8);
2189 /* Write to TIMx CCER register */
2190 TIMx
->CCER
= tmpccer
;
2194 * @brief Configures the TIMx channel 4 polarity.
2195 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
2196 * @param TIM_OCPolarity: specifies the OC4 Polarity
2197 * This parameter can be one of the following values:
2198 * @arg TIM_OCPolarity_High: Output Compare active high
2199 * @arg TIM_OCPolarity_Low: Output Compare active low
2202 void TIM_OC4PolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPolarity
)
2204 uint32_t tmpccer
= 0;
2206 /* Check the parameters */
2207 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
2208 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity
));
2210 tmpccer
= TIMx
->CCER
;
2212 /* Set or Reset the CC4P Bit */
2213 tmpccer
&= (uint32_t)~TIM_CCER_CC4P
;
2214 tmpccer
|= ((uint32_t)TIM_OCPolarity
<< 12);
2216 /* Write to TIMx CCER register */
2217 TIMx
->CCER
= tmpccer
;
2221 * @brief Configures the TIMx channel 5 polarity.
2222 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
2223 * @param TIM_OCPolarity: specifies the OC5 Polarity
2224 * This parameter can be one of the following values:
2225 * @arg TIM_OCPolarity_High: Output Compare active high
2226 * @arg TIM_OCPolarity_Low: Output Compare active low
2229 void TIM_OC5PolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPolarity
)
2231 uint32_t tmpccer
= 0;
2233 /* Check the parameters */
2234 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2235 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity
));
2237 tmpccer
= TIMx
->CCER
;
2239 /* Set or Reset the CC5P Bit */
2240 tmpccer
&= (uint32_t)~TIM_CCER_CC5P
;
2241 tmpccer
|= ((uint32_t)TIM_OCPolarity
<< 16);
2243 /* Write to TIMx CCER register */
2244 TIMx
->CCER
= tmpccer
;
2248 * @brief Configures the TIMx channel 6 polarity.
2249 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
2250 * @param TIM_OCPolarity: specifies the OC6 Polarity
2251 * This parameter can be one of the following values:
2252 * @arg TIM_OCPolarity_High: Output Compare active high
2253 * @arg TIM_OCPolarity_Low: Output Compare active low
2256 void TIM_OC6PolarityConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_OCPolarity
)
2258 uint32_t tmpccer
= 0;
2260 /* Check the parameters */
2261 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2262 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity
));
2264 tmpccer
= TIMx
->CCER
;
2266 /* Set or Reset the CC6P Bit */
2267 tmpccer
&= (uint32_t)~TIM_CCER_CC6P
;
2268 tmpccer
|= ((uint32_t)TIM_OCPolarity
<< 20);
2270 /* Write to TIMx CCER register */
2271 TIMx
->CCER
= tmpccer
;
2275 * @brief Enables or disables the TIM Capture Compare Channel x.
2276 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
2277 * @param TIM_Channel: specifies the TIM Channel
2278 * This parameter can be one of the following values:
2279 * @arg TIM_Channel_1: TIM Channel 1
2280 * @arg TIM_Channel_2: TIM Channel 2
2281 * @arg TIM_Channel_3: TIM Channel 3
2282 * @arg TIM_Channel_4: TIM Channel 4
2283 * @arg TIM_Channel_5: TIM Channel 5
2284 * @arg TIM_Channel_6: TIM Channel 6
2285 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
2286 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
2289 void TIM_CCxCmd(TIM_TypeDef
* TIMx
, uint16_t TIM_Channel
, uint16_t TIM_CCx
)
2293 /* Check the parameters */
2294 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
2295 assert_param(IS_TIM_CHANNEL(TIM_Channel
));
2296 assert_param(IS_TIM_CCX(TIM_CCx
));
2298 tmp
= (uint32_t)CCER_CCE_SET
<< (uint32_t)TIM_Channel
;
2300 /* Reset the CCxE Bit */
2301 TIMx
->CCER
&= (uint32_t)(~tmp
);
2303 /* Set or reset the CCxE Bit */
2304 TIMx
->CCER
|= ((uint32_t)TIM_CCx
<< (uint32_t)TIM_Channel
);
2308 * @brief Enables or disables the TIM Capture Compare Channel xN.
2309 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
2310 * @param TIM_Channel: specifies the TIM Channel
2311 * This parameter can be one of the following values:
2312 * @arg TIM_Channel_1: TIM Channel 1
2313 * @arg TIM_Channel_2: TIM Channel 2
2314 * @arg TIM_Channel_3: TIM Channel 3
2315 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
2316 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
2319 void TIM_CCxNCmd(TIM_TypeDef
* TIMx
, uint16_t TIM_Channel
, uint16_t TIM_CCxN
)
2323 /* Check the parameters */
2324 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2325 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel
));
2326 assert_param(IS_TIM_CCXN(TIM_CCxN
));
2328 tmp
= (uint32_t)CCER_CCNE_SET
<< (uint32_t)TIM_Channel
;
2330 /* Reset the CCxNE Bit */
2331 TIMx
->CCER
&= (uint32_t) ~tmp
;
2333 /* Set or reset the CCxNE Bit */
2334 TIMx
->CCER
|= ((uint32_t)TIM_CCxN
<< (uint32_t)TIM_Channel
);
2340 /** @defgroup TIM_Group3 Input Capture management functions
2341 * @brief Input Capture management functions
2344 ===============================================================================
2345 ##### Input Capture management functions #####
2346 ===============================================================================
2348 *** TIM Driver: how to use it in Input Capture Mode ***
2349 =======================================================
2351 To use the Timer in Input Capture mode, the following steps are mandatory:
2353 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
2355 (#) Configure the TIM pins by configuring the corresponding GPIO pins
2357 (#) Configure the Time base unit as described in the first part of this driver,
2358 if needed, else the Timer will run with the default configuration:
2359 (++) Autoreload value = 0xFFFF
2360 (++) Prescaler value = 0x0000
2361 (++) Counter mode = Up counting
2362 (++) Clock Division = TIM_CKD_DIV1
2364 (#) Fill the TIM_ICInitStruct with the desired parameters including:
2365 (++) TIM Channel: TIM_Channel
2366 (++) TIM Input Capture polarity: TIM_ICPolarity
2367 (++) TIM Input Capture selection: TIM_ICSelection
2368 (++) TIM Input Capture Prescaler: TIM_ICPrescaler
2369 (++) TIM Input CApture filter value: TIM_ICFilter
2371 (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
2372 corresponding configuration and to measure only frequency or duty cycle of the input signal,
2374 Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
2375 corresponding configuration and to measure the frequency and the duty cycle of the input signal
2377 (#) Enable the NVIC or the DMA to read the measured frequency.
2379 (#) Enable the corresponding interrupt (or DMA request) to read the Captured value,
2380 using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
2382 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
2384 (#) Use TIM_GetCapturex(TIMx); to read the captured value.
2386 (@) All other functions can be used separately to modify, if needed,
2387 a specific feature of the Timer.
2394 * @brief Initializes the TIM peripheral according to the specified parameters
2395 * in the TIM_ICInitStruct.
2396 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
2397 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
2398 * the configuration information for the specified TIM peripheral.
2401 void TIM_ICInit(TIM_TypeDef
* TIMx
, TIM_ICInitTypeDef
* TIM_ICInitStruct
)
2403 /* Check the parameters */
2404 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
2405 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct
->TIM_ICPolarity
));
2406 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct
->TIM_ICSelection
));
2407 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct
->TIM_ICPrescaler
));
2408 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct
->TIM_ICFilter
));
2410 if (TIM_ICInitStruct
->TIM_Channel
== TIM_Channel_1
)
2412 /* TI1 Configuration */
2413 TI1_Config(TIMx
, TIM_ICInitStruct
->TIM_ICPolarity
,
2414 TIM_ICInitStruct
->TIM_ICSelection
,
2415 TIM_ICInitStruct
->TIM_ICFilter
);
2416 /* Set the Input Capture Prescaler value */
2417 TIM_SetIC1Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2419 else if (TIM_ICInitStruct
->TIM_Channel
== TIM_Channel_2
)
2421 /* TI2 Configuration */
2422 TI2_Config(TIMx
, TIM_ICInitStruct
->TIM_ICPolarity
,
2423 TIM_ICInitStruct
->TIM_ICSelection
,
2424 TIM_ICInitStruct
->TIM_ICFilter
);
2425 /* Set the Input Capture Prescaler value */
2426 TIM_SetIC2Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2428 else if (TIM_ICInitStruct
->TIM_Channel
== TIM_Channel_3
)
2430 /* TI3 Configuration */
2431 TI3_Config(TIMx
, TIM_ICInitStruct
->TIM_ICPolarity
,
2432 TIM_ICInitStruct
->TIM_ICSelection
,
2433 TIM_ICInitStruct
->TIM_ICFilter
);
2434 /* Set the Input Capture Prescaler value */
2435 TIM_SetIC3Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2439 /* TI4 Configuration */
2440 TI4_Config(TIMx
, TIM_ICInitStruct
->TIM_ICPolarity
,
2441 TIM_ICInitStruct
->TIM_ICSelection
,
2442 TIM_ICInitStruct
->TIM_ICFilter
);
2443 /* Set the Input Capture Prescaler value */
2444 TIM_SetIC4Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2449 * @brief Fills each TIM_ICInitStruct member with its default value.
2450 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
2454 void TIM_ICStructInit(TIM_ICInitTypeDef
* TIM_ICInitStruct
)
2456 /* Set the default configuration */
2457 TIM_ICInitStruct
->TIM_Channel
= TIM_Channel_1
;
2458 TIM_ICInitStruct
->TIM_ICPolarity
= TIM_ICPolarity_Rising
;
2459 TIM_ICInitStruct
->TIM_ICSelection
= TIM_ICSelection_DirectTI
;
2460 TIM_ICInitStruct
->TIM_ICPrescaler
= TIM_ICPSC_DIV1
;
2461 TIM_ICInitStruct
->TIM_ICFilter
= 0x00;
2465 * @brief Configures the TIM peripheral according to the specified parameters
2466 * in the TIM_ICInitStruct to measure an external PWM signal.
2467 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
2469 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
2470 * the configuration information for the specified TIM peripheral.
2473 void TIM_PWMIConfig(TIM_TypeDef
* TIMx
, TIM_ICInitTypeDef
* TIM_ICInitStruct
)
2475 uint16_t icoppositepolarity
= TIM_ICPolarity_Rising
;
2476 uint16_t icoppositeselection
= TIM_ICSelection_DirectTI
;
2478 /* Check the parameters */
2479 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
2481 /* Select the Opposite Input Polarity */
2482 if (TIM_ICInitStruct
->TIM_ICPolarity
== TIM_ICPolarity_Rising
)
2484 icoppositepolarity
= TIM_ICPolarity_Falling
;
2488 icoppositepolarity
= TIM_ICPolarity_Rising
;
2490 /* Select the Opposite Input */
2491 if (TIM_ICInitStruct
->TIM_ICSelection
== TIM_ICSelection_DirectTI
)
2493 icoppositeselection
= TIM_ICSelection_IndirectTI
;
2497 icoppositeselection
= TIM_ICSelection_DirectTI
;
2499 if (TIM_ICInitStruct
->TIM_Channel
== TIM_Channel_1
)
2501 /* TI1 Configuration */
2502 TI1_Config(TIMx
, TIM_ICInitStruct
->TIM_ICPolarity
, TIM_ICInitStruct
->TIM_ICSelection
,
2503 TIM_ICInitStruct
->TIM_ICFilter
);
2504 /* Set the Input Capture Prescaler value */
2505 TIM_SetIC1Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2506 /* TI2 Configuration */
2507 TI2_Config(TIMx
, icoppositepolarity
, icoppositeselection
, TIM_ICInitStruct
->TIM_ICFilter
);
2508 /* Set the Input Capture Prescaler value */
2509 TIM_SetIC2Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2513 /* TI2 Configuration */
2514 TI2_Config(TIMx
, TIM_ICInitStruct
->TIM_ICPolarity
, TIM_ICInitStruct
->TIM_ICSelection
,
2515 TIM_ICInitStruct
->TIM_ICFilter
);
2516 /* Set the Input Capture Prescaler value */
2517 TIM_SetIC2Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2518 /* TI1 Configuration */
2519 TI1_Config(TIMx
, icoppositepolarity
, icoppositeselection
, TIM_ICInitStruct
->TIM_ICFilter
);
2520 /* Set the Input Capture Prescaler value */
2521 TIM_SetIC1Prescaler(TIMx
, TIM_ICInitStruct
->TIM_ICPrescaler
);
2526 * @brief Gets the TIMx Input Capture 1 value.
2527 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
2528 * @retval Capture Compare 1 Register value.
2530 uint32_t TIM_GetCapture1(TIM_TypeDef
* TIMx
)
2532 /* Check the parameters */
2533 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
2535 /* Get the Capture 1 Register value */
2540 * @brief Gets the TIMx Input Capture 2 value.
2541 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
2543 * @retval Capture Compare 2 Register value.
2545 uint32_t TIM_GetCapture2(TIM_TypeDef
* TIMx
)
2547 /* Check the parameters */
2548 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
2550 /* Get the Capture 2 Register value */
2555 * @brief Gets the TIMx Input Capture 3 value.
2556 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
2557 * @retval Capture Compare 3 Register value.
2559 uint32_t TIM_GetCapture3(TIM_TypeDef
* TIMx
)
2561 /* Check the parameters */
2562 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
2564 /* Get the Capture 3 Register value */
2569 * @brief Gets the TIMx Input Capture 4 value.
2570 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
2571 * @retval Capture Compare 4 Register value.
2573 uint32_t TIM_GetCapture4(TIM_TypeDef
* TIMx
)
2575 /* Check the parameters */
2576 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
2578 /* Get the Capture 4 Register value */
2583 * @brief Sets the TIMx Input Capture 1 prescaler.
2584 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
2585 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
2586 * This parameter can be one of the following values:
2587 * @arg TIM_ICPSC_DIV1: no prescaler
2588 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2589 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2590 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2593 void TIM_SetIC1Prescaler(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPSC
)
2595 /* Check the parameters */
2596 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
2597 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC
));
2599 /* Reset the IC1PSC Bits */
2600 TIMx
->CCMR1
&= (uint32_t)~TIM_CCMR1_IC1PSC
;
2602 /* Set the IC1PSC value */
2603 TIMx
->CCMR1
|= TIM_ICPSC
;
2607 * @brief Sets the TIMx Input Capture 2 prescaler.
2608 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
2610 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
2611 * This parameter can be one of the following values:
2612 * @arg TIM_ICPSC_DIV1: no prescaler
2613 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2614 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2615 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2618 void TIM_SetIC2Prescaler(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPSC
)
2620 /* Check the parameters */
2621 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
2622 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC
));
2624 /* Reset the IC2PSC Bits */
2625 TIMx
->CCMR1
&= (uint32_t)~TIM_CCMR1_IC2PSC
;
2627 /* Set the IC2PSC value */
2628 TIMx
->CCMR1
|= (uint32_t)((uint32_t)TIM_ICPSC
<< 8);
2632 * @brief Sets the TIMx Input Capture 3 prescaler.
2633 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
2634 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
2635 * This parameter can be one of the following values:
2636 * @arg TIM_ICPSC_DIV1: no prescaler
2637 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2638 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2639 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2642 void TIM_SetIC3Prescaler(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPSC
)
2644 /* Check the parameters */
2645 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
2646 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC
));
2648 /* Reset the IC3PSC Bits */
2649 TIMx
->CCMR2
&= (uint16_t)~TIM_CCMR2_IC3PSC
;
2651 /* Set the IC3PSC value */
2652 TIMx
->CCMR2
|= TIM_ICPSC
;
2656 * @brief Sets the TIMx Input Capture 4 prescaler.
2657 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
2658 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
2659 * This parameter can be one of the following values:
2660 * @arg TIM_ICPSC_DIV1: no prescaler
2661 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2662 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2663 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2666 void TIM_SetIC4Prescaler(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPSC
)
2668 /* Check the parameters */
2669 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
2670 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC
));
2672 /* Reset the IC4PSC Bits */
2673 TIMx
->CCMR2
&= (uint16_t)~TIM_CCMR2_IC4PSC
;
2675 /* Set the IC4PSC value */
2676 TIMx
->CCMR2
|= (uint16_t)(TIM_ICPSC
<< 8);
2682 /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
2683 * @brief Advanced-control timers (TIM1 and TIM8) specific features
2686 ===============================================================================
2687 ##### Advanced-control timers (TIM1 and TIM8) specific features #####
2688 ===============================================================================
2690 *** TIM Driver: how to use the Break feature ***
2691 ================================================
2693 After configuring the Timer channel(s) in the appropriate Output Compare mode:
2695 (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
2696 Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
2697 AOE(automatic output enable).
2699 (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
2701 (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
2703 (#) Once the break even occurs, the Timer's output signals are put in reset
2704 state or in a known state (according to the configuration made in
2705 TIM_BDTRConfig() function).
2712 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2713 * and the AOE(automatic output enable).
2714 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM
2715 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
2716 * contains the BDTR Register configuration information for the TIM peripheral.
2719 void TIM_BDTRConfig(TIM_TypeDef
* TIMx
, TIM_BDTRInitTypeDef
*TIM_BDTRInitStruct
)
2721 /* Check the parameters */
2722 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2723 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct
->TIM_OSSRState
));
2724 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct
->TIM_OSSIState
));
2725 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct
->TIM_LOCKLevel
));
2726 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct
->TIM_Break
));
2727 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct
->TIM_BreakPolarity
));
2728 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct
->TIM_AutomaticOutput
));
2730 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2731 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2732 TIMx
->BDTR
= (uint32_t)TIM_BDTRInitStruct
->TIM_OSSRState
| TIM_BDTRInitStruct
->TIM_OSSIState
|
2733 TIM_BDTRInitStruct
->TIM_LOCKLevel
| TIM_BDTRInitStruct
->TIM_DeadTime
|
2734 TIM_BDTRInitStruct
->TIM_Break
| TIM_BDTRInitStruct
->TIM_BreakPolarity
|
2735 TIM_BDTRInitStruct
->TIM_AutomaticOutput
;
2739 * @brief Configures the Break1 feature.
2740 * @param TIMx: where x can be 1 or 8 to select the TIM
2741 * @param TIM_Break1Polarity: specifies the Break1 polarity.
2742 * This parameter can be one of the following values:
2743 * @arg TIM_Break1Polarity_Low: Break1 input is active low
2744 * @arg TIM_Break1Polarity_High: Break1 input is active high
2745 * @param TIM_Break1Filter: specifies the Break1 filter value.
2746 * This parameter must be a value between 0x00 and 0x0F
2749 void TIM_Break1Config(TIM_TypeDef
* TIMx
, uint32_t TIM_Break1Polarity
, uint8_t TIM_Break1Filter
)
2750 { /* Check the parameters */
2751 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2752 assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter
));
2754 /* Reset the BKP and BKF Bits */
2755 TIMx
->BDTR
&= (uint32_t)~ (TIM_BDTR_BKP
| TIM_BDTR_BKF
);
2756 /* Configure the Break1 polarity and filter */
2757 TIMx
->BDTR
|= TIM_Break1Polarity
|((uint32_t)TIM_Break1Filter
<< 16);
2761 * @brief Configures the Break2 feature.
2762 * @param TIMx: where x can be 1 or 8 to select the TIM
2763 * @param TIM_Break2Polarity: specifies the Break2 polarity.
2764 * This parameter can be one of the following values:
2765 * @arg TIM_Break2Polarity_Low: Break2 input is active low
2766 * @arg TIM_Break2Polarity_High: Break2 input is active high
2767 * @param TIM_Break2Filter: specifies the Break2 filter value.
2768 * This parameter must be a value between 0x00 and 0x0F
2771 void TIM_Break2Config(TIM_TypeDef
* TIMx
, uint32_t TIM_Break2Polarity
, uint8_t TIM_Break2Filter
)
2773 /* Check the parameters */
2774 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2775 assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter
));
2777 /* Reset the BKP and BKF Bits */
2778 TIMx
->BDTR
&= (uint32_t)~ (TIM_BDTR_BK2P
| TIM_BDTR_BK2F
);
2780 /* Configure the Break1 polarity and filter */
2781 TIMx
->BDTR
|= TIM_Break2Polarity
|((uint32_t)TIM_Break2Filter
<< 20);
2785 * @brief Enables or disables the TIM Break1 input.
2786 * @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral.
2787 * @param NewState: new state of the TIM Break1 input.
2788 * This parameter can be: ENABLE or DISABLE.
2791 void TIM_Break1Cmd(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
2793 /* Check the parameters */
2794 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2795 assert_param(IS_FUNCTIONAL_STATE(NewState
));
2797 if (NewState
!= DISABLE
)
2799 /* Enable the Break1 */
2800 TIMx
->BDTR
|= TIM_BDTR_BKE
;
2804 /* Disable the Break1 */
2805 TIMx
->BDTR
&= (uint32_t)~TIM_BDTR_BKE
;
2810 * @brief Enables or disables the TIM Break2 input.
2811 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
2812 * @param NewState: new state of the TIM Break2 input.
2813 * This parameter can be: ENABLE or DISABLE.
2816 void TIM_Break2Cmd(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
2818 /* Check the parameters */
2819 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
2820 assert_param(IS_FUNCTIONAL_STATE(NewState
));
2822 if (NewState
!= DISABLE
)
2824 /* Enable the Break1 */
2825 TIMx
->BDTR
|= TIM_BDTR_BK2E
;
2829 /* Disable the Break1 */
2830 TIMx
->BDTR
&= (uint32_t)~TIM_BDTR_BK2E
;
2835 * @brief Fills each TIM_BDTRInitStruct member with its default value.
2836 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
2837 * will be initialized.
2840 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef
* TIM_BDTRInitStruct
)
2842 /* Set the default configuration */
2843 TIM_BDTRInitStruct
->TIM_OSSRState
= TIM_OSSRState_Disable
;
2844 TIM_BDTRInitStruct
->TIM_OSSIState
= TIM_OSSIState_Disable
;
2845 TIM_BDTRInitStruct
->TIM_LOCKLevel
= TIM_LOCKLevel_OFF
;
2846 TIM_BDTRInitStruct
->TIM_DeadTime
= 0x00;
2847 TIM_BDTRInitStruct
->TIM_Break
= TIM_Break_Disable
;
2848 TIM_BDTRInitStruct
->TIM_BreakPolarity
= TIM_BreakPolarity_Low
;
2849 TIM_BDTRInitStruct
->TIM_AutomaticOutput
= TIM_AutomaticOutput_Disable
;
2853 * @brief Enables or disables the TIM peripheral Main Outputs.
2854 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
2855 * @param NewState: new state of the TIM peripheral Main Outputs.
2856 * This parameter can be: ENABLE or DISABLE.
2859 void TIM_CtrlPWMOutputs(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
2861 /* Check the parameters */
2862 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2863 assert_param(IS_FUNCTIONAL_STATE(NewState
));
2865 if (NewState
!= DISABLE
)
2867 /* Enable the TIM Main Output */
2868 TIMx
->BDTR
|= TIM_BDTR_MOE
;
2872 /* Disable the TIM Main Output */
2873 TIMx
->BDTR
&= (uint16_t)~TIM_BDTR_MOE
;
2878 * @brief Selects the TIM peripheral Commutation event.
2879 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
2880 * @param NewState: new state of the Commutation event.
2881 * This parameter can be: ENABLE or DISABLE.
2884 void TIM_SelectCOM(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
2886 /* Check the parameters */
2887 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2888 assert_param(IS_FUNCTIONAL_STATE(NewState
));
2890 if (NewState
!= DISABLE
)
2892 /* Set the COM Bit */
2893 TIMx
->CR2
|= TIM_CR2_CCUS
;
2897 /* Reset the COM Bit */
2898 TIMx
->CR2
&= (uint16_t)~TIM_CR2_CCUS
;
2903 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
2904 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
2905 * @param NewState: new state of the Capture Compare Preload Control bit
2906 * This parameter can be: ENABLE or DISABLE.
2909 void TIM_CCPreloadControl(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
2911 /* Check the parameters */
2912 assert_param(IS_TIM_LIST6_PERIPH(TIMx
));
2913 assert_param(IS_FUNCTIONAL_STATE(NewState
));
2914 if (NewState
!= DISABLE
)
2916 /* Set the CCPC Bit */
2917 TIMx
->CR2
|= TIM_CR2_CCPC
;
2921 /* Reset the CCPC Bit */
2922 TIMx
->CR2
&= (uint16_t)~TIM_CR2_CCPC
;
2929 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions
2930 * @brief Interrupts, DMA and flags management functions
2933 ===============================================================================
2934 ##### Interrupts, DMA and flags management functions #####
2935 ===============================================================================
2942 * @brief Enables or disables the specified TIM interrupts.
2943 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral.
2944 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
2945 * This parameter can be any combination of the following values:
2946 * @arg TIM_IT_Update: TIM update Interrupt source
2947 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
2948 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
2949 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
2950 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
2951 * @arg TIM_IT_COM: TIM Commutation Interrupt source
2952 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
2953 * @arg TIM_IT_Break: TIM Break Interrupt source
2955 * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
2956 * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
2957 * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
2958 * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
2959 * be used: TIM_IT_Update or TIM_IT_CC1
2960 * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
2962 * @param NewState: new state of the TIM interrupts.
2963 * This parameter can be: ENABLE or DISABLE.
2966 void TIM_ITConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_IT
, FunctionalState NewState
)
2968 /* Check the parameters */
2969 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
2970 assert_param(IS_TIM_IT(TIM_IT
));
2971 assert_param(IS_FUNCTIONAL_STATE(NewState
));
2973 if (NewState
!= DISABLE
)
2975 /* Enable the Interrupt sources */
2976 TIMx
->DIER
|= TIM_IT
;
2980 /* Disable the Interrupt sources */
2981 TIMx
->DIER
&= (uint16_t)~TIM_IT
;
2986 * @brief Configures the TIMx event to be generate by software.
2987 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
2988 * @param TIM_EventSource: specifies the event source.
2989 * This parameter can be one or more of the following values:
2990 * @arg TIM_EventSource_Update: Timer update Event source
2991 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
2992 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
2993 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
2994 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
2995 * @arg TIM_EventSource_COM: Timer COM event source
2996 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
2997 * @arg TIM_EventSource_Break: Timer Break event source
2999 * @note TIM6 and TIM7 can only generate an update event.
3000 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
3004 void TIM_GenerateEvent(TIM_TypeDef
* TIMx
, uint16_t TIM_EventSource
)
3006 /* Check the parameters */
3007 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
3008 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource
));
3010 /* Set the event sources */
3011 TIMx
->EGR
= TIM_EventSource
;
3015 * @brief Checks whether the specified TIM flag is set or not.
3016 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
3017 * @param TIM_FLAG: specifies the flag to check.
3018 * This parameter can be one of the following values:
3019 * @arg TIM_FLAG_Update: TIM update Flag
3020 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
3021 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
3022 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
3023 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
3024 * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
3025 * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
3026 * @arg TIM_FLAG_COM: TIM Commutation Flag
3027 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
3028 * @arg TIM_FLAG_Break: TIM Break Flag
3029 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
3030 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
3031 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
3032 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
3034 * @note TIM6 and TIM7 can have only one update flag.
3035 * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
3037 * @retval The new state of TIM_FLAG (SET or RESET).
3039 FlagStatus
TIM_GetFlagStatus(TIM_TypeDef
* TIMx
, uint32_t TIM_FLAG
)
3041 ITStatus bitstatus
= RESET
;
3042 /* Check the parameters */
3043 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
3044 assert_param(IS_TIM_GET_FLAG(TIM_FLAG
));
3047 if ((TIMx
->SR
& TIM_FLAG
) != RESET
)
3059 * @brief Clears the TIMx's pending flags.
3060 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
3061 * @param TIM_FLAG: specifies the flag bit to clear.
3062 * This parameter can be any combination of the following values:
3063 * @arg TIM_FLAG_Update: TIM update Flag
3064 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
3065 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
3066 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
3067 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
3068 * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
3069 * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
3070 * @arg TIM_FLAG_COM: TIM Commutation Flag
3071 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
3072 * @arg TIM_FLAG_Break: TIM Break Flag
3073 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
3074 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
3075 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
3076 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
3078 * @note TIM6 and TIM7 can have only one update flag.
3079 * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
3083 void TIM_ClearFlag(TIM_TypeDef
* TIMx
, uint16_t TIM_FLAG
)
3085 /* Check the parameters */
3086 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
3088 /* Clear the flags */
3089 TIMx
->SR
= (uint16_t)~TIM_FLAG
;
3093 * @brief Checks whether the TIM interrupt has occurred or not.
3094 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
3095 * @param TIM_IT: specifies the TIM interrupt source to check.
3096 * This parameter can be one of the following values:
3097 * @arg TIM_IT_Update: TIM update Interrupt source
3098 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
3099 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
3100 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
3101 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
3102 * @arg TIM_IT_COM: TIM Commutation Interrupt source
3103 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
3104 * @arg TIM_IT_Break: TIM Break Interrupt source
3106 * @note TIM6 and TIM7 can generate only an update interrupt.
3107 * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
3109 * @retval The new state of the TIM_IT(SET or RESET).
3111 ITStatus
TIM_GetITStatus(TIM_TypeDef
* TIMx
, uint16_t TIM_IT
)
3113 ITStatus bitstatus
= RESET
;
3114 uint16_t itstatus
= 0x0, itenable
= 0x0;
3115 /* Check the parameters */
3116 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
3117 assert_param(IS_TIM_GET_IT(TIM_IT
));
3119 itstatus
= TIMx
->SR
& TIM_IT
;
3121 itenable
= TIMx
->DIER
& TIM_IT
;
3122 if ((itstatus
!= (uint16_t)RESET
) && (itenable
!= (uint16_t)RESET
))
3134 * @brief Clears the TIMx's interrupt pending bits.
3135 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
3136 * @param TIM_IT: specifies the pending bit to clear.
3137 * This parameter can be any combination of the following values:
3138 * @arg TIM_IT_Update: TIM1 update Interrupt source
3139 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
3140 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
3141 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
3142 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
3143 * @arg TIM_IT_COM: TIM Commutation Interrupt source
3144 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
3145 * @arg TIM_IT_Break: TIM Break Interrupt source
3147 * @note TIM6 and TIM7 can generate only an update interrupt.
3148 * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
3152 void TIM_ClearITPendingBit(TIM_TypeDef
* TIMx
, uint16_t TIM_IT
)
3154 /* Check the parameters */
3155 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
3157 /* Clear the IT pending Bit */
3158 TIMx
->SR
= (uint16_t)~TIM_IT
;
3162 * @brief Configures the TIMx's DMA interface.
3163 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
3164 * @param TIM_DMABase: DMA Base address.
3165 * This parameter can be one of the following values:
3166 * @arg TIM_DMABase_CR1
3167 * @arg TIM_DMABase_CR2
3168 * @arg TIM_DMABase_SMCR
3169 * @arg TIM_DMABase_DIER
3170 * @arg TIM1_DMABase_SR
3171 * @arg TIM_DMABase_EGR
3172 * @arg TIM_DMABase_CCMR1
3173 * @arg TIM_DMABase_CCMR2
3174 * @arg TIM_DMABase_CCER
3175 * @arg TIM_DMABase_CNT
3176 * @arg TIM_DMABase_PSC
3177 * @arg TIM_DMABase_ARR
3178 * @arg TIM_DMABase_RCR
3179 * @arg TIM_DMABase_CCR1
3180 * @arg TIM_DMABase_CCR2
3181 * @arg TIM_DMABase_CCR3
3182 * @arg TIM_DMABase_CCR4
3183 * @arg TIM_DMABase_BDTR
3184 * @arg TIM_DMABase_DCR
3185 * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
3186 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3189 void TIM_DMAConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_DMABase
, uint16_t TIM_DMABurstLength
)
3191 /* Check the parameters */
3192 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
3193 assert_param(IS_TIM_DMA_BASE(TIM_DMABase
));
3194 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength
));
3196 /* Set the DMA Base and the DMA Burst Length */
3197 TIMx
->DCR
= TIM_DMABase
| TIM_DMABurstLength
;
3201 * @brief Enables or disables the TIMx's DMA Requests.
3202 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
3203 * @param TIM_DMASource: specifies the DMA Request sources.
3204 * This parameter can be any combination of the following values:
3205 * @arg TIM_DMA_Update: TIM update Interrupt source
3206 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3207 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3208 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3209 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3210 * @arg TIM_DMA_COM: TIM Commutation DMA source
3211 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
3212 * @param NewState: new state of the DMA Request sources.
3213 * This parameter can be: ENABLE or DISABLE.
3216 void TIM_DMACmd(TIM_TypeDef
* TIMx
, uint16_t TIM_DMASource
, FunctionalState NewState
)
3218 /* Check the parameters */
3219 assert_param(IS_TIM_ALL_PERIPH(TIMx
));
3220 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource
));
3221 assert_param(IS_FUNCTIONAL_STATE(NewState
));
3223 if (NewState
!= DISABLE
)
3225 /* Enable the DMA sources */
3226 TIMx
->DIER
|= TIM_DMASource
;
3230 /* Disable the DMA sources */
3231 TIMx
->DIER
&= (uint16_t)~TIM_DMASource
;
3236 * @brief Selects the TIMx peripheral Capture Compare DMA source.
3237 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
3238 * @param NewState: new state of the Capture Compare DMA source
3239 * This parameter can be: ENABLE or DISABLE.
3242 void TIM_SelectCCDMA(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
3244 /* Check the parameters */
3245 assert_param(IS_TIM_LIST1_PERIPH(TIMx
));
3246 assert_param(IS_FUNCTIONAL_STATE(NewState
));
3248 if (NewState
!= DISABLE
)
3250 /* Set the CCDS Bit */
3251 TIMx
->CR2
|= TIM_CR2_CCDS
;
3255 /* Reset the CCDS Bit */
3256 TIMx
->CR2
&= (uint16_t)~TIM_CR2_CCDS
;
3263 /** @defgroup TIM_Group6 Clocks management functions
3264 * @brief Clocks management functions
3267 ===============================================================================
3268 ##### Clocks management functions #####
3269 ===============================================================================
3276 * @brief Configures the TIMx internal Clock
3277 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
3281 void TIM_InternalClockConfig(TIM_TypeDef
* TIMx
)
3283 /* Check the parameters */
3284 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3286 /* Disable slave mode to clock the prescaler directly with the internal clock */
3287 TIMx
->SMCR
&= (uint16_t)~TIM_SMCR_SMS
;
3291 * @brief Configures the TIMx Internal Trigger as External Clock
3292 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
3294 * @param TIM_InputTriggerSource: Trigger source.
3295 * This parameter can be one of the following values:
3296 * @arg TIM_TS_ITR0: Internal Trigger 0
3297 * @arg TIM_TS_ITR1: Internal Trigger 1
3298 * @arg TIM_TS_ITR2: Internal Trigger 2
3299 * @arg TIM_TS_ITR3: Internal Trigger 3
3302 void TIM_ITRxExternalClockConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_InputTriggerSource
)
3304 /* Check the parameters */
3305 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3306 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource
));
3308 /* Select the Internal Trigger */
3309 TIM_SelectInputTrigger(TIMx
, TIM_InputTriggerSource
);
3311 /* Select the External clock mode1 */
3312 TIMx
->SMCR
|= TIM_SlaveMode_External1
;
3316 * @brief Configures the TIMx Trigger as External Clock
3317 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
3318 * to select the TIM peripheral.
3319 * @param TIM_TIxExternalCLKSource: Trigger source.
3320 * This parameter can be one of the following values:
3321 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
3322 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
3323 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
3324 * @param TIM_ICPolarity: specifies the TIx Polarity.
3325 * This parameter can be one of the following values:
3326 * @arg TIM_ICPolarity_Rising
3327 * @arg TIM_ICPolarity_Falling
3328 * @param ICFilter: specifies the filter value.
3329 * This parameter must be a value between 0x0 and 0xF.
3332 void TIM_TIxExternalClockConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_TIxExternalCLKSource
,
3333 uint16_t TIM_ICPolarity
, uint16_t ICFilter
)
3335 /* Check the parameters */
3336 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3337 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity
));
3338 assert_param(IS_TIM_IC_FILTER(ICFilter
));
3340 /* Configure the Timer Input Clock Source */
3341 if (TIM_TIxExternalCLKSource
== TIM_TIxExternalCLK1Source_TI2
)
3343 TI2_Config(TIMx
, TIM_ICPolarity
, TIM_ICSelection_DirectTI
, ICFilter
);
3347 TI1_Config(TIMx
, TIM_ICPolarity
, TIM_ICSelection_DirectTI
, ICFilter
);
3349 /* Select the Trigger source */
3350 TIM_SelectInputTrigger(TIMx
, TIM_TIxExternalCLKSource
);
3351 /* Select the External clock mode1 */
3352 TIMx
->SMCR
|= TIM_SlaveMode_External1
;
3356 * @brief Configures the External clock Mode1
3357 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
3358 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
3359 * This parameter can be one of the following values:
3360 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
3361 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
3362 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
3363 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
3364 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
3365 * This parameter can be one of the following values:
3366 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
3367 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
3368 * @param ExtTRGFilter: External Trigger Filter.
3369 * This parameter must be a value between 0x00 and 0x0F
3372 void TIM_ETRClockMode1Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ExtTRGPrescaler
,
3373 uint16_t TIM_ExtTRGPolarity
, uint16_t ExtTRGFilter
)
3375 uint16_t tmpsmcr
= 0;
3377 /* Check the parameters */
3378 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
3379 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler
));
3380 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity
));
3381 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter
));
3382 /* Configure the ETR Clock source */
3383 TIM_ETRConfig(TIMx
, TIM_ExtTRGPrescaler
, TIM_ExtTRGPolarity
, ExtTRGFilter
);
3385 /* Get the TIMx SMCR register value */
3386 tmpsmcr
= TIMx
->SMCR
;
3388 /* Reset the SMS Bits */
3389 tmpsmcr
&= (uint16_t)~TIM_SMCR_SMS
;
3391 /* Select the External clock mode1 */
3392 tmpsmcr
|= TIM_SlaveMode_External1
;
3394 /* Select the Trigger selection : ETRF */
3395 tmpsmcr
&= (uint16_t)~TIM_SMCR_TS
;
3396 tmpsmcr
|= TIM_TS_ETRF
;
3398 /* Write to TIMx SMCR */
3399 TIMx
->SMCR
= tmpsmcr
;
3403 * @brief Configures the External clock Mode2
3404 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
3405 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
3406 * This parameter can be one of the following values:
3407 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
3408 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
3409 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
3410 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
3411 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
3412 * This parameter can be one of the following values:
3413 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
3414 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
3415 * @param ExtTRGFilter: External Trigger Filter.
3416 * This parameter must be a value between 0x00 and 0x0F
3419 void TIM_ETRClockMode2Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ExtTRGPrescaler
,
3420 uint16_t TIM_ExtTRGPolarity
, uint16_t ExtTRGFilter
)
3422 /* Check the parameters */
3423 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
3424 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler
));
3425 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity
));
3426 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter
));
3428 /* Configure the ETR Clock source */
3429 TIM_ETRConfig(TIMx
, TIM_ExtTRGPrescaler
, TIM_ExtTRGPolarity
, ExtTRGFilter
);
3431 /* Enable the External clock mode2 */
3432 TIMx
->SMCR
|= TIM_SMCR_ECE
;
3438 /** @defgroup TIM_Group7 Synchronization management functions
3439 * @brief Synchronization management functions
3442 ===============================================================================
3443 ##### Synchronization management functions #####
3444 ===============================================================================
3446 *** TIM Driver: how to use it in synchronization Mode ***
3447 =========================================================
3448 [..] Case of two/several Timers
3450 (#) Configure the Master Timers using the following functions:
3451 (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
3452 (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
3453 (#) Configure the Slave Timers using the following functions:
3454 (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
3455 (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
3457 [..] Case of Timers and external trigger(ETR pin)
3459 (#) Configure the External trigger using this function:
3460 (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
3461 uint16_t ExtTRGFilter);
3462 (#) Configure the Slave Timers using the following functions:
3463 (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
3464 (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
3471 * @brief Selects the Input Trigger source
3472 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
3473 * to select the TIM peripheral.
3474 * @param TIM_InputTriggerSource: The Input Trigger source.
3475 * This parameter can be one of the following values:
3476 * @arg TIM_TS_ITR0: Internal Trigger 0
3477 * @arg TIM_TS_ITR1: Internal Trigger 1
3478 * @arg TIM_TS_ITR2: Internal Trigger 2
3479 * @arg TIM_TS_ITR3: Internal Trigger 3
3480 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
3481 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
3482 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
3483 * @arg TIM_TS_ETRF: External Trigger input
3486 void TIM_SelectInputTrigger(TIM_TypeDef
* TIMx
, uint16_t TIM_InputTriggerSource
)
3488 uint16_t tmpsmcr
= 0;
3490 /* Check the parameters */
3491 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3492 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource
));
3494 /* Get the TIMx SMCR register value */
3495 tmpsmcr
= TIMx
->SMCR
;
3497 /* Reset the TS Bits */
3498 tmpsmcr
&= (uint16_t)~TIM_SMCR_TS
;
3500 /* Set the Input Trigger source */
3501 tmpsmcr
|= TIM_InputTriggerSource
;
3503 /* Write to TIMx SMCR */
3504 TIMx
->SMCR
= tmpsmcr
;
3508 * @brief Selects the TIMx Trigger Output Mode.
3509 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral.
3511 * @param TIM_TRGOSource: specifies the Trigger Output source.
3512 * This parameter can be one of the following values:
3515 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
3516 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
3517 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
3519 * - For all TIMx except TIM6 and TIM7
3520 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
3521 * is to be set, as soon as a capture or compare match occurs(TRGO)
3522 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
3523 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
3524 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
3525 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
3529 void TIM_SelectOutputTrigger(TIM_TypeDef
* TIMx
, uint16_t TIM_TRGOSource
)
3531 /* Check the parameters */
3532 assert_param(IS_TIM_LIST7_PERIPH(TIMx
));
3533 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource
));
3535 /* Reset the MMS Bits */
3536 TIMx
->CR2
&= (uint16_t)~TIM_CR2_MMS
;
3537 /* Select the TRGO source */
3538 TIMx
->CR2
|= TIM_TRGOSource
;
3542 * @brief Selects the TIMx Trigger Output Mode2 (TRGO2).
3543 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
3545 * @param TIM_TRGO2Source: specifies the Trigger Output source.
3546 * This parameter can be one of the following values:
3549 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2)
3550 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2)
3551 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2)
3552 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
3553 * is to be set, as soon as a capture or compare match occurs(TRGO2)
3554 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2)
3555 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2)
3556 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2)
3557 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2)
3558 * @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2)
3559 * @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2)
3560 * @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
3561 * @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
3562 * @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
3563 * @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
3567 void TIM_SelectOutputTrigger2(TIM_TypeDef
* TIMx
, uint32_t TIM_TRGO2Source
)
3569 /* Check the parameters */
3570 assert_param(IS_TIM_LIST4_PERIPH(TIMx
));
3571 assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source
));
3573 /* Reset the MMS Bits */
3574 TIMx
->CR2
&= (uint32_t)~TIM_CR2_MMS2
;
3575 /* Select the TRGO source */
3576 TIMx
->CR2
|= TIM_TRGO2Source
;
3580 * @brief Selects the TIMx Slave Mode.
3581 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
3582 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
3583 * This parameter can be one of the following values:
3584 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
3585 * the counter and triggers an update of the registers
3586 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
3587 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
3588 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
3589 * @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI)
3590 * reinitializes the counter, generates an update
3591 * of the registers and starts the counter.
3594 void TIM_SelectSlaveMode(TIM_TypeDef
* TIMx
, uint32_t TIM_SlaveMode
)
3596 /* Check the parameters */
3597 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3598 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode
));
3600 /* Reset the SMS Bits */
3601 TIMx
->SMCR
&= (uint32_t)~TIM_SMCR_SMS
;
3603 /* Select the Slave Mode */
3604 TIMx
->SMCR
|= (uint32_t)TIM_SlaveMode
;
3608 * @brief Sets or Resets the TIMx Master/Slave Mode.
3609 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
3610 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
3611 * This parameter can be one of the following values:
3612 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
3613 * and its slaves (through TRGO)
3614 * @arg TIM_MasterSlaveMode_Disable: No action
3617 void TIM_SelectMasterSlaveMode(TIM_TypeDef
* TIMx
, uint16_t TIM_MasterSlaveMode
)
3619 /* Check the parameters */
3620 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3621 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode
));
3623 /* Reset the MSM Bit */
3624 TIMx
->SMCR
&= (uint16_t)~TIM_SMCR_MSM
;
3626 /* Set or Reset the MSM Bit */
3627 TIMx
->SMCR
|= TIM_MasterSlaveMode
;
3631 * @brief Configures the TIMx External Trigger (ETR).
3632 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
3633 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
3634 * This parameter can be one of the following values:
3635 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
3636 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
3637 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
3638 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
3639 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
3640 * This parameter can be one of the following values:
3641 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
3642 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
3643 * @param ExtTRGFilter: External Trigger Filter.
3644 * This parameter must be a value between 0x00 and 0x0F
3647 void TIM_ETRConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_ExtTRGPrescaler
,
3648 uint16_t TIM_ExtTRGPolarity
, uint16_t ExtTRGFilter
)
3650 uint16_t tmpsmcr
= 0;
3652 /* Check the parameters */
3653 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
3654 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler
));
3655 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity
));
3656 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter
));
3658 tmpsmcr
= TIMx
->SMCR
;
3660 /* Reset the ETR Bits */
3661 tmpsmcr
&= SMCR_ETR_MASK
;
3663 /* Set the Prescaler, the Filter value and the Polarity */
3664 tmpsmcr
|= (uint16_t)(TIM_ExtTRGPrescaler
| (uint16_t)(TIM_ExtTRGPolarity
| (uint16_t)(ExtTRGFilter
<< (uint16_t)8)));
3666 /* Write to TIMx SMCR */
3667 TIMx
->SMCR
= tmpsmcr
;
3673 /** @defgroup TIM_Group8 Specific interface management functions
3674 * @brief Specific interface management functions
3677 ===============================================================================
3678 ##### Specific interface management functions #####
3679 ===============================================================================
3686 * @brief Configures the TIMx Encoder Interface.
3687 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM
3689 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
3690 * This parameter can be one of the following values:
3691 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
3692 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
3693 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
3694 * on the level of the other input.
3695 * @param TIM_IC1Polarity: specifies the IC1 Polarity
3696 * This parameter can be one of the following values:
3697 * @arg TIM_ICPolarity_Falling: IC Falling edge.
3698 * @arg TIM_ICPolarity_Rising: IC Rising edge.
3699 * @param TIM_IC2Polarity: specifies the IC2 Polarity
3700 * This parameter can be one of the following values:
3701 * @arg TIM_ICPolarity_Falling: IC Falling edge.
3702 * @arg TIM_ICPolarity_Rising: IC Rising edge.
3705 void TIM_EncoderInterfaceConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_EncoderMode
,
3706 uint16_t TIM_IC1Polarity
, uint16_t TIM_IC2Polarity
)
3708 uint16_t tmpsmcr
= 0;
3709 uint16_t tmpccmr1
= 0;
3710 uint16_t tmpccer
= 0;
3712 /* Check the parameters */
3713 assert_param(IS_TIM_LIST3_PERIPH(TIMx
));
3714 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode
));
3715 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity
));
3716 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity
));
3718 /* Get the TIMx SMCR register value */
3719 tmpsmcr
= TIMx
->SMCR
;
3721 /* Get the TIMx CCMR1 register value */
3722 tmpccmr1
= TIMx
->CCMR1
;
3724 /* Get the TIMx CCER register value */
3725 tmpccer
= TIMx
->CCER
;
3727 /* Set the encoder Mode */
3728 tmpsmcr
&= (uint16_t)~TIM_SMCR_SMS
;
3729 tmpsmcr
|= TIM_EncoderMode
;
3731 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3732 tmpccmr1
&= ((uint16_t)~TIM_CCMR1_CC1S
) & ((uint16_t)~TIM_CCMR1_CC2S
);
3733 tmpccmr1
|= TIM_CCMR1_CC1S_0
| TIM_CCMR1_CC2S_0
;
3735 /* Set the TI1 and the TI2 Polarities */
3736 tmpccer
&= ((uint16_t)~TIM_CCER_CC1P
) & ((uint16_t)~TIM_CCER_CC2P
);
3737 tmpccer
|= (uint16_t)(TIM_IC1Polarity
| (uint16_t)(TIM_IC2Polarity
<< (uint16_t)4));
3739 /* Write to TIMx SMCR */
3740 TIMx
->SMCR
= tmpsmcr
;
3742 /* Write to TIMx CCMR1 */
3743 TIMx
->CCMR1
= tmpccmr1
;
3745 /* Write to TIMx CCER */
3746 TIMx
->CCER
= tmpccer
;
3750 * @brief Enables or disables the TIMx's Hall sensor interface.
3751 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
3753 * @param NewState: new state of the TIMx Hall sensor interface.
3754 * This parameter can be: ENABLE or DISABLE.
3757 void TIM_SelectHallSensor(TIM_TypeDef
* TIMx
, FunctionalState NewState
)
3759 /* Check the parameters */
3760 assert_param(IS_TIM_LIST2_PERIPH(TIMx
));
3761 assert_param(IS_FUNCTIONAL_STATE(NewState
));
3763 if (NewState
!= DISABLE
)
3765 /* Set the TI1S Bit */
3766 TIMx
->CR2
|= TIM_CR2_TI1S
;
3770 /* Reset the TI1S Bit */
3771 TIMx
->CR2
&= (uint16_t)~TIM_CR2_TI1S
;
3778 /** @defgroup TIM_Group9 Specific remapping management function
3779 * @brief Specific remapping management function
3782 ===============================================================================
3783 ##### Specific remapping management function #####
3784 ===============================================================================
3791 * @brief Configures the TIM16 Remapping input Capabilities.
3792 * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral.
3793 * @param TIM_Remap: specifies the TIM input reampping source.
3794 * This parameter can be one of the following values:
3795 * @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO.
3796 * @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock.
3797 * @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock.
3798 * @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock.
3799 * @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1.
3800 * @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2.
3801 * @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3.
3802 * @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1.
3803 * @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2.
3804 * @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3.
3805 * @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1.
3806 * @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2.
3807 * @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3.
3808 * @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1.
3809 * @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2.
3810 * @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3.
3813 void TIM_RemapConfig(TIM_TypeDef
* TIMx
, uint16_t TIM_Remap
)
3815 /* Check the parameters */
3816 assert_param(IS_TIM_LIST8_PERIPH(TIMx
));
3817 assert_param(IS_TIM_REMAP(TIM_Remap
));
3819 /* Set the Timer remapping configuration */
3820 TIMx
->OR
= TIM_Remap
;
3827 * @brief Configure the TI1 as Input.
3828 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
3829 * to select the TIM peripheral.
3830 * @param TIM_ICPolarity : The Input Polarity.
3831 * This parameter can be one of the following values:
3832 * @arg TIM_ICPolarity_Rising
3833 * @arg TIM_ICPolarity_Falling
3834 * @arg TIM_ICPolarity_BothEdge
3835 * @param TIM_ICSelection: specifies the input to be used.
3836 * This parameter can be one of the following values:
3837 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
3838 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
3839 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
3840 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3841 * This parameter must be a value between 0x00 and 0x0F.
3844 static void TI1_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
3845 uint16_t TIM_ICFilter
)
3847 uint32_t tmpccmr1
= 0, tmpccer
= 0;
3849 /* Disable the Channel 1: Reset the CC1E Bit */
3850 TIMx
->CCER
&= (uint32_t)~TIM_CCER_CC1E
;
3851 tmpccmr1
= TIMx
->CCMR1
;
3852 tmpccer
= TIMx
->CCER
;
3854 /* Select the Input and set the filter */
3855 tmpccmr1
&= ((uint32_t)~TIM_CCMR1_CC1S
) & ((uint32_t)~TIM_CCMR1_IC1F
);
3856 tmpccmr1
|= (uint32_t)(TIM_ICSelection
| (uint32_t)((uint32_t)TIM_ICFilter
<< 4));
3858 /* Select the Polarity and set the CC1E Bit */
3859 tmpccer
&= (uint32_t)~(TIM_CCER_CC1P
| TIM_CCER_CC1NP
);
3860 tmpccer
|= (uint32_t)(TIM_ICPolarity
| (uint32_t)TIM_CCER_CC1E
);
3862 /* Write to TIMx CCMR1 and CCER registers */
3863 TIMx
->CCMR1
= tmpccmr1
;
3864 TIMx
->CCER
= tmpccer
;
3868 * @brief Configure the TI2 as Input.
3869 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
3871 * @param TIM_ICPolarity : The Input Polarity.
3872 * This parameter can be one of the following values:
3873 * @arg TIM_ICPolarity_Rising
3874 * @arg TIM_ICPolarity_Falling
3875 * @arg TIM_ICPolarity_BothEdge
3876 * @param TIM_ICSelection: specifies the input to be used.
3877 * This parameter can be one of the following values:
3878 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
3879 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
3880 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
3881 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3882 * This parameter must be a value between 0x00 and 0x0F.
3885 static void TI2_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
3886 uint16_t TIM_ICFilter
)
3888 uint32_t tmpccmr1
= 0, tmpccer
= 0, tmp
= 0;
3890 /* Disable the Channel 2: Reset the CC2E Bit */
3891 TIMx
->CCER
&= (uint16_t)~TIM_CCER_CC2E
;
3892 tmpccmr1
= TIMx
->CCMR1
;
3893 tmpccer
= TIMx
->CCER
;
3894 tmp
= (uint16_t)(TIM_ICPolarity
<< 4);
3896 /* Select the Input and set the filter */
3897 tmpccmr1
&= ((uint32_t)~TIM_CCMR1_CC2S
) & ((uint32_t)~TIM_CCMR1_IC2F
);
3898 tmpccmr1
|= (uint32_t)((uint32_t)TIM_ICFilter
<< 12);
3899 tmpccmr1
|= (uint32_t)((uint32_t)TIM_ICSelection
<< 8);
3901 /* Select the Polarity and set the CC2E Bit */
3902 tmpccer
&= (uint16_t)~(TIM_CCER_CC2P
| TIM_CCER_CC2NP
);
3903 tmpccer
|= (uint16_t)(tmp
| (uint16_t)TIM_CCER_CC2E
);
3905 /* Write to TIMx CCMR1 and CCER registers */
3906 TIMx
->CCMR1
= tmpccmr1
;
3907 TIMx
->CCER
= tmpccer
;
3911 * @brief Configure the TI3 as Input.
3912 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
3913 * @param TIM_ICPolarity : The Input Polarity.
3914 * This parameter can be one of the following values:
3915 * @arg TIM_ICPolarity_Rising
3916 * @arg TIM_ICPolarity_Falling
3917 * @arg TIM_ICPolarity_BothEdge
3918 * @param TIM_ICSelection: specifies the input to be used.
3919 * This parameter can be one of the following values:
3920 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
3921 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
3922 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
3923 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3924 * This parameter must be a value between 0x00 and 0x0F.
3927 static void TI3_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
3928 uint16_t TIM_ICFilter
)
3930 uint16_t tmpccmr2
= 0, tmpccer
= 0, tmp
= 0;
3932 /* Disable the Channel 3: Reset the CC3E Bit */
3933 TIMx
->CCER
&= (uint16_t)~TIM_CCER_CC3E
;
3934 tmpccmr2
= TIMx
->CCMR2
;
3935 tmpccer
= TIMx
->CCER
;
3936 tmp
= (uint16_t)(TIM_ICPolarity
<< 8);
3938 /* Select the Input and set the filter */
3939 tmpccmr2
&= ((uint16_t)~TIM_CCMR1_CC1S
) & ((uint16_t)~TIM_CCMR2_IC3F
);
3940 tmpccmr2
|= (uint16_t)(TIM_ICSelection
| (uint16_t)(TIM_ICFilter
<< (uint16_t)4));
3942 /* Select the Polarity and set the CC3E Bit */
3943 tmpccer
&= (uint16_t)~(TIM_CCER_CC3P
| TIM_CCER_CC3NP
);
3944 tmpccer
|= (uint16_t)(tmp
| (uint16_t)TIM_CCER_CC3E
);
3946 /* Write to TIMx CCMR2 and CCER registers */
3947 TIMx
->CCMR2
= tmpccmr2
;
3948 TIMx
->CCER
= tmpccer
;
3952 * @brief Configure the TI4 as Input.
3953 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
3954 * @param TIM_ICPolarity : The Input Polarity.
3955 * This parameter can be one of the following values:
3956 * @arg TIM_ICPolarity_Rising
3957 * @arg TIM_ICPolarity_Falling
3958 * @arg TIM_ICPolarity_BothEdge
3959 * @param TIM_ICSelection: specifies the input to be used.
3960 * This parameter can be one of the following values:
3961 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
3962 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
3963 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
3964 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3965 * This parameter must be a value between 0x00 and 0x0F.
3968 static void TI4_Config(TIM_TypeDef
* TIMx
, uint16_t TIM_ICPolarity
, uint16_t TIM_ICSelection
,
3969 uint16_t TIM_ICFilter
)
3971 uint16_t tmpccmr2
= 0, tmpccer
= 0, tmp
= 0;
3973 /* Disable the Channel 4: Reset the CC4E Bit */
3974 TIMx
->CCER
&= (uint16_t)~TIM_CCER_CC4E
;
3975 tmpccmr2
= TIMx
->CCMR2
;
3976 tmpccer
= TIMx
->CCER
;
3977 tmp
= (uint16_t)(TIM_ICPolarity
<< 12);
3979 /* Select the Input and set the filter */
3980 tmpccmr2
&= ((uint16_t)~TIM_CCMR1_CC2S
) & ((uint16_t)~TIM_CCMR1_IC2F
);
3981 tmpccmr2
|= (uint16_t)(TIM_ICSelection
<< 8);
3982 tmpccmr2
|= (uint16_t)(TIM_ICFilter
<< 12);
3984 /* Select the Polarity and set the CC4E Bit */
3985 tmpccer
&= (uint16_t)~(TIM_CCER_CC4P
| TIM_CCER_CC4NP
);
3986 tmpccer
|= (uint16_t)(tmp
| (uint16_t)TIM_CCER_CC4E
);
3988 /* Write to TIMx CCMR2 and CCER registers */
3989 TIMx
->CCMR2
= tmpccmr2
;
3990 TIMx
->CCER
= tmpccer
;
4005 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/