tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c

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  33
  34 #include "rtc_api.h"
  35 #include "cmsis.h"
  36 #include "rtc_regs.h"
  37 #include "pwrseq_regs.h"
  38 #include "clkman_regs.h"
  39
  40 static int rtc_inited = 0;
  41 static volatile uint32_t overflow_cnt = 0;
  42 static uint32_t overflow_alarm = 0;
  43
  44 //******************************************************************************
  45 static void overflow_handler(void)
  46 {
  47     MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
  48     overflow_cnt++;
  49
  50     if (overflow_cnt == overflow_alarm) {
  51         // Enable the comparator interrupt for the alarm
  52         MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0;
  53     }
  54 }
  55
  56 //******************************************************************************
  57 static void alarm_handler(void)
  58 {
  59     MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
  60     MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
  61 }
  62
  63 //******************************************************************************
  64 void rtc_init(void)
  65 {
  66     if(rtc_inited) {
  67         return;
  68     }
  69     rtc_inited = 1;
  70
  71     // Enable the clock to the synchronizer
  72     MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
  73
  74     // Enable the clock to the RTC
  75     MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
  76
  77     // Set the divider from the 4kHz clock
  78     MXC_RTCTMR->prescale = MXC_E_RTC_PRESCALE_DIV_2_0;
  79
  80     // Enable the overflow interrupt
  81     MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
  82
  83     // Prepare interrupt handlers
  84     NVIC_SetVector(RTC0_IRQn, (uint32_t)alarm_handler);
  85     NVIC_EnableIRQ(RTC0_IRQn);
  86     NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
  87     NVIC_EnableIRQ(RTC3_IRQn);
  88
  89     // Enable the RTC
  90     MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
  91 }
  92
  93 //******************************************************************************
  94 void rtc_free(void)
  95 {
  96     if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
  97         // Clear and disable RTC
  98         MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
  99         MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
 100
 101         // Wait for pending transactions
 102         while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
 103     }
 104
 105     // Disable the clock to the RTC
 106     MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
 107
 108     // Disable the clock to the synchronizer
 109     MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED;
 110 }
 111
 112 //******************************************************************************
 113 int rtc_isenabled(void)
 114 {
 115     return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
 116 }
 117
 118 //******************************************************************************
 119 time_t rtc_read(void)
 120 {
 121     unsigned int shift_amt;
 122     uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
 123
 124     // Account for a change in the default prescaler
 125     shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
 126
 127     // Ensure coherency between overflow_cnt and timer
 128     do {
 129         ovf_cnt_1 = overflow_cnt;
 130         timer_cnt = MXC_RTCTMR->timer;
 131         ovf_cnt_2 = overflow_cnt;
 132     } while (ovf_cnt_1 != ovf_cnt_2);
 133
 134     return (timer_cnt >> shift_amt) + (ovf_cnt_1 << (32 - shift_amt));
 135 }
 136
 137 //******************************************************************************
 138 uint64_t rtc_read_us(void)
 139 {
 140     unsigned int shift_amt;
 141     uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
 142     uint64_t currentUs;
 143
 144     // Account for a change in the default prescaler
 145     shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
 146
 147     // Ensure coherency between overflow_cnt and timer
 148     do {
 149         ovf_cnt_1 = overflow_cnt;
 150         timer_cnt = MXC_RTCTMR->timer;
 151         ovf_cnt_2 = overflow_cnt;
 152     } while (ovf_cnt_1 != ovf_cnt_2);
 153
 154     currentUs = (((uint64_t)timer_cnt * 1000000) >> shift_amt) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - shift_amt));
 155
 156     return currentUs;
 157 }
 158
 159 //******************************************************************************
 160 void rtc_write(time_t t)
 161 {
 162     // Account for a change in the default prescaler
 163     unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
 164
 165     MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
 166     MXC_RTCTMR->timer = t << shift_amt;
 167     overflow_cnt = t >> (32 - shift_amt);
 168     MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;  // enable the timer while updating
 169 }
 170
 171 //******************************************************************************
 172 void rtc_set_wakeup(uint64_t wakeupUs)
 173 {
 174     // Account for a change in the default prescaler
 175     unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
 176
 177     // Disable the alarm while it is prepared
 178     MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
 179     MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0;      // clear interrupt
 180
 181     overflow_alarm = (wakeupUs >> (32 - shift_amt)) / 1000000;
 182
 183     if (overflow_alarm == overflow_cnt) {
 184         MXC_RTCTMR->comp[0] = (wakeupUs << shift_amt) / 1000000;
 185         MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0;
 186     }
 187
 188     // Enable wakeup from RTC
 189     MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER | MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0);
 190 }